Datasheet W78E52C, W78E052C Datasheet (winbond)

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W78E52C/W78E052C Data Sheet

8-BIT MICROCONTROLLER

Table of Contents-

1. GENERAL DESCRIPTION ......................................................................................................... 2

2. FEATURES ................................................................................................................................. 2

3. PIN CONFIGURATIONS ............................................................................................................ 3

4. PIN DESCRIPTION..................................................................................................................... 4

5. FUNCTIONAL DESCRIPTION ................................................................................................... 5

5.1 Timers 0, 1, and 2........................................................................................................... 5

5.2 New Defined Peripheral.................................................................................................. 5

5.3 Watchdog Timer ............................................................................................................. 7

5.4 Clock ............................................................................................................................... 9

5.5 Power Management........................................................................................................ 9

5.6 Reset............................................................................................................................... 9

6. SECURITY BITS ....................................................................................................................... 10

6.1 Lock Bit ......................................................................................................................... 10

6.2 MOVC Inhibit................................................................................................................. 10

6.3 Encryption ..................................................................................................................... 10

7. ELECTRICAL CHARACTERISTICS......................................................................................... 11

7.1 Absolute Maximum Ratings .......................................................................................... 11

7.2 D.C. Characteristics...................................................................................................... 11

7.3 A.C. Characteristics ...................................................................................................... 13

8. TIMING WAVEFORMS ............................................................................................................. 16

8.1 Program Fetch Cycle .................................................................................................... 16

8.2 Data Read Cycle........................................................................................................... 16

8.3 Data Write Cycle........................................................................................................... 17

8.4 Port Access Cycle......................................................................................................... 17

9. TYPICAL APPLICATION CIRCUITS ........................................................................................ 18

9.1 Expanded External Program Memory and Crystal ....................................................... 18

9.2 Expanded External Data Memory and Oscillator ......................................................... 19

10. PACKAGE DIMENSIONS......................................................................................................... 20

10.1 40-pin DIP ..................................................................................................................... 20

10.2 44-pin PLCC ................................................................................................................. 20

10.3 44-pin PQFP ................................................................................................................. 21

11. REVISION HISTORY ................................................................................................................22

Publication Release Date: November 6, 2006

- 1 - Revision A4

W78E52C/W78E052C

1. GENERAL DESCRIPTION

The W78E052C is an 8-bit microcontroller which can accommodate a wider frequency range with low
power consumption. The instruction set for the W78E052C is fully compatible with the standard 8051.
The W78E052C contains an 8K bytes Flash EPROM; a 256 bytes RAM; four 8-bit bi-directional and
bit-addressable I/O ports; an additional 4-bit I/O port P4; three 16-bit timer/counters; a hardware
watchdog timer and a serial port. These peripherals are supported by eight sources two-level interrupt
capability. To facilitate programming and verification, the Flash EPROM inside the W78E052C allows
the program memory to be programmed and read electronically. Once the code is confirmed, the user
can protect the code for security.

The W78E052C microcontroller has two power reduction modes, idle mode and power-down mode,
both of which are software selectable. The idle mode turns off the processor clock but allows for
continued peripheral operation. The power-down mode stops the crystal oscillator for minimum power
consumption. The external clock can be stopped at any time and in any state without affecting the
processor.

2. FEATURES

• Fully static design 8-bit CMOS microcontroller

• Wide supply voltage of 4.5V to 5.5V

• 256 bytes of on-chip scratchpad RAM

• 8 KB On-chip Flash EPROM

• 64 KB program memory address space

• 64 KB data memory address space

• Four 8-bit bi-directional ports

• One extra 4-bit bit-addressable I/O port, additional

(available on 44-pin PLCC/QFP package)

• Three 16-bit timer/counters

• One full duplex serial port(UART)

• Watchdog Timer

• Eight sources, two-level interrupt capability

• EMI reduction mode

• Built-in power management

• Code protection mechanism

• Packages:

− Lead Free (RoHS) DIP 40: W78E052C40DL

− Lead Free (RoHS) PLCC 44: W78E052C40PL

− Lead Free (RoHS) PQFP 44: W78E052C40FL

INT2 / INT3

- 2 -

3. PIN CONFIGURATIONS

W78E52C/W78E052C

Publication Release Date: November 6, 2006

- 3 - Revision A4

W78E52C/W78E052C

A

A

4. PIN DESCRIPTION

SYMBOL DESCRIPTIONS

EXTERNAL ACCESS ENABLE: This pin forces the processor to execute out of

E

PSEN

ALE

RST

XTAL1

XTAL2

VSS

VDD

P0.0−P0.7

P1.0−P1.7

P2.0−P2.7

P3.0−P3.7

P4.0-P4.3

external ROM. It should be kept high to access internal ROM. The ROM address and
data will not be presented on the bus if

within on-chip ROM area.

PROGRAM STORE ENABLE:
address/ data bus during fetch and MOVC operations. When internal ROM access is

performed, no

ADDRESS LATCH ENABLE: ALE is used to enable the address latch that separates
the address from the data on Port 0.

RESET: A high on this pin for two machine cycles while the oscillator is running resets
the device.

CRYSTAL1: This is the crystal oscillator input. This pin may be driven by an external
clock.

CRYSTAL2: This is the crystal oscillator output. It is the inversion of XTAL1.

GROUND: Ground potential

POWER SUPPLY: Supply voltage for operation.

PORT 0: Port 0 is a bi-directional I/O port which also provides a multiplexed low order

address/data bus during accesses to external memory. The Port 0 is also an open­drain port and external pull-ups need to be connected while in programming.

PORT 1: Port 1 is a bi-directional I/O port with internal pull-ups. The bits have alternate
functions which are described below:

T2(P1.0): Timer/Counter 2 external count input

T2EX(P1.1): Timer/Counter 2 Reload/Capture control

PORT 2: Port 2 is a bi-directional I/O port with internal pull-ups. This port also provides
the upper address bits for accesses to external memory.

PORT 3: Port 3 is a bi-directional I/O port with internal pull-ups. All bits have alternate
functions, which are described below:

RXD(P3.0) : Serial Port receiver input
TXD(P3.1) : Serial Port transmitter output

INT0 (P3.2) : External Interrupt 0

INT1(P3.3) : External Interrupt 1

T0(P3.4) : Timer 0 External Input
T1(P3.5) : Timer 1 External Input

WR (P3.6) : External Data Memory Write Strobe

RD

(P3.7) : External Data Memory Read Strobe

PORT 4: Another bit-addressable bidirectional I/O port P4. P4.3 and P4.2 are alternative
function pins. It can be used as general I/O port or external interrupt input sources

INT2 /INT3 ).

(

PSEN strobe signal outputs from this pin.

PSEN

E

pin is high and the program counter is

enables the external ROM data onto the Port 0

- 4 -

W78E52C/W78E052C

5. FUNCTIONAL DESCRIPTION

The W78E052C architecture consists of a core controller surrounded by various registers, five general
purpose I/O ports, 256 bytes of RAM, three timer/counters, and a serial port. The processor supports
111 different opcodes and references both a 64K program address space and a 64K data storage
space.

5.1 Timers 0, 1, and 2

Timers 0, 1, and 2 each consist of two 8-bit data registers. These are called TL0 and TH0 for Timer 0,
TL1 and TH1 for Timer 1, and TL2 and TH2 for Timer 2. The TCON and TMOD registers provide
control functions for timers 0 and 1. The T2CON register provides control functions for Timer 2.
RCAP2H and RCAP2L are used as reload/capture registers for Timer 2.

The operations of Timer 0 and Timer 1 are the same as in the W78C51. Timer 2 is a special feature of
the W78E54B: it is a 16-bit timer/counter that is configured and controlled by the T2CON register. Like
Timers 0 and 1, Timer 2 can operate as either an external event counter or as an internal timer,
depending on the setting of bit C/T2 in T2CON. Timer 2 has three operating modes: capture, auto­reload, and baud rate generator. The clock speed at capture or auto-reload mode is the same as that
of Timers 0 and 1.

5.2 New Defined Peripheral

In order to be more suitable for I/O, an extra 4-bit bit-addressable port P4 and two external interrupt

INT2

, INT3 has been added to either the PLCC or QFP 44 pin package. And description follows:

INT2 / NT3I

Two additional external interrupts, INT2 and INT3 , whose functions are similar to those of external
interrupt 0 and 1 in the standard 80C52. The functions/status of these interrupts are
determined/shown by the bits in the XICON (External Interrupt Control) register. The XICON register is
bit-addressable but is not a standard register in the standard 80C52. Its address is at 0C0H. To
set/clear bits in the XICON register, one can use the "SETB (/CLR) bit" instruction. For example,
"SETB 0C2H" sets the EX2 bit of XICON.

XICON - external interrupt control (C0H)

PX3 EX3 IE3 IT3 PX2 EX2 IE2 IT2

PX3: External interrupt 3 priority high if set

EX3: External interrupt 3 enable if set

IE3: If IT3 = 1, IE3 is set/cleared automatically by hardware when interrupt is detected/serviced

IT3: External interrupt 3 is falling-edge/low-level triggered when this bit is set/cleared by software

PX2: External interrupt 2 priority high if set

EX2: External interrupt 2 enable if set

IE2: If IT2 = 1, IE2 is set/cleared automatically by hardware when interrupt is detected/serviced

IT2: External interrupt 2 is falling-edge/low-level triggered when this bit is set/cleared by software

Publication Release Date: November 6, 2006

- 5 - Revision A4

Eight-source interrupt information:

W78E52C/W78E052C

INTERRUPT SOURCE

External Interrupt 0 03H 0 (highest) IE.0 TCON.0

Timer/Counter 0 0BH 1 IE.1 -

External Interrupt 1 13H 2 IE.2 TCON.2

Timer/Counter 1 1BH 3 IE.3 -

Serial Port 23H 4 IE.4 -

Timer/Counter 2 2BH 5 IE.5 -

External Interrupt 2 33H 6 XICON.2 XICON.0

External Interrupt 3 3BH 7 (lowest) XICON.6 XICON.3

VECTOR

ADDRESS

POLLING

SEQUENCE WITHIN

PRIORITY LEVEL

ENABLE

REQUIRED

SETTINGS

INTERRUPT

TYPE

EDGE/LEVEL

PORT4

Another bit-addressable port P4 is also available and only 4 bits (P4<3:0>) can be used. This port
address is located at 0D8H with the same function as that of port P1, except the P4.3 and P4.2 are

alternative function pins. It can be used as general I/O pins or external interrupt input sources (

INT3 ).

Example:
P4 REG 0D8H
MOV P4, #0AH ; Output data "A" through P4.0−P4.3.

MOV A, P4 ; Read P4 status to Accumulator.
ORL P4,#00000001B ; Set bit P4.0

ANL P4,#11111101B ; Clear bit P4.1

INT2 ,

Reduce EMI Emission

Because of on-chip ROM, when a program is running in internal ROM space, the ALE will be unused.
The transition of ALE will cause noise, so it can be turned off to reduce the EMI emission if it is
useless. Turning off the ALE signal transition only requires setting the bit 0 of the AUXR SFR, which is
located at 08Eh. When ALE is turned off, it will be reactivated when the program accesses external
ROM/RAM data or jumps to execute an external ROM code. The ALE signal will turn off again after it
has been completely accessed or the program returns to internal ROM code space. The AO bit in the
AUXR register, when set, disables the ALE output. In order to reduce EMI emission from oscillation
circuitry, W78E052C allows user to diminish the gain of on-chip oscillator amplifiers by using
programmer to clear the B7 bit of security register. Once B7 is set to 0, a half of gain will be
decreased. Care must be taken if user attempts to diminish the gain of oscillator amplifier, reducing a
half of gain may affect the external crystal operating improperly at high frequency above 24 MHz. The
value of R and C1,C2 may need some adjustment while running at lower gain.

- 6 -

W78E52C/W78E052C

***AUXR - Auxiliary register (8EH)

- - - - - - - AO

AO: Turn off ALE output.

Power-off Flag

***PCON - Power control (87H)

- -

POF: Power off flag. Bit is set by hardware when power on reset. It can be cleared by software
to determine chip reset is a warm boot or cold boot.

GF1, GF0: These two bits are general-purpose flag bits for the user.

PD: Power down mode bit. Set it to enter power down mode.

IDL: Idle mode bit. Set it to enter idle mode.

The power-off flag is located at PCON.4. This bit is set when V
be used to determine if a reset is a warm boot or a cold boot if it is subsequently reset by software.

-

POF

GF1 GF0 PD IDL

DD has been applied to the part. It can

5.3 Watchdog Timer

The Watchdog timer is a free-running timer which can be programmed by the user to serve as a
system monitor, a time-base generator or an event timer. It is basically a set of dividers that divide the
system clock. The divider output is selectable and determines the time-out interval. When the time-out
occurs a system reset can also be caused if it is enabled. The main use of the Watchdog timer is as a
system monitor. This is important in real-time control applications. In case of power glitches or electro­magnetic interference, the processor may begin to execute errant code. If this is left unchecked the
entire system may crash. The watchdog time-out selection will result in different time-out values
depending on the clock speed. The Watchdog timer will de disabled on reset. In general, software
should restart the Watchdog timer to put it into a known state. The control bits that support the
Watchdog timer are discussed below.

Watchdog Timer Control Register

Bit: 7 6 5 4 3 2 1 0

ENW CLRW WIDL - - PS2 PS1 PS0

Mnemonic: WDTC Address: 8FH

ENW : Enable watch-dog if set.
CLRW : Clear watch-dog timer and prescaler if set. This flag will be cleared automatically
WIDL : If this bit is set, watch-dog is enabled under IDLE mode. If cleared, watch-dog is disabled
under IDLE mode. Default is cleared.

Publication Release Date: November 6, 2006

- 7 - Revision A4

W78E52C/W78E052C

PS2, PS1, PS0: Watch-dog prescaler timer select. Prescaler is selected when set PS2~0 as follows:

PS2 PS1 PS0 PRESCALER SELECT

0 0 0 2

0 0 1 4

0 1 0 8

0 1 1 16

1 0 0 32

1 0 1 64

1 1 0 128

1 1 1 256

The time-out period is obtained using the following equation:

1

14

2 PRESCALER 1000 12 mS

×× × ×

OSC

Before Watchdog time-out occurs, the program must clear the 14-bit timer by writing 1 to WDTC.6
(CLRW). After 1 is written to this bit, the 14-bit timer, prescaler and this bit will be reset on the next
instruction cycle. The Watchdog timer is cleared on reset.

WIDL

IDLE

OSC 1/12

Watchdog Timer Block Diagram

ENW

PRESCALER

CLRW

EXTERNAL

RESET

14-BIT TIMER

CLEAR

INTERNAL

RESET

- 8 -

W78E52C/W78E052C

Typical Watch-Dog time-out period when OSC = 20 MHz

PS2 PS1 PS0 WATCHDOG TIME-OUT PERIOD

0 0 0 19.66 mS

0 0 1 39.32 mS

0 1 0 78.64 mS

0 1 1 157.28 mS

1 0 0 314.57 mS

1 0 1 629.14 mS

1 1 0 1.25 S

1 1 1 2.50 S

5.4 Clock

The W78E052C is designed to be used with either a crystal oscillator or an external clock. Internally,
the clock is divided by two before it is used. This makes the W78E052C relatively insensitive to duty
cycle variations in the clock. The W78E052C incorporates a built-in crystal oscillator. To make the
oscillator work, a crystal must be connected across pins XTAL1 and XTAL2. In addition, a load
capacitor must be connected from each pin to ground. An external clock source should be connected
to pin XTAL1. Pin XTAL2 should be left unconnected. The XTAL1 input is a CMOS-type input, as
required by the crystal oscillator.

5.5 Power Management

Idle Mode

The idle mode is entered by setting the IDL bit in the PCON register. In the idle mode, the internal
clock to the processor is stopped. The peripherals and the interrupt logic continue to be clocked. The
processor will exit idle mode when either an interrupt or a reset occurs.

Power-down Mode

When the PD bit of the PCON register is set, the processor enters the power-down mode. In this
mode all of the clocks are stopped, including the oscillator. The only way to exit power-down mode is
by a reset.

5.6 Reset

The external RESET signal is sampled at S5P2. To take effect, it must be held high for at least two
machine cycles while the oscillator is running. An internal trigger circuit in the reset line is used to
deglitch the reset line when the W78E052C is used with an external RC network. The reset logic also
has a special glitch removal circuit that ignores glitches on the reset line.

During reset, the ports are initialized to FFH, the stack pointer to 07H, PCON (with the exception of bit

4) to 00H, and all of the other SFR registers except SBUF to 00H. SBUF is not reset.

Publication Release Date: November 6, 2006

- 9 - Revision A4

W78E52C/W78E052C

6. SECURITY BITS

During the on-chip Flash EPROM operation mode, the ROM can be programmed and verified
repeatedly. Until the code inside the ROM is confirmed OK, the code can be protected. The protection
of ROM and those operations on it are described below.

The W78E052C has a Security Register which can not be accessed in normal mode. These registers
can only be accessed from the Flash EPROM operation mode. Those bits of the Security Register can
not be changed once they have been programmed from high to low. They can only be reset through
erase-all operation. The Security Register is addressed in the Flash EPROM operation mode by
address #0FFFFh.

0000h

8KB On-chip ROM

Program Memory

Reserved

B7

B0 : Lock bit, logic 0 : active

B1 : MOVC inhibit,
logic 0 : the MOVC instruction in external memory
cannot access the code in internal memory.
logic 1 : no restriction.

B2 : Encryption
logic 0 : the encryption logic enable
logic 1 : the encryption logic disable

B7 : Osillator Control

logic 0 : 1/2 gain
logic 1 : Full gain
Default 1 for all security bits.

B2

Reserved bits must be kept in logic 1.

Security Bits

B0B1

Special Setting Register

Reserved

Security Register

1FFFh

0FFFFh

6.1 Lock Bit

This bit is used to protect the customer's program code in the W78E052C. It may be set after the
programmer finishes the programming and verifies sequence. Once this bit is set to logic 0, both the
ROM data and Special Setting Register can not be accessed again.

6.2 MOVC Inhibit

This bit is used to restrict the accessible region of the MOVC instruction. It can prevent the MOVC
instruction in external program memory from reading the internal program code. When this bit is set to
logic 0, a MOVC instruction in external program memory space will be able to access code only in the
external memory, not in the internal memory. A MOVC instruction in internal program memory space
will always be able to access the ROM data in both internal and external memory. If this bit is logic 1,
there are no restrictions on the MOVC instruction.

6.3 Encryption

This bit is used to enable/disable the encryption logic for code protection. Once encryption feature is
enabled, the data presented on port 0 will be encoded via encryption logic. Only whole chip erase will
reset this bit.

- 10 -

7. ELECTRICAL CHARACTERISTICS

7.1 Absolute Maximum Ratings

PARAMETER SYMBOL MIN. MAX. UNIT

W78E52C/W78E052C

DC Power Supply

V

DD−VSS

-0.3 +7.0 V

Input Voltage VIN VSS -0.3 VDD +0.3 V

Operating Temperature TA 0 70

Storage Temperature TST -55 +150

Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability

of the device.

°C

°C

7.2 D.C. Characteristics

(VCC−VSS = 5V ±10%, TA = 25° C, unless otherwise specified.)

PARAMETER SYMBOL TEST CONDITIONS

Operating Voltage VDD

Operating Current IDD No load VDD = 5.5V - 20 mA

Idle Current IIDLE

Idle mode V

DD =

5.5V

Power-down mode

Power Down Current IPWDN

V

DD = 5.5V

Input Current

P1, P2, P3

Logical 1-to-0 Transition

Current P1, P2, P3

(*1)

Input Current

(*2)

RST

Input Leakage Current

P0,

EA

Output Low Voltage

P1, P2, P3

Output Low Voltage

ALE,

INT1

, P0

(*3)

Output High Voltage

P1, P2, P3

I

I

I

I

V

V

V

IN1

TL

IN2

LK

OL1

OL2

OH1

V

DD = 5.5V

V

IN

= 0V or V

DD = 5.5V

V

IN = 2.0V

V

V

DD = 5.5V

V

IN

DD

= V

V

DD = 5.5V

0V < V

IN < VDD

V

DD = 4.5V

I

= +2 mA

OL1

V

DD = 4.5V

I

OL2

= +4 mA

V

DD = 4.5V

OH1 = -100 µA

I

(*1)

DD

SPECIFICATION

MIN. MAX.

UNIT

4.5 5.5 V

- 6 mA

- 50

-50 +10

-550 -

-10 +300

-10 +10

µA

µA

µA

µA

µA

- 0.45 V

- 0.45 V

2.4 - V

Publication Release Date: November 6, 2006

- 11 - Revision A4

DC Characteristics, continued

W78E52C/W78E052C

PARAMETER SYMBOL TEST CONDITIONS

Output High Voltage

ALE,

PSEN , P0

(*3)

V

OH2

OH2

I

DD

V

Input Low Voltage

V

IL1 VDD = 4.5V 0 0.8 V

(Except RST)

Input Low Voltage

V

RST

(*4)

IL2 VDD = 4.5V 0 0.8 V

Input Low Voltage

V

XTAL1

(*4)

IL3 VDD = 4.5V 0 0.8 V

Input High Voltage

V

IH1 VDD = 4.5V 2.4 VDD +0.2 V

(Except RST)

Sink Current

P1, P2, P3, P4

I

SK1

V

DD = 4.5V

V

S = 0.45V

Input High Voltage

V

RST

(*4)

IH2 VDD

Input High Voltage

V

XTAL1

(*4)

Sink Current

P0, ALE, PSEN

(*3)

IH3 VDD = 4.5V 0.67 V

V

I

SK2

DD = 4.5V

V

S = 0.45V

= 4.5V

= -400 µA

= 4.5V 0.67 V

SPECIFICATION

UNIT

MIN. MAX.

2.4 - V

4 12 mA

VDD +0.2 V

DD

VDD +0.2 V

DD

8 16 mA

V

Source Current

I

SR1

P1, P2, P3, P4

Source Current

SR2

P0, ALE,

Notes:

*1. Pins P1, P2 and P3 source a transition current when they are being externally driven from 1 to 0. The transition current

*2. RST pin has an internal pull-down resistor.

*3. P0, ALE,
*4. XTAL1 is a CMOS input and RST is a Schmitt trigger input.

PSEN

reaches its maximum value when V

(*3)

are in the external access memory mode.

PSEN

I

IN is approximately 2V.

DD = 4.5V

S

= 2.4V

V

DD = 4.5V

V

V

= 2.4V

-100 -250 uA

-8 -14 mA

- 12 -

W78E52C/W78E052C

7.3 A.C. Characteristics

The AC specifications are a function of the particular process used to manufacture the part, the
ratings of the I/O buffers, the capacitive load, and the internal routing capacitance. Most of the
specifications can be expressed in terms of multiple input clock periods (T
usually experience less than a ±20 nS variation. The numbers below represent the performance
expected from a 0.6micron CMOS process when using 2 and 4 mA output buffers.

Clock Input Waveform

XTAL1

T

CH

T

CP), and actual parts will

CL

F

OP,

T

CP

PARAMETER SYMBOL MIN. TYP. MAX. UNIT NOTES

Operating Speed FOP 0 - 40 MHz 1

Clock Period TCP 25 - - nS 2

Clock High TCH 10 - - nS 3

Clock Low TCL 10 - - nS 3

Notes:

1. The clock may be stopped indefinitely in either state.

2. The T

3. There are no duty cycle requirements on the XTAL1 input.

CP specification is used as a reference in other specifications.

Publication Release Date: November 6, 2006

- 13 - Revision A4

Program Fetch Cycle

PARAMETER SYMBOL MIN. TYP. MAX. UNIT NOTES

W78E52C/W78E052C

Address Valid to ALE Low TAAS

Address Hold from ALE Low TAAH

T

ALE Low to

RES

PSEN

Low

Low to Data Valid

Data Hold after PSEN High

Data Float after PSEN High

APL

T

PDA - - 2 TCP nS 2

PDH 0 - 1 TCP nS 3

T

PDZ 0 - 1 TCP nS

T

ALE Pulse Width TALW

PSW

PSEN Pulse Width

Notes:

1. P0.0−P0.7, P2.0−P2.7 remain stable throughout entire memory cycle.

2. Memory access time is 3 T

3. Data have been latched internally prior to

4. "∆

" (due to buffer driving delay and wire loading) is 20 nS.

CP.

T

PSEN going high.

1 T

1 T

1 T

2 T

3 T

CP -∆

CP -∆

CP -∆

CP -∆

CP -∆

Data Read Cycle

PARAMETER SYMBOL MIN. TYP. MAX. UNIT NOTES

DAR

ALE Low to RD Low

RD Low to Data Valid

Data Hold from RD High

T

DDA - - 4 TCP nS 1

T

DDH 0 - 2 TCP nS

T

3 T

CP -∆

- - nS 4

- - nS 1, 4

- - nS 4

CP - nS 4

2 T

CP - nS 4

3 T

-

3 TCP +∆

nS 1, 2

DDZ 0 - 2 TCP nS

Data Float from RD High

RD Pulse Width

Notes:

1. Data memory access time is 8 TCP.

2. "

∆" (due to buffer driving delay and wire loading) is 20 nS.

T

DRD

T

6 T

CP -∆

Data Write Cycle

PARAMETER SYMBOL MIN. TYP. MAX. UNIT

DAW

ALE Low to WR Low

Data Valid to WR Low

Data Hold from WR High

WR Pulse Width

Note: "∆" (due to buffer driving delay and wire loading) is 20 nS.

T

DAD

T

DWD

T

DWR

T

- 14 -

CP - nS 2

6 T

3 T

1 T

1 T

6 T

CP -∆

CP -∆

CP -∆

CP -∆

-

3 TCP +∆

- - nS

- - nS

CP - nS

6 T

nS

W78E52C/W78E052C

Port Access Cycle

PARAMETER SYMBOL MIN. TYP. MAX. UNIT

Port Input Setup to ALE Low TPDS 1 TCP - - nS

Port Input Hold from ALE Low TPDH 0 - - nS

Port Output to ALE TPDA 1 TCP - - nS

Note: Ports are read during S5P2, and output data becomes available at the end of S6P2. The timing data are referenced to

ALE, since it provides a convenient reference.

Program Operation

PARAMETER SYMBOL MIN. TYP. MAX. UNIT

VPP Setup Time TVPS 2.0 - -

Data Setup Time TDS 2.0 - -

Data Hold Time TDH 2.0 - -

Address Setup Time TAS 2.0 - -

Address Hold Time TAH 0 - -

CE Program Pulse Width for

Program Operation

T

PWP 290 300 310

OECTRL Setup Time TOCS 2.0 - -

OECTRL Hold Time TOCH 2.0 - -

OES 2.0 - -

OE Setup Time

OE

High to Output Float

Data Valid from OE

Note: Flash data can be accessed only in flash mode. The RST pin must pull in VIH status, the ALE pin must pull in VIL status,

and the

PSEN pin must pull in VIH status.

T

DFP 0 - 130 nS

T

OEV - - 150 nS

T

µS

µS

µS

µS

µS

µS

µS

µS

µS

Publication Release Date: November 6, 2006

- 15 - Revision A4

8. TIMING WAVEFORMS

8.1 Program Fetch Cycle

S1

S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6

XTAL1

ALE

PSEN

PORT 2

T

AAH

PORT 0

A0-A7

Code

W78E52C/W78E052C

T

ALW

T

APL

T

PSW

T

AAS

T

PDA

Data

T

PDH,TPDZ

A0-A7

Code

A0-A7

Data

A0-A7

8.2 Data Read Cycle

XTAL1

ALE

PSEN

PORT 2

PORT 0

RD

A0-A7

T

DAR

A8-A15

T

DDA

T

DRD

DATA

T

DDH,TDDZ

S2 S3S5 S6 S1S2 S3 S4S5 S6 S1S4

- 16 -

Timing Waveforms, continued

8.3 Data Write Cycle

XTAL1

ALE

PSEN

W78E52C/W78E052C

S2 S3S5 S6 S1S2 S3 S4S1S5 S6S4

PORT 2

PORT 0

WR

8.4 Port Access Cycle

XTAL1

ALE

PORT

INPUT

SAMPLE

T

A8-A15

A0-A7

T

DAW

S5 S6 S1

T

T

PDHPDS

DAD

DATA OUT

T

DWR

T

DWD

T

PDA

DATA OUT

Publication Release Date: November 6, 2006

- 17 - Revision A4

W78E52C/W78E052C

9. TYPICAL APPLICATION CIRCUITS

9.1 Expanded External Program Memory and Crystal

V

DD

31

EA

19

XTAL1

R

18

XTAL2

9

C2

RST

INT0

12
13

INT1

14

T0

15

T1

1

P1.0

2

P1.1

3

P1.2

4

P1.3

5

P1.4

6

P1.5

7

P1.6

8

P1.7

W78E52B

P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7

P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7

RD
WR

PSEN

ALE
TXD

RXD

AD0

39

AD1

38

AD2

37
36

AD3
AD4

35

AD5

34

AD6

33

AD7

32

A8

21
22

A9

23

A10

24

A11

25

A12

26

A13
A14

27
28

A15

17
16
29
30
11
10

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7

GND

3

D0
D1
D2
D3
D4
D5
D6
D7

OC
G

74373

Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7

4
7
8
13
14
17
18

1

11

8.2 K

V

DD

10 u

CRYSTAL

C1

11

2
5
6
9
12
15
16
19

A0

A0
A1
A2
A3
A4
A5
A6
A7

A10
A11
A12
A13
A14
A15

GND

10

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15

CE

OE

27512

O0
O1
O2
O3
O4
O5
O6
O7

A1

9

A2

8

A3

7

A4

6

A5

5

A6

4

A7

3

A8

25

A9

24
21
23
2
26
27

1

20
22

AD0

12

AD1

13

AD2

15

AD3

16

AD4

17

AD5

18

AD6

19

AD7

CRYSTAL C1 C2 R

16 MHz 30P 30P -

24 MHz 15P 15P -

33 MHz 10P 10P 6.8K

40 MHz 5P 5P 4.7K

Above table shows the reference values for crystal applications (full gain).

Note:

C1, C2, R components refer to Figure A.

Figure A

- 18 -

Typical Application Circuits, continued

9.2 Expanded External Data Memory and Oscillator

V

OSCILLATOR

DD

31

EA

19

XTAL1

18

XTAL2

9

RST

INT0

12
13

INT1

14

T0

15

T1

1

P1.0

2

P1.1

3

P1.2

4

P1.3

5

P1.4

6

P1.5

7

P1.6

8

P1.7

W78E52B

P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7

P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7

RD

WR

PSEN

ALE
TXD

RXD

39

AD0
AD1

38

AD2

37

AD3

36

AD4

35

AD5

34
33

AD6

32

AD7

21

A8

22

A9

23

A10

24

A11

25

A12
A13

26

A14

27
28

17

16
29

30
11
10

AD0

AD1

AD2

AD3

AD4

AD5

AD6

AD7

GND

3

D0

4

D1

7

D2

8

D3

13

D4

14

D5

17

D6

18

D7

1

OC

11

G

74373

8.2 K

V

DD

10 u

W78E52C/W78E052C

A0

2

A0

Q0

A1

5

Q1

6

A2

Q2

9

A3

Q3

12

A4

Q4

15

A5

Q5

16

A6

Q6

19

A7

Q7

A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14

GND

10

A0

20256

A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14

CE

OE

WR

D0
D1
D2
D3
D4
D5
D6
D7

9
8
7
6
5
4

3
25
24
21
23

2
26

1

20
22
27

AD0

11

AD1

12

AD2

13

AD3

15

AD4

16

AD5

17

AD6

18

AD7

19

Figure B

Publication Release Date: November 6, 2006

- 19 - Revision A4

10. PACKAGE DIMENSIONS

10.1 40-pin DIP

40

1

E

1

S

A

2

A

L

D

B

e

1

B

1

W78E52C/W78E052C

Dimension in inch Dimension in mm

Symbol

A
A
A
B
B
c

21

D
E
E
e
L

a

e

20

Base Plane

1

A

Seating Plane

E

e

a

A

S

Notes:

1. Dimension D Max. & S include mold flash or
tie bar burrs.

c

2. Dimension E1 does not include interlead flash.

3. Dimension D & E1 include mold mismatch and
are determined at the mold parting line.

4. Dimension B1 does not include dambar
protrusion/intrusion.

5. Controlling dimension: Inches.

6. General appearance spec. should be based on
final visual inspection spec.

Nom.

Min.

0.010

1

0.155

0.150

2

0.016

0.018

0.050 1.27

1

0.010

0.008

2.055 2.070

0.6000.590

0.540

0.545

1

1

0.120

0.130

015

0.630 16.00

0.650

A

Min.

0.254

3.81

0.406

0.203

14.986

13.72

2.286 2.54 2.7940.090 0.100

3.048

Nom.

3.937

0.457

0.254

52.20

15.24

13.84

3.302

16.51

5.334

4.064

0.559

1.3721.219

0.356

52.58

15.494

13.97

3.556

17.01

2.286

Max. Max.

0.210

0.160

0.022

0.0540.048

0.014

0.610

0.550

0.110

0.140

0.670

0.090

.

150

10.2 44-pin PLCC

61

7

17

L

θ

Seating Plane

e

H

D

D

44 40

G

D

Dimension in inch Dimension in mm

Symbol

39

H

E

E

29

2818

2

A

A

b

b

1

1

A

y

G

E

c

A
A
A
b
b
c
D
E

e
G
G
H
H

L

y

Notes:

1. Dimension D & E do not include interlead
flash.

2. Dimension b1 does not include dambar

protrusion/intrusion.

3. Controlling dimension: Inches

4. General appearance spec. should be based
on final visual inspection spec.

Nom.

Min.

0.020

1

0.145

2

0.026

1

0.016

0.008

0.648

0.648

0.590

D

0.590

E

0.680

D

0.680

E

0.090

Max. Max.

0.185

0.150

0.155

0.028

0.032

0.022

0.018

0.010

0.014

0.653

0.658

0.653

0.658

BSC

0.050

0.630

0.610

0.6300.610

0.700

0.690

0.700

0.690

0.100

0.110

0.004

Min.

0.508

3.683

0.66

0.406

0.203

16.46

16.46

14.99

17.27

17.27

2.296

1.27

Nom.

3.81

0.711

0.457

0.254

16.59

16.59

15.49

15.4914.99

17.53

2.54

BSC

4.699

3.937

0.813

0.559

0.356

16.71

16.71

16.00

16.00

17.78

17.7817.53

2.794

0.10

- 20 -

Package Dimensions, continued

10.3 44-pin PQFP

H

D

D

44

1

11

12

e

b

Seating Plane

See Detail F

W78E52C/W78E052C

Dimension in inch

34

33

Symbol

A
A
A

b

1

2

c

D

E

EH

E

e

D

H

E

H
L

1

L

22

c

A

A

2

A

1

y

θ

L

1

L

Detail F

y

θ

Notes:

1. Dimension D & E do not include interlead
flash.

2. Dimension b does not include dambar
protrusion/intrusion.

3. Controlling dimension: Millimeter

4. General appearance spec. should be based
on final visual inspection spec.

Nom.

Min.

--- ---

---

0.01 0.02 0.25

0.002

0.081

0.075

0.01

0.014

0.006 0.152

0.394

0.390

0.390

0.025

0.031

0.510 13.45

0.520

0.520

0.510

0.025

0.031

0.063

0.051

0

Dimension in mm

Min.

---

0.05

1.90

0.25

9.9

9.9

0.635

12.95

12.95

0.65

Nom.

---

0.5

2.05

2.20

0.45

0.35

0.2540.101

10.00

10.1

10.1

10.00

0.952

0.80

13.2

13.45

13.2

0.8

0.95

1.6

1.905

0

0.08

Max. Max.

---

0.087

0.018

0.0100.004

0.398

0.3980.394

0.036

0.530

0.530

0.037

0.075 1.295

0.003

7

7

Publication Release Date: November 6, 2006

- 21 - Revision A4

W78E52C/W78E052C

11. REVISION HISTORY

VERSION DATE PAGE DESCRIPTION

A1 Nov. 26, 2004 - Initial issued

A2 April 20, 2005 23 Add Important Notice

A3 May 11, 2005 2 Add Lead Free (RoHS) parts

A4

November 6,

2006

Remove block diagram

2 Remove all Leaded parts

Important Notice

Winbond products are not designed, intended, authorized or warranted for use as components
in systems or equipment intended for surgical implantation, atomic energy control
instruments, airplane or spaceship instruments, transportation instruments, traffic signal
instruments, combustion control instruments, or for other applications intended to support or
sustain life. Further more, Winbond products are not intended for applications wherein failure
of Winbond products could result or lead to a situation wherein personal injury, death or
severe property or environmental damage could occur.

Winbond customers using or selling these products for use in such applications do so at their
own risk and agree to fully indemnify Winbond for any damages resulting from such improper
use or sales.

Headquarters

No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: [phone]
FAX: [phone]
http://www.winbond.com.tw/

Taipei Office

9F, No.480, Rueiguang Rd.,
Neihu District, Taipei, 114,
Taiwan, R.O.C.
TEL: [phone]
FAX: [phone]

Please note that all data and specifications are subject to change without notice.
All the trademarks of products and companies mentioned in this datasheet belong to their respective owners.

Winbond Electronics Corporation America

2727 North First Street, San Jose,
CA 95134, U.S.A.
TEL: [phone]
FAX: [phone]

Winbond Electronics Corporation Japan

7F Daini-ueno BLDG, 3-7-18
Shinyokohama Kohoku-ku,
Yokohama, 222-0033
TEL: [phone]
FAX: [phone]

Winbond Electronics (Shanghai) Ltd.

27F, 2299 Yan An W. Rd. Shanghai,

200336 China
TEL: [phone]
FAX: [phone]

Winbond Electronics (H.K.) Ltd.

Unit 9-15, 22F, Millennium City,
No. 378 Kwun Tong Rd.,
Kowloon, Hong Kong
TEL: [phone]
FAX: [phone]

- 22 -