Datasheet W78E52BP-40, W78E52BP-24, W78E52BF-40, W78E52BF-24, W78E52B-40 Datasheet (Winbond Electronics)

Preliminary W78E52B

INT2

8-BIT MTP MICROCONTROLLER

GENERAL DESCRIPTION

The W78E52B is an 8-bit microcontroller which can accommodate a wider frequency range with low power consumption. The instruction set for the W78E52B is fully compatible with the standard 8051. The W78E52B contains an 8K bytes MTP ROM (Multiple-Time Programmable ROM); a 256 bytes RAM; four 8-bit bi-directional and bit-addressable I/O ports; an additional 4-bit I/O port P4; three 16bit timer/counters; a hardware watchdog timer and a serial port. These peripherals are supported by eight sources two-level interrupt capability. To facilitate programming and verification, the MTP-ROM inside the W78E52B allows the program memory to be programmed and read electronically. Once the code is confirmed, the user can protect the code for security.

The W78E52B microcontroller has two power reduction modes, idle mode and power-down mode, both of which are software selectable. The idle mode turns off the processor clock but allows for continued peripheral operation. The power-down mode stops the crystal oscillator for minimum power consumption. The external clock can be stopped at any time and in any state without affecting the processor.

FEATURES

• Fully static design 8-bit CMOS microcontroller

• Wide supply voltage of 4.5V to 5.5V

• 256 bytes of on-chip scratchpad RAM

• 8 KB electrically erasable/programmable MTP-ROM

• 64 KB program memory address space

• 64 KB data memory address space

• Four 8-bit bi-directional ports

•One extra 4-bit bit-addressable I/O port, additional

(available on 44-pin PLCC/QFP package)

• Three 16-bit timer/counters

• One full duplex serial port(UART)

• Watchdog Timer

• Eight sources, two-level interrupt capability

• EMI reduction mode

• Built-in power management

• Code protection mechanism

• Packages:

− DIP 40: W78E52B-24/40

− PLCC 44: W78E52BP-24/40

− PQFP 44: W78E52BF-24/40

- 1 - Revision A1

/ INT3

Publication Release Date: December 1998

PIN CONFIGURATIONS

40-Pin DIP (W78E52B)

T2, P1.0

T2EX, P1.1

P1.2 P1.3 P1.4 P1.5 P1.6 P1.7

RST RXD, P3.0 TXD, P3.1

INT0, P3.2 INT1, P3.3

T0, P3.4 T1, P3.5

WR, P3.6

RD, P3.7

XTAL2 XTAL1

VSS

Preliminary W78E52B

VDD1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

40 39

P0.0, AD0

38

P0.1, AD1

37

P0.2, AD2

36

P0.3, AD3

35

P0.4, AD4

34

P0.5, AD5

33

P0.6, AD6

32

P0.7, AD7

31

EA

30

ALE

29

PSEN

28

P2.7, A15

27

P2.6, A14

26

P2.5, A13

25

P2.4, A12

24

P2.3, A11

23

P2.2, A10

22

P2.1, A9

21

P2.0, A8

44-Pin PLCC (W78E52BP)

/

T

I

2

N

T

E

T

2

X

3

,

P

P1.5 P1.6 P1.7

RST RXD, P3.0 INT2, P4.3

TXD, P3.1 INT0, P3.2 INT1, P3.3

T0, P3.4 T1, P3.5

P

1

.

3

4

6 5 4 3

7 8 9 10 11 12 13 14 15 16

17

P

3

.

7

6

,

/

R

W

D

R

1

.

. 2

1

X

T

A

L

1

2

P

1

4

.

0

2

2 1 44 43 42

V

P

S

4

S

. 0

44-Pin QFP (W78E52BF)

/

T

I

2

A

D

3

2

1

0

,

P

P V D D

P 2 . 0 , A 8

0

.

3

1

2

0

40

41

P

2

.

3

2

1

,

A

1

9

1

0

P0.4, AD4

39 38

P0.5, AD5

37

P0.6, AD6

36

P0.7, AD7

35

EA

34

P4.1

33

ALE

32

PSEN

31

P2.7, A15

30

P2.6, A14

29

P2.5, A13

2827262524232221201918

P 2 . 4 , A 1 2

P1.5 P1.6 P1.7

RST RXD, P3.0 INT2, P4.3

TXD, P3.1 INT0, P3.2 INT1, P3.3

T0, P3.4 T1, P3.5

1 2

3

4 5 6 7 8 9 10

11

P 1 . 4

12

P 3 . 6 , / W R

P 1 . 3

43 4241

P 3 . 7 , / R D

E X , P

P 1

1

.

2

1

X

T

A

L

1

2

N

T

2

3

,

P

1

V

4

.

D

.

0

D

2

40 39 38 37 36

V

P

S

2

4

S

.

0

, A 8

A

D

3

2

1

0

,

P

0

.

3

1

2

0

34

3544

P

2

.

3

1

2

,

A

1

9

1

0

P0.4, AD4

33 32

P0.5, AD5

31

P0.6, AD6

30

P0.7, AD7

29

EA

28

P4.1

27

ALE

26

PSEN

25

P2.7, A15

24

P2.6, A14

23

P2.5, A13

22212019181716151413

P 2 . 4 , A 1 2

- 2 -

PIN DESCRIPTION

EA

PSEN

INT1

WR

RD

INT2

SYMBOL DESCRIPTIONS

EXTERNAL ACCESS ENABLE: This pin forces the processor to execute out of

external ROM. It should be kept high to access internal ROM. The ROM address and data will not be presented on the bus if EA pin is high and the program counter is

within on-chip ROM area.

Preliminary W78E52B

ALE

RST

XTAL1

XTAL2

VSS

VDD

P0.0−P0.7

P1.0−P1.7

P2.0−P2.7

P3.0−P3.7

PROGRAM STORE ENABLE: address/ data bus during fetch and MOVC operations. When internal ROM access is

performed, no ADDRESS LATCH ENABLE: ALE is used to enable the address latch that separates

the address from the data on Port 0. RESET: A high on this pin for two machine cycles while the oscillator is running resets

the device. CRYSTAL1: This is the crystal oscillator input. This pin may be driven by an external

clock.

CRYSTAL2: This is the crystal oscillator output. It is the inversion of XTAL1. GROUND: Ground potential POWER SUPPLY: Supply voltage for operation. PORT 0: Port 0 is a bi-directional I/O port which also provides a multiplexed low order

address/data bus during accesses to external memory. The pins of Port 0 can be individually configured to open-drain or standard port with internal pull-ups.

PORT 1: Port 1 is a bi-directional I/O port with internal pull-ups. The bits have alternate functions which are described below:

T2(P1.0): Timer/Counter 2 external count input T2EX(P1.1): Timer/Counter 2 Reload/Capture control PORT 2: Port 2 is a bi-directional I/O port with internal pull-ups. This port also provides

the upper address bits for accesses to external memory. PORT 3: Port 3 is a bi-directional I/O port with internal pull-ups. All bits have alternate

functions, which are described below: RXD(P3.0) : Serial Port receiver input TXD(P3.1) : Serial Port transmitter output

INT0 (P3.2) : External Interrupt 0

strobe signal outputs from this pin.

enables the external ROM data onto the Port 0

P4.0-P4.3

(P3.3) : External Interrupt 1 T0(P3.4) : Timer 0 External Input T1(P3.5) : Timer 1 External Input

(P3.6) : External Data Memory Write Strobe

(P3.7) : External Data Memory Read Strobe

PORT 4: Another bit-addressable bidirectional I/O port P4. P4.3 and P4.2 are alternative function pins. It can be used as general I/O port or external interrupt input

sources (

/INT3).

Publication Release Date: December 1998

- 3 - Revision A1

BLOCK DIAGRAM

Preliminary W78E52B

P1.0

~

P1.7

P3.0 ~ P3.7

P4.0 ~ P4.3

INT2

INT3

Port

1

Port

Port 1 Latch

ACC

Interrupt

PSW

Instruction

Decoder

&

Sequencer

Bus & Clock

Controller

T1

ALU

Reset Block

Timer

2

Timer

0

Timer

1

UART

3

4

Port 3

Latch

Port 4

Latch

Oscillator

T2

SFR RAM

Address

256 bytes

RAM & SFR

ROM

Watchdog

Timer

B

Stack

Pointer

Power control

Port 0 Latch

DPTR

Temp Reg.

PC

Incrementor

Addr. Reg.

Port 2

Latch

Port

2

P0.0

0

~ P0.7

P2.0 ~ P2.7

XTAL1

XTAL2

PSENALE

RST

Vcc

Vss

FUNCTIONAL DESCRIPTION

The W78E52B architecture consists of a core controller surrounded by various registers, five general purpose I/O ports, 256 bytes of RAM, three timer/counters, and a serial port. The processor supports 111 different opcodes and references both a 64K program address space and a 64K data storage space.

Timers 0, 1, and 2

Timers 0, 1, and 2 each consist of two 8-bit data registers. These are called TL0 and TH0 for Timer 0, TL1 and TH1 for Timer 1, and TL2 and TH2 for Timer 2. The TCON and TMOD registers provide control functions for timers 0 and 1. The T2CON register provides control functions for Timer 2. RCAP2H and RCAP2L are used as reload/capture registers for Timer 2.

- 4 -

Preliminary W78E52B

INT2

The operations of Timer 0 and Timer 1 are the same as in the W78C51. Timer 2 is a special feature of the W78E54B: it is a 16-bit timer/counter that is configured and controlled by the T2CON register. Like Timers 0 and 1, Timer 2 can operate as either an external event counter or as an internal timer, depending on the setting of bit C/T2 in T2CON. Timer 2 has three operating modes: capture, autoreload, and baud rate generator. The clock speed at capture or auto-reload mode is the same as that of Timers 0 and 1.

New Defined Peripheral

In order to be more suitable for I/O, an extra 4-bit bit-addressable port P4 and two external interrupt

, INT3 has been added to either the PLCC or QFP 44 pin package. And description follows:

1.

Two additional external interrupts, interrupt 0 and 1 in the standard 80C52. The functions/status of these interrupts are determined/shown by the bits in the XICON (External Interrupt Control) register. The XICON register is bit-addressable but is not a standard register in the standard 80C52. Its address is at 0C0H. To set/clear bits in the XICON register, one can use the "SETB (/CLR) bit" instruction. For example, "SETB 0C2H" sets the EX2 bit of XICON.

XICON - external interrupt control (C0H)

PX3: External interrupt 3 priority high if set EX3: External interrupt 3 enable if set IE3: If IT3 = 1, IE3 is set/cleared automatically by hardware when interrupt is detected/serviced IT3: External interrupt 3 is falling-edge/low-level triggered when this bit is set/cleared by software PX2: External interrupt 2 priority high if set EX2: External interrupt 2 enable if set IE2: If IT2 = 1, IE2 is set/cleared automatically by hardware when interrupt is detected/serviced IT2: External interrupt 2 is falling-edge/low-level triggered when this bit is set/cleared by software

Eight-source interrupt informations:

External Interrupt 0 03H 0 (highest) IE.0 TCON.0 Timer/Counter 0 0BH 1 IE.1 External Interrupt 1 13H 2 IE.2 TCON.2 Timer/Counter 1 1BH 3 IE.3 Serial Port 23H 4 IE.4 Timer/Counter 2 2BH 5 IE.5 External Interrupt 2 33H 6 XICON.2 XICON.0 External Interrupt 3 3BH 7 (lowest) XICON.6 XICON.3

/ INT3

and INT3 , whose functions are similar to those of external

PX3 EX3 IE3 IT3 PX2 EX2 IE2 IT2

INTERRUPT

SOURCE

VECTOR

ADDRESS

POLLING

SEQUENCE WITHIN

PRIORITY LEVEL

ENABLE

REQUIRED

SETTINGS

INTERRUPT

EDGE/LEVEL

TYPE

Publication Release Date: December 1998

- 5 - Revision A1

Preliminary W78E52B

INT2

2. PORT4

Another bit-addressable port P4 is also available and only 4 bits (P4<3:0>) can be used. This port address is located at 0D8H with the same function as that of port P1, except the P4.3 and P4.2 are

alternative function pins. It can be used as general I/O pins or external interrupt input sources (

INT3 ).

Example:

P4 REG 0D8H

MOV P4, #0AH ; Output data "A" through P4.0−P4.3.

MOV A, P4 ; Read P4 status to Accumulator. SETB P4.0 ; Set bit P4.0 CLR P4.1 ; Clear bit P4.1

3. Reduce EMI Emission

Because of on-chip MTP-ROM, when a program is running in internal ROM space, the ALE will be unused. The transition of ALE will cause noise, so it can be turned off to reduce the EMI emission if it is useless. Turning off the ALE signal transition only requires setting the bit 0 of the AUXR SFR, which is located at 08Eh. When ALE is turned off, it will be reactivated when the program accesses external ROM/RAM data or jumps to execute an external ROM code. The ALE signal will turn off again after it has been completely accessed or the program returns to internal ROM code space. The AO bit in the AUXR register, when set, disables the ALE output. In order to reduce EMI emission from oscillation circuitry, W78E52B allows user to diminish the gain of on-chip oscillator amplifiers by using programmer to clear the B7 bit of security register. Once B7 is set to 0, a half of gain will be decreased. Care must be taken if user attempts to diminish the gain of oscillator amplifier, reducing a half of gain may affect the external crystal operating improperly at high frequency above 24MHz. The value of R and C1,C2 may need some adjustment while running at lower gain.

,

***AUXR - Auxiliary register (8EH)

- - - - - - - AO

AO: Turn off ALE output.

4. Power-off Flag

***PCON - Power control (87H)

- -

POF: Power off flag. Bit is set by hardware when power on reset. It can be cleared by software

to determine chip reset is a warm boot or cold boot. GF1, GF0: These two bits are general-purpose flag bits for the user. PD: Power down mode bit. Set it to enter power down mode. IDL: Idle mode bit. Set it to enter idle mode.

-

POF

GF1 GF0 PD IDL

- 6 -

Preliminary W78E52B

The power-off flag is located at PCON.4. This bit is set when VDD has been applied to the part. It can be used to determine if a reset is a warm boot or a cold boot if it is subsequently reset by software.

Watchdog Timer

The Watchdog timer is a free-running timer which can be programmed by the user to serve as a system monitor, a time-base generator or an event timer. It is basically a set of dividers that divide the system clock. The divider output is selectable and determines the time-out interval. When the time-out occurs a system reset can also be caused if it is enabled. The main use of the Watchdog timer is as a system monitor. This is important in real-time control applications. In case of power glitches or electro-magnetic interference, the processor may begin to execute errant code. If this is left unchecked the entire system may crash. The watchdog time-out selection will result in different time-out values depending on the clock speed. The Watchdog timer will de disabled on reset. In general, software should restart the Watchdog timer to put it into a known state. The control bits that support the Watchdog timer are discussed below.

Watchdog Timer Control Register

Bit: 7 6 5 4 3 2 1 0

ENW CLRW WIDL - - PS2 PS1 PS0

Mnemonic: WDTC Address: 8FH

ENW : Enable watch-dog if set. CLRW : Clear watch-dog timer and prescaler if set. This flag will be cleared automatically WIDL : If this bit is set, watch-dog is enabled under IDLE mode. If cleared, watch-dog is disabled

under IDLE mode. Default is cleared.

PS2, PS1, PS0 : Watch-dog prescaler timer select. Prescaler is selected when set PS2~0 as follows:

PS2 PS1 PS0 PRESCALER SELECT

0 0 0 2 0 1 0 4 0 0 1 8 0 1 1 16 1 0 0 32 1 0 1 64 1 1 0 128 1 1 1 256

The time-out period is obtained using the following equation:

1

14

2 PRESCALER 1000 12 mS

× × × ×

OSC

Publication Release Date: December 1998

- 7 - Revision A1

Preliminary W78E52B

Before Watchdog time-out occurs, the program must clear the 14-bit timer by writing 1 to WDTC.6 (CLRW). After 1 is written to this bit, the 14-bit timer, prescaler and this bit will be reset on the next instruction cycle. The Watchdog timer is cleared on reset.

WIDL

IDLE

OSC 1/12

Watchdog Timer Block Diagram

ENW

PRESCALER

CLRW

Typical Watch-Dog time-out period when OSC = 20 MHz

PS2 PS1 PS0 WATCHDOG TIME-OUT PERIOD

0 0 0 19.66 mS 0 1 0 39.32 mS 0 0 1 78.64 mS 0 1 1 157.28 mS 1 0 0 314.57 mS 1 0 1 629.14 mS 1 1 0 1.25 S 1 1 1 2.50 S

EXTERNAL

RESET

14-BIT TIMER

CLEAR

INTERNAL

RESET

Clock

The W78E52B is designed to be used with either a crystal oscillator or an external clock. Internally, the clock is divided by two before it is used. This makes the W78E52B relatively insensitive to duty cycle variations in the clock. The W78E52B incorporates a built-in crystal oscillator. To make the oscillator work, a crystal must be connected across pins XTAL1 and XTAL2. In addition, a load capacitor must be connected from each pin to ground. An external clock source should be connected to pin XTAL1. Pin XTAL2 should be left unconnected. The XTAL1 input is a CMOS-type input, as required by the crystal oscillator.

Power Management

Idle Mode

The idle mode is entered by setting the IDL bit in the PCON register. In the idle mode, the internal clock to the processor is stopped. The peripherals and the interrupt logic continue to be clocked. The processor will exit idle mode when either an interrupt or a reset occurs.

- 8 -

Preliminary W78E52B

PSEN

Power-down Mode

When the PD bit of the PCON register is set, the processor enters the power-down mode. In this mode all of the clocks are stopped, including the oscillator. The only way to exit power-down mode is by a reset.

Reset

The external RESET signal is sampled at S5P2. To take effect, it must be held high for at least two machine cycles while the oscillator is running. An internal trigger circuit in the reset line is used to deglitch the reset line when the W78E52B is used with an external RC network. The reset logic also has a special glitch removal circuit that ignores glitches on the reset line.

During reset, the ports are initialized to FFH, the stack pointer to 07H, PCON (with the exception of bit 4) to 00H, and all of the other SFR registers except SBUF to 00H. SBUF is not reset.

ON-CHIP MTP ROM CHARACTERISTICS

The W78E52B has several modes to program the on-chip MTP-ROM. All these operations are configured by the pins RST, ALE, OECTRL(P3.3), CE(P3.6), OE(P3.7), A0(P1.0) and VPP(EA). Moreover, the A15−A0(P2.7−P2.0, P1.7−P1.0) and the D7−D0(P0.7−P0.0) serve as the address and data bus respectively for these

operations.

, A9CTRL(P3.0), A13CTRL(P3.1), A14CTRL(P3.2),

Read Operation

This operation is supported for customer to read their code and the Security bits. The data will not be valid if the Lock bit is programmed to low.

Output Disable Condition

When the OE is set to high, no data output appears on the D7..D0.

Program Operation

This operation is used to program the data to MTP ROM and the security bits. Program operation is done when the Vpp is reach to Vcp (12.5V) level, CE set to low, and OE set to high.

Program Verify Operation

All the programming data must be checked after program operations. This operation should be performed after each byte is programmed; it will ensure a substantial program margin.

Erase Operation

An erase operation is the only way to change data from 0 to 1. This operation will erase all the MTP ROM cells and the security bits from 0 to 1. This erase operation is done when the Vpp is reach to

Vep level, CE set to low, and OE set to high.

Erase Verify Operation

After an erase operation, all of the bytes in the chip must be verified to check whether they have been successfully erased to 1 or not. The erase verify operation automatically ensures a substantial erase

margin. This operation will be done after the erase operation if Vpp = Vep(14.5V), CE is high and

OE is low.

Publication Release Date: December 1998

- 9 - Revision A1

Preliminary W78E52B

EA

Program/Erase Inhibit Operation

This operation allows parallel erasing or programming of multiple chips with different data. When P3.6(CE) = VIH, P3.7( OE) = VIH, erasing or programming of non-targeted chips is inhibited. So,

except for the P3.6 and P3.7 pins, the individual chips may have common inputs.

Company/Device ID Read Operation

This operation is supported for MTP ROM programmer to get the company ID or device ID on the W78E52B.

OPERATIONS P3.0

(A9

CTRL)

P3.1 (A13

CTRL)

P3.2 (A14

CTRL)

P3.3

(OE

CTRL)

P3.6

(CE)

P3.7

(OE )

(VPP)

P2,P1

(A15..A0)P0(D7..D0)

NOTE

Read 0 0 0 0 0 0 1 Address Data Out Output Disable 0 0 0 0 0 1 1 X Hi-Z Program 0 0 0 0 0 1 VCP Address Data In Program Verify 0 0 0 0 1 0 VCP Address Data Out @3 Erase 1 0 0 0 0 1 VEP A0:0,

others: X

Data In

0FFH

@4

Erase Verify 1 0 0 0 1 0 VEP Address Data Out @5 Program/Erase

Inhibit

X 0 0 0 1 1 VCP/

VEP

X X

Company ID 1 0 0 0 0 0 1 A0 = 0 Data Out Device ID 1 0 0 0 0 0 1 A0 = 1 Data Out

Notes:

1. All these operations happen in RST = VIH, ALE = VIL and

2. VCP = 12.5V, VEP = 14.5V, VIH = VDD, VIL = Vss.

3. The program verify operation follows behind the program operation.

4. This erase operation will erase all the on-chip MTP-ROM cells and the Security bits.

5. The erase verify operation follows behind the erase operation.

PSEN

= VIH.

SECURITY BITS

During the on-chip MTP-ROM operation mode, the MTP-ROM can be programmed and verified repeatedly. Until the code inside the MTP-ROM is confirmed OK, the code can be protected. The protection of MTP ROM and those operations on it are described below.

The W78E52B has several Special Setting Registers, including the Security Register and Company/Device ID Registers, which can not be accessed in normal mode. These registers can only be accessed from the MTP-ROM operation mode. Those bits of the Security Registers can not be changed once they have been programmed from high to low. They can only be reset through eraseall operation. The contents of the Company ID and Device ID registers have been set in factory. Both registers are addressed by the A0 address line during the same specific condition. The Security Register is addressed in the MTP-ROM operation mode by address #0FFFFh.

- 10 -

Preliminary W78E52B

logic 0 : the MOVC instruction in external memory

0FFFFh

D7 D6 D5 D4 D3 D2 D1 D0

1 1 0 1 1 0 1 0

1 1 1 0 00 0

B7

B0 : Lock bit, logic 0 : active B1 : MOVC inhibit,

cannot access the code in internal memory. logic 1 : no restriction.

B2 : Encryption logic 0 : the encryption logic enable logic 1 : the encryption logic disable

B7 : Osillator Control

logic 0 : 1/2 gain logic 1 : Full gain Default 1 for all security bits.

0

Reserved B2

Company ID (#DAH)

Device ID (#E0H)

Security Bits

B0B1

Reserved bits must be kept in logic 1.

8KB MTP ROM

Program Memory

Reserved

Security Register

0000h

1FFFh

Special Setting Registers

Lock bit

This bit is used to protect the customer's program code in the W78E52B. It may be set after the programmer finishes the programming and verifies sequence. Once this bit is set to logic 0, both the MTP ROM data and Special Setting Registers can not be accessed again.

MOVC Inhibit

This bit is used to restrict the accessible region of the MOVC instruction. It can prevent the MOVC instruction in external program memory from reading the internal program code. When this bit is set to logic 0, a MOVC instruction in external program memory space will be able to access code only in the external memory, not in the internal memory. A MOVC instruction in internal program memory space will always be able to access the ROM data in both internal and external memory. If this bit is logic 1, there are no restrictions on the MOVC instruction.

Encryption

This bit is used to enable/disable the encryption logic for code protection. Once encryption feature is enabled, the data presented on port 0 will be encoded via encryption logic. Only whole chip erase will reset this bit.

Publication Release Date: December 1998

- 11 - Revision A1

Preliminary W78E52B

(*1)

(*2)

V

A0 to A7

P1

V

P3.0

IL

P3.1

V

IL

P3.2

V

IL

P3.3

V

IL

V

P3.6

IL

P3.7

V

IH

X'tal1 X'tal2 Vss

DD

P0

EA/Vpp

ALE

RST

PSEN

P2

Programming Configuration

+5V

PGM DATA

V

CP

V

IL

V

IH

V

IH

A8 to A15

A0 to A7

P1

V

P3.0

IL

P3.1

V

IL

P3.2

V

IL

V

P3.3

IL

P3.6

V

IH

P3.7

V

IL

X'tal1 X'tal2 Vss

Programming Verification

V

EA/Vpp

ALE

RST

PSEN

+5V

DD

PGM DATA

P0

V

CP

V

IL

V

IH

V

IH

A8 to A15

P2

ABSOLUTE MAXIMUM RATINGS

PARAMETER SYMBOL MIN. MAX. UNIT

DC Power Supply

VDD−VSS Input Voltage VIN VSS -0.3 VDD +0.3 V Operating Temperature TA 0 70 Storage Temperature TST -55 +150

Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the

device.

-0.3 +7.0 V

°C °C

DC CHARACTERISTICS

VCC−VSS = 5V ±10%, TA = 25° C, unless otherwise specified.

PARAMETER SYMBOL TEST CONDITIONS SPECIFICATION UNIT

MIN. MAX.

Operating Voltage VDD 4.5 5.5 V Operating Current IDD No load VDD = 5.5V - 20 mA Idle Current IIDLE Idle mode VDD = 5.5V - 6 mA Power Down Current IPWDN Power-down mode

VDD = 5.5V Input Current P1, P2, P3 Logical 1-to-0 Transition Current P1, P2, P3 Input Current RST

IIN1 VDD = 5.5V

VIN = 0V or VDD

ITL VDD = 5.5V

VIN = 2.0V

IIN2 VDD = 5.5V

VIN = VDD

- 12 -

- 50

-50 +10

-550 -

-10 +300

µA

Preliminary W78E52B

EA

PSEN

(*4)

PSEN

DC Characteristics, continued

PARAMETER SYMBOL TEST CONDITIONS SPECIFICATION UNIT

MIN. MAX.

Input Leakage Current P0,

Output Low Voltage P1, P2, P3 Output Low Voltage

ALE,

, P0

(*3)

Output High Voltage P1, P2, P3

Output High Voltage ALE,

, P0

(*3)

Input Low Voltage (Except RST) Input Low Voltage RST Input Low Voltage XTAL1 Input High Voltage (Except RST) Sink Current P1, P2, P3, P4 Input High Voltage RST Input High Voltage XTAL1 Sink Current

P0, ALE, PSEN

(*3)

Source Current P1, P2, P3, P4 Source Current

P0, ALE, PSEN

Notes: *1. Pins P1, P2 and P3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches

its maximum value when VIN is approximately 2V.

*2. RST pin has an internal pull-down resistor. *3. P0, ALE,

*4. XTAL1 is a CMOS input and RST is a Schmitt trigger input.

(*3)

are in the external access memory mode.

ILK VDD = 5.5V

-10 +10

0V < VIN < VDD

VOL1 VDD = 4.5V

- 0.45 V

IOL1 = +2 mA

VOL2 VDD = 4.5V

- 0.45 V

IOL2 = +4 mA

VOH1 VDD = 4.5V

2.4 - V

IOH1 = -100 µA

VOH2 VDD = 4.5V

2.4 - V

IOH2 = -400 µA

VIL1 VDD = 4.5V 0 0.8 V

VIL2 VDD = 4.5V 0 0.8 V

VIL3 VDD = 4.5V 0 0.8 V

VIH1 VDD = 4.5V 2.4 VDD +0.2 V

ISK1 VDD = 4.5V

4 12 mA

VS = 0.45V

VIH2 VDD = 4.5V 0.67 V

VIH3 VDD = 4.5V 0.67 V

ISK2 VDD = 4.5V

8 16 mA

VDD +0.2 V

DD

VDD +0.2 V

DD

VS = 0.45V

ISR1 VDD = 4.5V

-100 -250 uA

VS = 2.4V

ISR2 VDD = 4.5V

-8 -14 mA

V = 2.4V

µA

Publication Release Date: December 1998

- 13 - Revision A1

Preliminary W78E52B

PSEN

AC CHARACTERISTICS

The AC specifications are a function of the particular process used to manufacture the part, the ratings of the I/O buffers, the capacitive load, and the internal routing capacitance. Most of the specifications can be expressed in terms of multiple input clock periods (TCP), and actual parts will usually experience less than a ±20 nS variation. The numbers below represent the performance expected from a 0.6micron CMOS process when using 2 and 4 mA output buffers.

Clock Input Waveform

XTAL1

T

CH

F

OP, TCP

T

CL

PARAMETER SYMBOL MIN. TYP. MAX. UNIT NOTES

Operating Speed FOP 0 - 40 MHz 1 Clock Period TCP 25 - - nS 2 Clock High TCH 10 - - nS 3 Clock Low TCL 10 - - nS 3

Notes:

1. The clock may be stopped indefinitely in either state.

2. The TCP specification is used as a reference in other specifications.

3. There are no duty cycle requirements on the XTAL1 input.

Program Fetch Cycle

PARAMETER SYMBOL MIN. TYP. MAX. UNIT NOTES

Address Valid to ALE Low TAAS Address Hold from ALE Low TAAH

ALE Low to

Low to Data Valid Data Hold after Data Float after

Low

High

TAPL

TPDA - - 2 TCP nS 2

TPDH 0 - 1 TCP nS 3

TPDZ 0 - 1 TCP nS

ALE Pulse Width TALW

Pulse Width

Notes:

1. P0.0−P0.7, P2.0−P2.7 remain stable throughout entire memory cycle.

2. Memory access time is 3 TCP.

3. Data have been latched internally prior to

4. "∆" (due to buffer driving delay and wire loading) is 20 nS.

TPSW

going high.

1 TCP -∆ 1 TCP -∆ 1 TCP -∆

2 TCP -∆ 3 TCP -∆

- - nS 4

- - nS 1, 4

- - nS 4

2 TCP - nS 4 3 TCP - nS 4

- 14 -

Data Read Cycle

RD

WR

PARAMETER SYMBOL MIN. TYP. MAX. UNIT NOTES

ALE Low to RD Low

Low to Data Valid Data Hold from RD High Data Float from RD High

Pulse Width

Notes:

1. Data memory access time is 8 TCP.

2. "∆" (due to buffer driving delay and wire loading) is 20 nS.

TDAR TDDA - - 4 TCP nS 1

TDDH 0 - 2 TCP nS

TDDZ 0 - 2 TCP nS

TDRD

Data Write Cycle

PARAMETER SYMBOL MIN. TYP. MAX. UNIT

ALE Low to WR Low Data Valid to WR Low Data Hold from WR High

Pulse Width

TDAW

TDAD TDWD TDWR

3 TCP -∆

6 TCP -∆

3 TCP -∆ 1 TCP -∆ 1 TCP -∆ 6 TCP -∆

Preliminary W78E52B

-

3 TCP +∆

6 TCP - nS 2

-

3 TCP +∆

- - nS

6 TCP - nS

nS 1, 2

nS

Note: "∆" (due to buffer driving delay and wire loading) is 20 nS.

Port Access Cycle

PARAMETER SYMBOL MIN. TYP. MAX. UNIT

Port Input Setup to ALE Low TPDS 1 TCP - - nS Port Input Hold from ALE Low TPDH 0 - - nS Port Output to ALE TPDA 1 TCP - - nS

Note: Ports are read during S5P2, and output data becomes available at the end of S6P2. The timing data are referenced to

ALE, since it provides a convenient reference.

Program Operation

PARAMETER SYMBOL MIN. TYP. MAX. UNIT

VPP Setup Time TVPS 2.0 - Data Setup Time TDS 2.0 - Data Hold Time TDH 2.0 - Address Setup Time TAS 2.0 - Address Hold Time TAH 0 - -

µS µS µS µS µS

Publication Release Date: December 1998

- 15 - Revision A1

Program Operation, continued

CE

OE

PSEN

PARAMETER SYMBOL MIN. TYP. MAX. UNIT

Preliminary W78E52B

Program Pulse Width for

TPWP 290 300 310

µS

Program Operation OECTRL Setup Time OECTRL Hold Time

Setup Time High to Output Float

Data Valid from

Note: Flash data can be accessed only in flash mode. The RST pin must pull in VIH status, the ALE pin must pull in VIL status, and

the

pin must pull in VIH status.

TOCS 2.0 - -

TOCH 2.0 - -

TOES 2.0 - -

TDFP 0 - 130 nS

TOEV - - 150 nS

µS µS µS

TIMING WAVEFORMS

Program Fetch Cycle

S1

S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6

XTAL1

T

ALW

ALE

T

APL

PSEN

T

PSW

T

AAS

PORT 2

T

A0-A7

PDA

T

PDH,TPDZ

A0-A7

DataCode

Code

A0-A7

Data

A0-A7

PORT 0

T

AAH

- 16 -

Timing Waveforms, continued

Data Read Cycle

XTAL1

ALE

PSEN

Preliminary W78E52B

S2 S3S5 S6 S1S2 S3 S4S5 S6 S1S4

PORT 2

PORT 0

RD

Data Write Cycle

XTAL1

ALE

PSEN

PORT 2

A0-A7

TDAR

A8-A15

TDDA

A8-A15

DATA

T

DDH,TDDZ

T

DRD

S2 S3S5 S6 S1S2 S3 S4S1S5 S6S4

PORT 0

WR

A0-A7

T

DAW

T

DAD

DATA OUT

T

DWD

T

DWR

Publication Release Date: December 1998

- 17 - Revision A1

Timing Waveforms, continued

Port Access Cycle

XTAL1

ALE

Preliminary W78E52B

S5 S6 S1

T

PDHPDS

T

PDA

PORT

INPUT

SAMPLE

Program Operation

P2, P1

(A15... A0)

P3.6 (CE)

P3.3

(OECTRL)

P3.7 (OE)

P0

(A7... A0)

Vpp

V

IH

V

IL

V

IH

V

IL

V

IH

V

IL

V

IH

V

IL

V

IH

V

IL

Vcp V

IH

DATA OUT

Program Program

Verify

Address Stable

T

AS

T

PWP

T

OCS

T

OCH

T

OES

T

DH

Data In Data Out

T

DS

T

VPS

AH

T

DFP

OUT

D

T

OEV

Read Verify

Address Valid

- 18 -

TYPICAL APPLICATION CIRCUITS

Expanded External Program Memory and Crystal

V

DD

31

EA

19

XTAL1

R

18

XTAL2

9

C2

RST

INT0

12 13

INT1

14

T0

15

T1

1

P1.0

2

P1.1

3

P1.2

4

P1.3

5

P1.4

6

P1.5

7

P1.6

8

P1.7

W78E52B

P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7

P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7

WR

PSEN

ALE TXD RXD

AD0

39 38 37 36

35

34

33

32

21

22

23

24

25

26

27 28

RD

17

16

29

30 11 10

AD1

AD2

AD3

AD4 AD5 AD6 AD7

A8 A9 A10 A11 A12 A13 A14 A15

AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7

GND

8.2 K

V

DD

10 u

CRYSTAL

C1

Preliminary W78E52B

3

D0

4

D1

7

D2

8

D3

13

D4

14

D5

17

D6

18

D7

1

OC

11

G

74373

2

Q0

5

Q1

6

Q2

9

Q3

12

Q4

15

Q5

16

Q6

19

Q7

A0

A0 A1 A2

A3 A4 A5 A6 A7

A10 A11 A12 A13 A14 A15

GND

10

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15

CE

OE

27512

O0 O1 O2 O3 O4 O5 O6 O7

A1

9

A2

8

A3

7

A4

6

A5

5

A6

4

A7

3

25

A8

24

A9

21 23 2 26 27

1

20 22

11

AD0

12

AD1

13

AD2

15

AD3

16

AD4

17

AD5

18

AD6

19

AD7

CRYSTAL C1 C2 R

16 MHz 30P 30P 24 MHz 15P 15P 33 MHz 10P 10P 6.8K 40 MHz 5P 5P 4.7K

Above table shows the reference values for crystal applications (full gain).

Note: C1, C2, R components refer to Figure A.

Figure A

Publication Release Date: December 1998

- 19 - Revision A1

Typical Application Circuits, continued

Expanded External Data Memory and Oscillator

V

OSCILLATOR

DD

31

EA

19

XTAL1

18

XTAL2

9

RST

INT0

12 13

INT1

14

T0

15

T1

1

P1.0

2

P1.1

3

P1.2

4

P1.3

5

P1.4

6

P1.5

7

P1.6

8

P1.7

W78E52B

P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7

P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7

RD WR

PSEN

ALE

TXD

RXD

39

AD0

38

AD1 AD2

37 36

AD3 AD4

35

AD5

34

33

AD6

32

AD7

21

A8

22

A9

23

A10

24

A11

25

A12 A13

26

A14

27

28

17 16

29 30 11 10

8.2 K

V

DD

10 u

AD0 AD1 AD2 AD3 AD4 AD5 AD6

AD7

GND

Preliminary W78E52B

3 4 7 8 13 14 17

18

1

OC

11

G

D0 D1 D2 D3 D4 D5 D6 D7

74373

2

Q0

5

Q1

6

Q2

9

Q3

12

Q4

15

Q5

16

Q6

19

Q7

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14

GND

10

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9

A10 A11 A12 A13 A14

CE OE WR

20256

D0 D1 D2 D3 D4 D5 D6 D7

9 8 7

6

5

4

3 25 24 21 23

2 26

1

20 22 27

A0 A1 A2 A3 A4 A5 A6 A7

AD0

11

AD1

12

AD2

13

AD3

15

AD4

16

AD5

17

AD6

18

AD7

19

Figure B

- 20 -

PACKAGE DIMENSIONS

40-pin DIP

40

1

E

S

A

2

A

L

D

B

e

B

1

Preliminary W78E52B

Dimension in inch Dimension in mm

Symbol

A A A B B c

21

D E E e L

a

e

201

Base Plane

1

A

Seating Plane

1

E

e A

a

S

Notes:

1. Dimension D Max. & S include mold flash or tie bar burrs.

c

2. Dimension E1 does not include interlead flash.

3. Dimension D & E1 include mold mismatch and

are determined at the mold parting line.

4. Dimension B1 does not include dambar

protrusion/intrusion.

5. Controlling dimension: Inches.

6. General appearance spec. should be based on

final visual inspection spec.

Nom.

Min.

0.010

1

0.155

0.150

2

0.016

0.018

0.050 1.27

1

0.008

0.010

2.055 2.070 52.20 52.58

0.6000.590

0.540

1

0.120

0.130

0 15

0.6500.630 16.00 16.51

A

Min.

0.254

3.81

0.406

0.203

14.986

13.72

2.286 2.54 2.7940.090 0.100

3.048

Nom.

3.937

0.457

0.254

15.24

13.84

3.302

5.334

4.064

0.559

1.3721.2190.0540.048

0.356

15.494

13.97

3.556

17.01

Max. Max.

0.210

0.160

0.022

0.014

0.610

0.5500.545

0.110

0.140

0.670

0.090

.

150

2.286

44-pin PLCC

7

17

L

θ

Seating Plane

6 1

e

H

D

44 40

G

D

Dimension in inch Dimension in mm

Symbol

39

H

E

29

2818

A

2

A

b b

1

A

1

y

G

E

c

A A A b1 b c D E e G G H HE L y

Notes:

1. Dimension D & E do not include interlead flash.

2. Dimension b1 does not include dambar

protrusion/intrusion.

3. Controlling dimension: Inches

4. General appearance spec. should be based on final visual inspection spec.

Nom.

Min.

0.020

1

0.145

2

0.026

0.016

0.008

0.648

0.590

D

0.590

E

0.680

D

0.680

0.090

Max. Max.

0.185

0.150

0.155

0.028

0.032

0.022

0.018

0.010

0.014

0.653

0.658

0.6580.6530.648

0.050 BSC

0.610

0.630

0.6300.610

0.690

0.700

0.690

0.100

0.110

0.004

0.508

3.683

0.66

0.406

0.203

16.46

14.99

17.27

2.296

Min.

1.27

Nom.

3.81

0.711

0.457

0.254

16.59

15.49

15.4914.99

17.53

2.54

BSC

4.699

3.937

0.813

0.559

0.356

16.71

16.7116.5916.46

16.00

17.78

17.7817.53

2.794

0.10

Publication Release Date: December 1998

- 21 - Revision A1

Package Dimensions, continued

44-pin PQFP

H

D

44

1

11

12

e

Seating Plane

See Detail F

Preliminary W78E52B

Dimension in inch

34

33

Symbol

A A A b

1

2

c D

E

EH

E e

D

H

E

H L

1

L

22

b

c

A

2

A

1

y

θ

L

L 1

Detail F

y

θ

Notes:

1. Dimension D & E do not include interlead flash.

2. Dimension b does not include dambar protrusion/intrusion.

3. Controlling dimension: Millimeter

4. General appearance spec. should be based on final visual inspection spec.

Nom.

Min.

--- ---

0.002

0.01 0.02 0.25

0.081

0.075

0.01

0.014

0.006 0.152

0.394

0.390

0.025

0.031

0.510 13.45

0.520

0.510

0.025

0.031

0.063

0.051 0.075 1.295

0

Dimension in mm

Min.

--- ---

0.05

1.90

0.25

9.9

0.635

12.95

0.65

Nom.

0.5

2.05

2.20

0.45

0.35

0.2540.101

10.00

10.1

10.00

0.952

0.80

13.2

13.4513.2

0.8

0.95

1.6

1.905

0

0.08

Max. Max.

---

0.087

0.018

0.0100.004

0.398

0.3980.394

0.036

0.530

0.037

0.003 7

---

7

Headquarters

No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5792766 http://www.winbond.com.tw/ Voice & Fax-on-demand: 886-2-27197006

Winbond Electronics (H.K.) Ltd.

Rm. 803, World Trade Square, Tower II, 123 Hoi Bun Rd., Kwun Tong, Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064

Taipei Office

11F, No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-27190505 FAX: 886-2-27197502

Note: All data and specifications are subject to change without notice.

- 22 -

Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab.

2727 N. First Street, San Jose, CA 95134, U.S.A. TEL: 408-9436666 FAX: 408-5441798