Datasheet W78C33 Datasheet (winbond)

INT2

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8-BIT MICROCONTROLLER

GENERAL DESCRIPTION

The W78C33 microcontroller supplies a wider frequency range than most 8-bit microcontrollers on the market. It is functional compatible with the industry standard 80C32 microcontroller series except

the one extra 4-bit bit-addressable I/O port (Port 4) and two additional external interrupts (

INT3 ).

The W78C33 contains four 8-bit bidirectional parallel ports, three 16-bit timer/counters, and a serial port. These peripherals are supported by a six-source, two-level interrupt capability. There are 256 bytes of RAM, and the device supports ROMless operation for application programs.

The W78C33 microcontroller has two power reduction modes, idle mode and power-down mode, both of which are software selectable. The idle mode turns off the processor clock but allows for continued peripheral operation. The power-down mode stops the crystal oscillator for minimum power consumption. The external clock can be stopped at any time and in any state without affecting the processor.

W78C33

,

FEATURES

• 8-bit CMOS microcontroller

• Fully static design

• Low standby current at full supply voltage

• DC-40 MHz operation

• 256 bytes of on-chip scratchpad RAM

• ROMless operation

• 64K bytes program memory address space

• 64K bytes data memory address space

• Four 8-bit bidirectional ports

• Three 16-bit timer/counters

• One full duplex serial port

• Boolean processor

• Eight-source, two-level interrupt capability

• Built-in power management

• One extra 4-bit bit-addressable I/O port

• Two additional external interrupts

• Packages:

− PLCC 44: W78C33P-16/24/40

− QFP 44: W78C33F-16/24/40

− TQFP 44: W78C33M-16/24/40

/ INT3

Publication Release Date: October 1997

- 1 - Revision A1

PIN CONFIGURATIONS

44-Pin PLCC (W78C33P)

P1.5 P1.6 P1.7

RST RXD, P3.0 INT2, P4.3

TXD, P3.1 INT0, P3.2 INT1, P3.3

T0, P3.4 T1, P3.5

P

1

.

3

4

6 5 4 3

7 8 9 10 11 12 13 14 15 16

17

P

3

.

7

6

,

/

R

W

D

R

T 2 E X ,

P

P 1

1 .

.

2

1

X

T

A

L

1

2

/ I

A

N

T

D

T

2

0

3

,

P

1

V

0

4

.

C

.

0

C

0

2

2 1 44 43 42

V

P

S

2

4

S

.

1

0

,

A

9

8

W78C33

A

D

3

2

1

,

P

0

.

3

1

2

40

41

39

P0.4, AD4

38

P0.5, AD5

37

P0.6, AD6

36

P0.7, AD7

35

EA

34

P4.1

33

ALE

32

PSEN

31

P2.7, A15

30

P2.6, A14

29

P2.5, A13

2827262524232221201918

P

2

.

4

3

2

,

A

1

2

0

44-Pin QFP/TQFP (W78C33F/W78C33M)

1

P1.5

2

P1.6 P1.7

RST RXD, P3.0 INT2, P4.3

TXD, P3.1 INT0, P3.2 INT1, P3.3

T0, P3.4 T1, P3.5

5 6 7 8 9 10

- 2 -

3 4

11

P 1 . 4

44

12

P 3 . 6 , / W R

P

1

.

2

3

43 4241

X

P

T

3

A

.

L

7

2

, / R D

/

T

I

2

N

T

E

T

2

X

3

,

P

1

V

4

.

C

.

0

1

C

2

403938 37 36 35

X

V

P

T

S

2

4

A

S

.

L

0

1

, A 8

A

D

3

2

1

0

,

P

0

.

3

2

1

0

34

33

P0.4, AD4

32

P0.5, AD5

31

P0.6, AD6

30

P0.7, AD7

29

EA

28

P4.1

27

ALE

26

PSEN

25

P2.7, A15

24

P2.6, A14

23

P2.5, A13

22212019181716151413

P

2

.

4

3

2

1

,

A

1

9

1

2

0

W78C33

INT0

INT1

WR

RD

INT2

PIN DESCRIPTION

P0.0−P0.7

Port 0, Bits 0 through 7. Port 0 is a bidirectional I/O port. This port also provides a multiplexed low order address/data bus during accesses to external memory.

P1.0−P1.7

Port 1, Bits 0 through 7. Port 1 is a bidirectional I/O port with internal pull-ups. Pins P1.0 and P1.1 also serve as T2 (Timer 2 external input) and T2EX (Timer 2 capture/reload trigger), respectively.

P2.0−P2.7

Port 2, Bits 0 through 7. Port 2 is a bidirectional I/O port with internal pull-ups. This port also provides the upper address bits for accesses to external memory.

P3.0−P3.7

Port 3, Bits 0 through 7. Port 3 is a bidirectional I/O port with internal pull-ups. All bits have alternate functions, which are described below:

PIN ALTERNATE FUNCTION

P3.0 RXD Serial Receive Data P3.1 TXD Serial Transmit Data P3.2

P3.3 P3.4 T0 Timer 0 Input

P3.5 T1 Timer 1 Input P3.6

P3.7

External Interrupt 0 External Interrupt 1

Data Write Strobe

Data Read Strobe

P4.0−P4.3

Another bit-addressable bidirectional I/O port P4. P4.3 and P4.2 are alternative function pins. It can be used as general I/O pins or external interrupt input sources (

/ INT3 ).

EA

External Address Input, active low. This pin forces the processor to execute out of external ROM. This pin should be kept low for all W78C33 operations.

RST

Reset Input, active high. This pin resets the processor. It must be kept high for at least two machine cycles in order to be recognized by the processor.

Publication Release Date: October 1997

- 3 - Revision A1

W78C33

PSEN

ALE

Address Latch Enable Output, active high. ALE is used to enable the address latch that separates the address from the data on Port 0. ALE runs at 1/6th of the oscillator frequency. A single ALE pulse is skipped during external data memory accesses. ALE goes to a high state during reset with a weak pull-up.

PSEN

Program Store Enable Output, active low. address/data bus during fetch and MOVC operations.

weak pull-up.

XTAL1

Crystal 1. This is the crystal oscillator input. This pin may be driven by an external clock.

XTAL2

Crystal 2. This is the crystal oscillator output. It is the inversion of XTAL1.

VSS, VCC

Power Supplies. These are the chip ground and positive supplies.

enables the external ROM onto the Port 0

goes to a high state during reset with a

- 4 -

BLOCK DIAGRAM

W78C33

P1.0

~

P1.7

P3.0 ~ P3.7

P4.0 ~ P4.3

INT2

INT3

Port

1

Port

Port 1 Latch

ACC

Interrupt

Timer

2

Timer

0

Timer

1

UART

3

4

Port 3 Latch

Port 4 Latch

XTAL1 PSENALE GNDVCCRSTXTAL2

Oscillator

PSW

Instruction

Decoder

&

Sequencer

Bus & Clock

Controller

ALU

T2T1

SFR RAM

Address

256 bytes

RAM & SFR

Reset Block

B

Stack

Pointer

Power control

Port 0 Latch

DPTR

Temp Reg.

PC

Incrementor

Addr. Reg.

Port 2

Latch

Port 0

Port 2

P0.0 ~ P0.7

P2.0 ~ P2.7

Publication Release Date: October 1997

- 5 - Revision A1

W78C33

FUNCTIONAL DESCRIPTION

The W78C33 architecture consists of a core controller surrounded by various registers, four general purpose I/O ports, 256 bytes of RAM, three timer/counters, and a serial port. The processor supports 111 different instruction and references both a 64K program address space and a 64K data storage space.

Timers 0, 1, and 2

Timers 0, 1, and 2 each consist of two 8-bit data registers. These are called TL0 and TH0 for Timer 0, TL1 and TH1 for Timer 1, and TL2 and TH2 for Timer 2. The TCON and TMOD registers provide control functions for timers 0, 1. The T2CON register provides control functions for Timer 2. RCAP2H and RCAP2L are used as reload/capture registers for Timer 2.

The operations of Timer 0 and Timer 1 are the same as in the W78C31. Timer 2 is a special feature of the W78C33: it is a 16-bit timer/counter that is configured and controlled by the T2CON register. Like Timers 0 and 1, Timer 2 can operate as either an external event counter or as an internal timer, depending on the setting of bit C/T2 in T2CON. Timer 2 has three operating modes: capture, autoreload, and baud rate generator. The clock speed at capture or auto-reload mode is the same as that of Timers 0 and 1.

Clock

The W78C33 is designed to be used with either a crystal oscillator or an external clock. Internally, the clock is divided by two before it is used. This makes the W78C33 relatively insensitive to duty cycle variations in the clock.

Crystal Oscillator

The W78C33 incorporates a built-in crystal oscillator. To make the oscillator work, a crystal must be connected across pins XTAL1 and XTAL2. In addition, a load capacitor must be connected from each pin to ground, and a resistor must also be connected from XTAL1 to XTAL2 to provide a DC bias when the crystal frequency is above 24 MHz.

External Clock

An external clock should be connected to pin XTAL1. Pin XTAL2 should be left unconnected. The XTAL1 input is a CMOS-type input, as required by the crystal oscillator. As a result, the external clock signal should have an input one level of greater than 3.5 volts.

Power Management

Idle Mode

The idle mode is entered by setting the IDL bit in the PCON register. In the idle mode, the internal clock to the processor is stopped. The peripherals and the interrupt logic continue to be clocked. The processor will exit idle mode when either an interrupt or a reset occurs.

Power-down Mode

When the PD bit of the PCON register is set, the processor enters the power-down mode. In this mode all of the clocks, including the oscillator are stopped. The only way to exit power-down mode is by a reset.

- 6 -

W78C33

INT2

Reset

The external RESET signal is sampled at S5P2. To take effect, it must be held high for at least two machine cycles while the oscillator is running.

An internal trigger circuit in the reset line is used to deglitch the reset line when the W78C33 is used with an external RC network. The reset logic also has a special glitch removal circuit that ignores glitches on the reset line.

During reset, the ports are initialized to FFH, the stack pointer to 07H, PCON (with the exception of bit 4) to 00H, and all of the other SFR registers except SBUF to 00H. SBUF is not reset.

New Defined Peripheral

In order to be more suitable for I/O, an extra 4-bit bit-addressable port P4 and two external interrupt

, INT3 has been added to either the PLCC or QFP 44 pin package. And description follows:

1. INT2/ INT3

Two additional external interrupts, interrupt 0 and 1 in the standard 80C52. The functions/status of these interrupts are determined/shown by the bits in the XICON (External Interrupt Control) register. The XICON register is bit-addressable but is not a standard register in the standard 80C52. Its address is at 0C0H. To set/clear bits in the XICON register, one can use the "SETB (/CLR) bit" instruction. For example, "SETB 0C2H" sets the EX2 bit of XICON.

***XICON - external interrupt control (C0H)

PX3 EX3 IE3 IT3 PX2 EX2 IE2 IT2

PX3: External interrupt 3 priority high if set EX3: External interrupt 3 enable if set IE3: If IT3 = 1, IE3 is set/cleared automatically by hardware when interrupt is detected/serviced IT3: External interrupt 3 is falling-edge/low-level triggered when this bit is set/cleared by software PX2: External interrupt 2 priority high if set EX2: External interrupt 2 enable if set IE2: If IT2 = 1, IE2 is set/cleared automatically by hardware when interrupt is detected/serviced IT2: External interrupt 2 is falling-edge/low-level triggered when this bit is set/cleared by software

Eight-source interrupt informations:

INTERRUPT

SOURCE

External Interrupt 0 03H 0 (highest) IE.0 TCON.0 Timer/Counter 0 0BH 1 IE.1 External Interrupt 1 13H 2 IE.2 TCON.2 Timer/Counter 1 1BH 3 IE.3 -

VECTOR

ADDRESS

and INT3 , whose functions are similar to those of external

POLLING

SEQUENCE WITHIN

PRIORITY LEVEL

ENABLE

REQUIRED

SETTINGS

INTERRUPT

TYPE

EDGE/LEVEL

Publication Release Date: October 1997

- 7 - Revision A1

Eight-source interrupt informations, continued

INT2

W78C33

INTERRUPT

SOURCE

Serial Port 23H 4 IE.4 Timer/Counter 2 2BH 5 IE.5 External Interrupt 2 33H 6 XICON.2 XICON.0 External Interrupt 3 3BH 7 (lowest) XICON.6 XICON.3

2. PORT4

Another bit-addressable port P4 is also available and only 4 bits (P4<3:0>) can be used. This port address is located at 0D8H with the same function as that of port P1, except the P4.3 and P4.2 are

alternative function pins. It can be used as general I/O pins or external interrupt input sources (

INT3 ). Example: P4 REG 0D8H MOV P4, #0AH ; Output data "A" through P4.0−P4.3.

MOV A, P4 ; Read P4 status to Accumulator. SETB P4.0 ; Set bit P4.0 CLR P4.1 ; Clear bit P4.1

VECTOR

ADDRESS

POLLING

SEQUENCE WITHIN

PRIORITY LEVEL

ENABLE

REQUIRED

SETTINGS

INTERRUPT

TYPE

EDGE/LEVEL

/

ABSOLUTE MAXIMUM RATINGS

PARAMETER SYMBOL MIN. MAX. UNIT

DC Power Supply VCC−VSS -0.3 +7.0 V Input Voltage VIN VSS -0.3 VCC +0.3 V Operating Temperature TA 0 70 Storage Temperature TST -55 +150

Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device.

- 8 -

°C °C

DC CHARACTERISTICS

EA

(VDD-VSS = 5V ±10%, TA = 25°C, Fosc = 20 MHz, unless otherwise specified.)

PARAMETER SYM. SPECIFICATION UNIT TEST CONDITIONS

MIN. MAX.

Operating Voltage VDD 4.5 5.5 V Operating Current IDD - 20 mA No load

VDD = 5.5V

Idle Current IIDLE - 6 mA Idle mode

VDD = 5.5V

W78C33

Power Down Current IPWDN - 50

Input Current P1, P2, P3, P4 Input Current RST Input Leakage Current

P0, Logic 1 to 0 Transition

Current P1, P2, P3, P4 Input Low Voltage

P0, P1, P2, P3, P4, Input Low Voltage RST Input Low Voltage XTAL1[*4] Input High Voltage

IIN1 -50 +10

IIN2 -10 +300

ILK -10 +10

ITL [*4] -500 -200

VIL1 0 0.8 V VDD = 4.5V

VIL2 0 0.8 V VDD = 4.5V

VIL3 0 0.8 V VDD = 4.5V

VIH1 2.4 VDD +0.2 V VDD = 5.5V

µA

Power-down mode VDD = 5.5V VDD = 5.5V VIN = 0V or VDD VDD = 5.5V 0 < VIN < VDD VDD = 5.5V 0V <VIN < VDD

VDD = 5.5V VIN =2.0V

P0, P1, P2, P3, P4, Input High Voltage RST Input High Voltage XTAL1 [*4] Output Low Voltage P1, P2, P3, P4

VIH2 3.5 VDD +0.2 V VDD = 5.5V

VIH3 3.5 VDD +0.2 V VDD = 5.5V

VOL1 - 0.45 V VDD = 4.5V

IOL = +2 mA

Publication Release Date: October 1997

- 9 - Revision A1

DC Characteristics, continued

PARAMETER SYM. SPECIFICATION UNIT TEST CONDITIONS

Output Low Voltage P0, ALE, PSEN [*3]

W78C33

MIN. MAX.

VOL2 - 0.45 V VDD = 4.5V

IOL = +4mA

Sink Current P1, P2, P3, P4 Sink Current

P0, ALE, PSEN Output High Voltage

P1, P2, P3, P4 Output High Voltage

P0, ALE, PSEN [*3] Source Current

P1, P2, P3, P4 Source Current

P0, ALE, PSEN

Notes: *1. RST pin is a Schmitt trigger input. RST has internal pull-low resistors of about 30 KΩ. *3. P0, ALE and /PSEN are tested in the external access mode. *4. XTAL1 is a CMOS input. *5. Pins of P1, P2, P3, P4 can source a transition current when they are being externally driven from 1 to 0. The transition

current reaches its maximum value when VIN approximates to 2V.

ISK1 4 8 mA VDD = 4.5V

Vs = 0.45V

ISK2 10 14 mA VDD = 4.5V

Vs = 0.45V

VOH1 2.4 - V VDD = 4.5V

IOH = -100 µA

VOH2 2.4 - V VDD = 4.5V

IOH = -400 µA

ISR1 -120 -180

µA

VDD = 4.5V Vs = 2.4V

ISR2 -10 -14 mA VDD = 4.5V

Vs = 2.4V

AC CHARACTERISTICS

The AC specifications are a function of the particular process used to manufacture the part, the ratings of the I/O buffers, the capacitive load, and the internal routing capacitance. Most of the specifications can be expressed in terms of multiple input clock periods (TCP), and actual parts will usually experience less than a ±20 nS variation. The numbers below represent the performance expected from a 1.2 micron CMOS process when using 2 and 4 mA output buffers.

Clock Input Waveform

XTAL1

Continued

T

CH

- 10 -

F

OP, TCP

T

CL

W78C33

PSEN

RD

PARAMETER SYMBOL MIN. TYP. MAX. UNIT NOTES

Operating Speed FOP 0 - 40 MHz 1 Clock Period TCP 25 - - nS 2 Clock High TCH 10 - - nS 3 Clock Low TCL 10 - - nS 3

Notes:

1. The clock may be stopped indefinitely in either state.

2. The TCP specification is used as a reference in other specifications.

3. There are no duty cycle requirements on the XTAL1 input.

Program Fetch Cycle

PARAMETER SYMBOL MIN. TYP. MAX. UNIT NOTES

Address Valid to ALE Low TAAS Address Hold after ALE Low TAAH

ALE Low to

Low to Data Valid Data Hold after Data Float after

Low

High

TAPL TPDA - - 2 TCP nS 2 TPDH 0 - 1 TCP nS 3 TPDZ 0 - 1 TCP nS

ALE Pulse Width TALW

Pulse Width

TPSW

1 TCP-∆ 1 TCP-∆ 1 TCP-∆

2 TCP-∆ 3 TCP-∆

- - nS 4

- - nS 1, 4

1Tcp

1Tcp+∆

nS 4

2 TCP - nS 4 3 TCP - nS 4

Notes:

1. P0.0−P0.7, P2.0−P2.7 remain stable throughout entire memory cycle.

2. Memory access time is 3 TCP.

3. Data have been latched internally prior to

4. "∆" ( due to buffer driving delay and wire loading) is 20 nS.

going high.

Data Read Cycle

PARAMETER SYMBOL MIN. TYP. MAX. UNIT NOTES

ALE Low to RD Low

Low to Data Valid Data Hold after RD High Data Float after RD High

Pulse Width

Notes:

1. Data memory access time is 8 TCP.

2. "∆" (due to buffer driving delay and wire loading) is 20 nS.

TDAR TDDA - - 4 TCP nS 1 TDDH 0 - 2 TCP nS TDDZ 0 - 2 TCP nS TDRD

3 TCP-∆

6 TCP-∆

- 11 - Revision A1

-

3 TCP+∆

nS 1, 2

6 TCP - nS 2

Publication Release Date: October 1997

Data Write Cycle

WR

PARAMETER SYMBOL MIN. TYP. MAX. UNIT

ALE Low to WR Low Data Valid to WR Low Data Hold from WR High

Pulse Width

Note: "∆" ( due to buffer driving delay and wire loading) is 20 nS.

TDAW

TDAD TDWD TDWR

3 TCP-∆ 1 TCP-∆ 1 TCP-∆ 6 TCP-∆

-

3 TCP+∆

- - nS

6 TCP - nS

Port Access Cycle

PARAMETER SYMBOL MIN. TYP. MAX. UNIT

Port Input Setup to ALE Low TPDS 1 TCP - - nS Port Input Hold from ALE Low TPDH 0 - - nS Port Output to ALE TPDA 1 TCP - - nS

W78C33

nS

Note: Ports are read during S5P2, and output data becomes available at the end of S6P2. The timing data are referenced to

ALE, since it provides a convenient reference.

TIMING WAVEFORMS

Program Fetch Cycle

S1

S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6

XTAL1

T

ALW

ALE

T

APL

PSEN

T

PSW

T

AAS

PORT 2

T

A0-A7

PDA

T

PDH,

PDZ

DataCode

A0-A7

Code

A0-A7

Data

A0-A7

PORT 0

T

AAH

- 12 -

Timing Waveforms, continued

Data Read Cycle

XTAL1

ALE

PSEN

W78C33

S2 S3S5 S6 S1S2 S3 S4S5 S6 S1S4

PORT 2

PORT 0

RD

Data Write Cycle

XTAL1

ALE

PSEN

PORT 2

A0-A7

T

DAR

A8-A15

T

DDA

A8-A15

T

DRD

DATA

T

DDH,TDDZ

S2 S3S5 S6 S1S2 S3 S4S1S5 S6S4

PORT 0

WR

A0-A7

T

DAW

T

DAD

DATA OUT

T

DWD

T

DWR

Publication Release Date: October 1997

- 13 - Revision A1

Timing Waveforms, continued

Port Access Cycle

XTAL1

ALE

W78C33

S5 S6 S1

T

PDS

PDH

TT

PDA

PORT

INPUT

SAMPLE

DATA OUT

- 14 -

TYPICAL APPLICATION CIRCUIT

Using External Program Memory and Crystal

V

8.2 K

CC

10 u

C1

CRYSTAL

C2

R

35 21

20

10

14 15 16

17 2

3

4

5

6 7 8 9

23 34

1

12

EA

XTAL1

XTAL2

RST

INT0 INT1

T0 T1

P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7

P4.0 P4.1 P4.2/INT3 P4.3/INT2

PSEN

P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7

P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7

RD WR

ALE TXD

RXD

43 42

41 40 39 38 37 36

24 25 26 27

29

28 30

31 19

18

33 13 11

32

AD0

AD1

AD2

AD3

AD4 AD5 AD6 AD7

A8 A9 A10

A11 A12 A13 A14

A15

AD0D0 3

AD1 AD2 AD3 AD4 AD5 AD6 AD7

GND

4 7 8 13 14 17 18

1

11

Q0

D1

Q1

D2

Q2

D3

Q3

D4

Q4

D5

Q5

D6

Q6

D7

Q7

OC G

74LS373

2

A0 A0A0 10 A1

5

A2

6

9

A3

12

A4

15

A5

16

A6 A7

19

A1 A2 A3 A4 A5 A6 A7 A8

A9 A10 A11 A12 A13 A14 A15

GND

9 8 7 6 5 4

3 25 24 21 23 2 26 27

1 20

22

A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15

CE OE

27512

W78C33

AD0

11

O0

12

AD1

O1

13

AD2

O2

15

AD3

O3

16

AD4

O4

17

AD5

O5

18

AD6

O6

19

AD7

O7

W78C33P

CRYSTAL C1 C2 R

16 MHz 30P 30P 24 MHz 15P 15P 33 MHz 10P 10P 6.8K 40 MHz 5P 5P 6.8K

Above table shows the reference values for crystal applications.

Note: C1, C2, R components refer to Figure A.

44-pin PLCC

Figure A

Publication Release Date: October 1997

- 15 - Revision A1

PACKAGE DIMENSIONS

44-pin PLCC

H

D

e

44 40

G

D

b b

1

6 1

7

17

L

θ

Seating Plane

W78C33

Dimension in inch Dimension in mm

Symbol

39

H

E

29

2818

A

2

A

1

y

G

E

c

A A A b b c D E

e

GD

G

H H E L y

Notes:

1. Dimension D & E do not include interlead flash.

2. Dimension b1 does not include dambar

protrusion/intrusion.

3. Controlling dimension: Inches

4. General appearance spec. should be based on final visual inspection spec.

Nom.

Min.

0.020

1

0.145

2

0.026

1

0.016

0.008

0.648

0.590

E

0.680

D

0.680

0.090

Max. Max.

0.185

0.150

0.155

0.028

0.032

0.022

0.018

0.010

0.014

0.653

0.658

0.6580.6530.648

0.050 BSC

0.610

0.630

0.6300.610

0.690

0.700

0.690

0.100

0.110

0.004

Min.

0.508

3.683

0.66

0.406

0.203

16.46

14.99

17.27

2.296

1.27

Nom.

3.81

0.711

0.457

0.254

16.59

15.49

15.4914.99

17.53

2.54

BSC

4.699

3.937

0.813

0.559

0.356

16.71

16.7116.5916.46

16.00

17.78

17.7817.53

2.794

0.10

44-pin QFP

1

11

Seating Plane

H

D

44

12

e

34

33

E

EH

22

b

Notes:

c

A

See Detail F

2

A

1

y

θ

L

L 1

Detail F

Dimension in inch

Symbol

A A

1

2

A b c D E

e

D

H

E

H L L1

y

θ

1. Dimension D & E do not include interlead flash.

2. Dimension b does not include dambar protrusion/intrusion.

3. Controlling dimension: Millimeter

4. General appearance spec. should be based on final visual inspection spec.

Nom.

Min.

--- ---

0.002

0.01 0.02 0.25

0.081

0.075

0.01

0.014

0.006 0.152

0.394

0.390

0.025

0.031

0.510 13.45

0.520

0.510

0.025

0.031

0.063

0.051 0.075 1.295

0

Dimension in mm

Min.

--- ---

0.05

1.90

0.25

9.9

0.635

12.95

0.65

Nom.

---

0.5

2.05

2.20

0.45

0.35

0.2540.101

10.00

10.1

10.00

0.952

0.80

13.2

13.4513.2

0.8

0.95

1.6

1.905

0

0.08

Max. Max.

---

0.087

0.018

0.0100.004

0.398

0.3980.394

0.036

0.530

0.037

0.003 7

7

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W78C33

Publication Release Date: October 1997

- 17 - Revision A1

W78C33

Headquarters

No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5792697 http://www.winbond.com.tw/ Voice & Fax-on-demand: 886-2-7197006

Winbond Electronics (H.K.) Ltd.

Rm. 803, World Trade Square, Tower II, 123 Hoi Bun Rd., Kwun Tong, Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064

Taipei Office

11F, No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-7190505 FAX: 886-2-7197502

Note: All data and specifications are subject to change without notice.

Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab.

2727 N. First Street, San Jose, CA 95134, U.S.A. TEL: 408-9436666 FAX: 408-5441798

- 18 -