Datasheet W49V002FAQ, W49V002FAP Datasheet (Winbond Electronics)

W49V002FA

256K × 8 CMOS FLASH MEMORY

WITH FWH INTERFACE

GENERAL DESCRIPTION

The W49V002FA is a 2-megabit, 3.3-volt only CMOS flash memory organized as 256K × 8 bits. The
device can be programmed and erased in-system with a standard 3.3V power supply. A 12-volt VPP is
not required. The unique cell architecture of the W49V002FA results in fast program/erase operations
with extremely low current consumption. This device can operate at two modes, Programmer bus
interface mode and FWH bus interface mode. As in the Programmer interface mode, it acts like the
traditional flash but with a multiplexed address inputs. But in the FWH interface mode, this device
complies with the Intel FWH specification. The device can also be programmed and erased using
standard EPROM programmers.

FEATURES

• Single 3.3-volt operations:

− 3.3-volt Read

− 3.3-volt Erase

− 3.3-volt Program

• Fast program operation:

− Byte-by-byte programming: 50 µS (typ.)

• Fast erase operation: 150 mS (typ.)

• Fast read access time: Tkq 11 nS

• Endurance: 10K cycles (typ.)

• Twenty-year data retention

• Hardware data protection

− #TBL & #WP serve as hardware protection

• One 16K bytes Boot Block with lockout

protection

• Two 8K bytes Parameter Blocks

• Four main memory blocks (with 32K bytes, 64K

bytes, 64K bytes, 64K bytes each)

• Low power consumption

− Active current: 40 mA (typ. for FWH)

• Automatic program and erase timing with

internal VPP generation

• End of program or erase detection

− Toggle bit

− Data polling

• Latched address and data

• TTL compatible I/O

• Available packages: 32L PLCC, 32L STSOP

Publication Release Date: February 19, 2002

- 1 - Revision A2

W49V002FA

T

v

#WE(FWH4)

DQ3(FWH3)

DQ2(FWH2)

DQ1(FWH1)

DQ0(FWH0)

PIN CONFIGURATIONS

A

NC
NC
NC

GND

A10(FGPI4)

R/#C(CLK)

V

NC

#RESET

A9(FGPI3)
A8(FGPI2)
A7(FGPI1)
A6(FGPI0)

A5(#WP)

A4(#TBL)

IC

DD

A7(FGPI1)
A6(FGPI0)

A5(#WP)
A4(#TBL)
A3(ID3)
A2(ID2)
A1(ID1)
A0(ID0)

DQ0(FWH0)

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

A

9

8
^

F

F

G

G

P

P

I

I

3

2
v

3

4

5
6
7

8

9
10
11
12
13

D

D

Q

Q

1

^

F

F

W

W

H

H
1
v

^

#
R
E
S
E

N
C

v

1

2

32L

PLCC

D

G

Q

N

2

3

D

^

^
F
W
H

2

3

v

v

32L

TSOP

R

#

C

^

C

V

L

D

K

D

v

1817161514

D

D

Q

Q

5

4

^

^

R

R

S

S

V

V

v

v

BLOCK DIAGRAM

#WP

#TBL

CLK

FWH[3:0]

FWH4

A

1

0

^
F
G

P

I
4

A[10:0]

DQ[7:0]

303132

29

IC

28

GND
NC

27
26

GND

25

VDD

24

#OE(#INIT)

23

#WE(FWH4)

22

NC

21

DQ7(RSV)

2019

D
Q
6

^
R
S
V
v

PIN DESCRIPTION

SYM. INTERFACE

IC * * Interface Mode Selection

#RESET * * Reset

#INIT * Initialize

Interface

IC

#RESET

#INIT

R/#C

Program­mer
Interface

#OE

#WE

PGM FWH

BOOT BLOCK
16K BYTES

PARAMETER
BLOCK1
8K BYTES

PARAMETER
BLOCK2
8K BYTES

MAIN MEMORY
BLOCK1
32K BYTES

MAIN MEMORY
BLOCK2
64K BYTES

MAIN MEMORY
BLOCK3
64K BYTES

MAIN MEMORY
BLOCK4
64K BYTES

#TBL * Top Boot Block Lock

#WP * Write Protect

CLK * CLK Input

FGPI[4:0] * General Purpose Inputs

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

#OE(#INIT)
NC

DQ7(RSV)
DQ6(RSV)
DQ5(RSV)
DQ4(RSV)

GND

A0(ID0)
A1(ID1)
A2(ID2)
A3(ID3)

ID[3:0] * Identification Inputs They

Are Internal Pull Down to
VSS

FWH[3:0]

FWH4

* Address/Data Inputs
* FWH Cycle Initial

R/#C * Row/Column Select

A[10:0] * Address Inputs

DQ[7:0] * Data Inputs/Outputs

#OE * Output Enable

#WE * Write Enable

VDD * * Power Supply

GND * * Ground

RSV * * Reserved Pins

NC * * No Connection

3FFFF
3C000

3BFFF

3A000
39FFF

38000
37FFF

30000
2FFFF

20000
1FFFF

10000
0FFFF

00000

PIN NAME

- 2 -

W49V002FA

FUNCTIONAL DESCRIPTION

Interface Mode Selection And Description

This device can be operated in two interface modes, one is Programmer interface mode, the other is
FWH interface mode. The IC pin of the device provides the control between these two interface
modes. These interface modes need to be configured before power up or return from #RESET. When
IC pin is set to high state, the device will be in the Programmer mode; while the IC pin is set to low
state (or leaved no connection), it will be in the FWH mode. In Programmer mode, this device just
behaves like traditional flash parts with 8 data lines. But the row and column address inputs are
multiplexed, which go through address inputs A[10:0]. For FWH mode, It complies with the FWH
Interface Specification. Through the FWH[3:0] to communicate with the system chipset .

Read (Write) Mode

In Programmer interface mode, the read (write) operation of the W49V002FA is controlled by #OE
(#WE). The #OE(#WE) is held low for the host to obtain(write) data from(to) the outputs(inputs). #OE
is the output control and is used to gate data from the output pins. The data bus is in high impedance
state when #OE is high. As for in the FWH interface mode, the read or write is determined by the "bit 0
& bit 1 of START CYCLE ". Refer to the FWH cycle definition for further details.

Reset Operation

The #RESET input pin can be used in some application. When #RESET pin is at high state, the device
is in normal operation mode. When #RESET pin is at low state, it will halt the device and all outputs will
be at high impedance state. As the high state re-asserted to the #RESET pin, the device will return to
read or standby mode, it depends on the control signals.

Chip Erase Operation

The chip-erase mode can be initiated by a six-byte command sequence. After the command loading
cycle, the device enters the internal chip erase mode, which is automatically timed and will be
completed within fast 150 mS (typical). The host system is not required to provide any control or timing
during this operation. If the boot block programming lockout is activated, only the data in the other
memory blocks will be erased to FF(hex) while the data in the boot block will not be erased (remains
as the same state before the chip erase operation). The entire memory array will be erased to FF(hex)
by the chip erase operation if the boot block programming lockout feature is not activated. The device
will automatically return to normal read mode after the erase operation completed. Data polling and/or
Toggle Bits can be used to detect end of erase cycle.

Sector Erase Operation

The seven sectors, one boot block and two parameter memory and four main blocks, can be erased
individually by initiating a six-byte command sequence. Sector address is latched on the falling #WE
edge of the sixth cycle, while the 30(hex) data input command is latched at the rising edge of #WE.
After the command loading cycle, the device enters the internal sector erase mode, which is
automatically timed and will be completed within fast 150 mS (typical). The host system is not required
to provide any control or timing during this operation. The device will automatically return to normal
read mode after the erase operation completed. Data polling and/or Toggle Bits can be used to detect
end of erase cycle.

Publication Release Date: February 19, 2002

- 3 - Revision A2

W49V002FA

Program Operation

The W49V002FA is programmed on a byte-by-byte basis. Program operation can only change logical
data "1" to logical data "0." The erase operation, which changed entire data in main memory and/or
boot block from "0" to "1", is needed before programming.

The program operation is initiated by a 4-byte command cycle (see Command Codes for Byte
Programming). The device will internally enter the program operation immediately after the byte­program command is entered. The internal program timer will automatically time-out (100 µS max. ­TBP) once it is completed and then return to normal read mode. Data polling and/or Toggle Bits can be
used to detect end of program cycle.

Boot Block Operation and Hardware Protection at Initial- #TBL & #WP

There are two alternatives to set the boot block. One is software command sequences method; the
other is hardware method. 16K-byte in the top location of this device can be locked as boot block,
which can be used to store boot codes. It is located in the last 16K bytes of the memory with the
address range from 3C000(hex) to 3FFFF(hex).

Please see Command Codes for Boot Block Lockout Enable for the specific code. Once this feature is
set, the data for the designated block cannot be erased or programmed (programming lockout), other
memory locations can be changed by the regular programming method.

Besides the software method, there is a hardware method to protect the top boot block and other
sectors. Before program/erase to this device, set the #TBL pin to low state and then the top boot block
will not be programmed/erased. When enabling hardware top boot block, #TBL being low state, it will
override the software method setting. That is, if #TBL is at low state, then top boot block cannot be
programmed/erased no matter how the software boot block lock setting.

Another pin, #WP, will protect the whole chip if this pin is set to low state before program/erase. The
enable of this pin will override the #TBL setting. That is, the top boot block cannot be
programmed/erased if this pin is set to low no matter how the #TBL or software boot block lock setting.

Hardware Data Protection

The integrity of the data stored in the W49V002FA is also hardware protected in the following ways:
(1) Noise/Glitch Protection: A #WE pulse of less than 15 nS in duration will not initiate a write cycle.
(2) VDD Power Up/Down Detection: The programming and read operation are inhibited when VDD is

less than 1.5V typical.

(3) Write Inhibit Mode: Forcing #OE low or #WE high will inhibit the write operation. This prevents

inadvertent writes during power-up or power-down periods.

(4) VDD power-on delay: When VDD has reached its sense level, the device will automatically time-out 5

mS before any write (erase/program) operation.

Data Polling (DQ7)- Write Status Detection

The W49V002FA includes a data polling feature to indicate the end of a program or erase cycle.
When the W49V002FA is in the internal program or erase cycle, any attempts to read DQ7 of the last
byte loaded will receive the complement of the true data. Once the program or erase cycle is
completed, DQ7 will show the true data. Note that DQ7 will show logical "0" during the erase cycle, and
when erase cycle has been completed it becomes logical "1" or true data.

- 4 -

W49V002FA

Toggle Bit (DQ6)- Write Status Detection

In addition to data polling, the W49V002FA provides another method for determining the end of a
program cycle. During the internal program or erase cycle, any consecutive attempts to read DQ6 will
produce alternating 0's and 1's. When the program or erase cycle is completed, this toggling between
0's and 1's will stop. The device is then ready for the next operation.

General Purpose Inputs Register

This register reads the FGPI[4:0] pins on the W49V002FA.This is a pass-through register which can
read via memory address FFBC0100(hex). Since it is pass-through register, there is no default value.

BIT FUNCTION

7 − 5

Product Identification

Reserved
4 Read FGPI4 pin status
3 Read FGPI3 pin status
2 Read FGPI2 pin status
1 Read FGPI1 pin status
0 Read FGPI0 pin status

The product ID operation outputs the manufacturer code and device code. Programming equipment
automatically matches the device with its proper erase and programming algorithms.

The manufacturer and device codes can be accessed by software operation. In the software access
mode, a six-byte (or JEDEC 3-byte) command sequence can be used to access the product ID for
programmer interface mode. A read from address 0000(hex) outputs the manufacturer code, DA(hex).
A read from address 0001(hex) outputs the device code, 32(hex).” The product ID operation can be
terminated by a three-byte command sequence or an alternate one-byte command sequence (see
Command Definition table).

As for FWH interface mode, a read from FFBC, 0000(hex) can output the manufacturer code,
DA(hex). A read from FFBC, 0001(hex) can output the device code 32(hex).

TABLE OF OPERATING MODES

Operating Mode Selection - Programmer Mode

(VHH = 12V ± 5%)

MODE PINS

Read VIL VIH VIH AIN Dout
Write VIH VIL VIH AIN Din
Standby X X VIL X High Z
Write Inhibit VIL X VIH X High Z/DOUT
X VIH VIH X High Z/DOUT
Output Disable VIH X VIH X High Z

#OE #WE #RESET

ADDRESS DQ.

Publication Release Date: February 19, 2002

- 5 - Revision A2

W49V002FA

Operating Mode Selection - FWH Mode

Operation modes in FWH interface mode are determined by "START Cycle" when it is selected. When
it is not selected, its outputs (FWH[3:0]) will be disable. Please reference to the "FWH Cycle
Definition".

TABLE OF COMMAND DEFINITION

COMMAND NO. OF 1ST CYCLE 2ND CYCLE 3RD CYCLE 4TH CYCLE 5TH CYCLE 6TH CYCLE

DESCRIPTION Cycles

Read 1 AIN D
Chip Erase 6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 10
Sector Erase 6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 SA 30
Byte Program 4 5555 AA 2AAA 55 5555 A0 AIN D
Boot Block Lockout 6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 40
Product ID Entry 3 5555 AA 2AAA 55 5555 90
Product ID Exit
Product ID Exit

(1)

3 5555 AA 2AAA 55 5555 F0

(1)

1 XXXX F0

Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data

OUT

IN

Notes:

1. The cycle means the write command cycle not the FWH clock cycle.

2. The Column Address / Row Address are mapped to the Low / High order Internal Address. i.e. Column Address
A[10:0] are mapped to the internal A[10:0], Row Address A[6:0] are mapped to the internal A[17:11]

3. Address Format: A14−A0 (Hex); Data Format: DQ7-DQ0 (Hex)

4. Either one of the two Product ID Exit commands can be used.

5. SA: Sector Address
SA = 3C000h to 3FFFFh for Boot Block

SA = 3A000h to 3BFFFh for Parameter Block1
SA = 38000h to 39FFFh for Parameter Block2
SA = 30000h to 37FFFh for Main Memory Block1
SA = 2XXXXh for Main Memory Block2
SA = 1XXXXh for Main Memory Block3
SA = 0XXXXh for Main Memory Block4

- 6 -

FWH CYCLE DEFINITION

Data Phase for Memory Cycle. The data transfer least significant nibble first

W49V002FA

FIELD NO. OF

CLOCKS

START 1 "1101b" indicates FWH Memory Read cycle; while "1110b" indicates FWH

Memory Write cycle.
IDSEL 1 This one clock field indicates which FWH component is being selected.
MSIZE 1 Memory Size. There is always show “0000b” for single byte access.
TAR 2 Turned Around Time
ADDR 7 Address Phase for Memory Cycle. FWH supports the 28 bits address

protocol. The addresses transfer most significant nibble first and least

significant nibble last. (i.e. Address[27:24] on FWH[3:0] first , and

Address[3:0] on FWH[3:0] last.)
SYNC N Synchronous to add wait state. "0000b" means Ready, "0101b" means

Short Wait, "0110b" means Long Wait, "1001b" for DMA only, "1010b"

means error, and other values are reserved.
DATA 2

and most significant nibble last. (i.e. DQ[3:0] on FWH[3:0] first , then

DQ[7:4] on FWH[3:0] last.)

DESCRIPTION

Publication Release Date: February 19, 2002

- 7 - Revision A2

Embedded Programming Algorithm

Write Program Command Sequence

W49V002FA

Start

(see below)

Increment Address

Program Command Sequence (Address/Command):

#Data Polling/ Toggle bit

No

Last Address

?

Programming Completed

5555H/AAH

2AAAH/55H

Yes

Pause T

BP

5555H/A0H

Program Address/Program Data

- 8 -

Embedded Erase Algorithm

W49V002FA

Start

Write Erase Command Sequence

(see below)

#Data Polling or Toggle

Successfully Completed

Erasure Completed

Chip Erase Command Sequence

(Address/Command):

5555H/AAH

2AAAH/55H

5555H/80H

5555H/AAH

Individual Sector Erase

Command Sequence

(Address/Command):

5555H/AAH

2AAAH/55H

5555H/80H

5555H/AAH

Pause

TEC/T

SEC

2AAAH/55H

5555H/10H

2AAAH/55H

Sector Address/30H

Publication Release Date: February 19, 2002

- 9 - Revision A2

Embedded #Data Polling Algorithm

Read Byte

(DQ0 - DQ7)

Address = VA

W49V002FA

Start

VA = Byte address for programming

= Any of the sector addresses within

the sector being erased during sector

erase operation

= Valid address equals any sector group

address during chip erase

No

Embedded Toggle Bit Algorithm

DQ7 = Data

?

Yes

Pass

Start

Read Byte

(DQ0 - DQ7)

Address = Don't Care

Yes

DQ6 = Toggle

?

No

Pass

- 10 -

W49V002FA

Software Product Identification and Boot Block Lockout Detection Acquisition
Flow

Product
Identification
Entry (1)

Load data AA

to

address 5555

Load data 55

to

address 2AAA

Load data 90

to

address 5555

Pause 10 S

µ

Product

Identification
and Boot Block
Lockout Detection

Mode (3)

Read address = 00000

data = DA

Read address = 00001

data = 32 (Hex)

Read address = 00002

DQ0 of data outputs = 1/0

(2)

(2)

(4)

Product
Identification Exit(6)

Load data AA

to

address 5555

Load data 55

to

address 2AAA

Load data F0

to

address 5555

Pause 10 S

Normal Mode

µ

(5)

Notes for software product identification/boot block lockout detection:
(1) Data Format: DQ7 − DQ0 (Hex); Address Format: A14 − A0 (Hex)
(2) A1 − A17 = VIL; manufacture code is read for A0 = VIL; device code is read for A0 = VIH.

(3) The device does not remain in identification and boot block lockout detection mode if power down.
(4) If the DQ0 of output data is "1," the boot block programming lockout feature is activated; if the DQ0 of output data "0," the

lockout feature is inactivated and the block can be programmed.

(5) The device returns to standard operation mode.
(6) Optional 1-write cycle (write F0 hex at XXXX address) can be used to exit the product identification/boot block lockout

detection.

Publication Release Date: February 19, 2002

- 11 - Revision A2

Boot Block Lockout Enable Acquisition Flow

Boot Block Lockout
Feature Set Flow

Load data AA

to

address 5555

Load data 55

to

address 2AAA

Load data 80

to

address 5555

Load data AA

to

address 5555

W49V002FA

Load data 55

to

address 2AAA

Load data 40

to

address 5555

Pause T

BP

Exit

- 12 -

W49V002FA

DC CHARACTERISTICS

Absolute Maximum Ratings

PARAMETER RATING UNIT

Power Supply Voltage to VSS Potential -0.5 to +4.1 V
Operating Temperature 0 to +70
Storage Temperature -65 to +150
D.C. Voltage on Any Pin to Ground Potential -0.5 to VDD +0.5 V
Transient Voltage (<20 nS) on Any Pin to Ground Potential -1.0 to VDD +0.5 V

Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability
of the device.

Programmer interface Mode DC Operating Characteristics

(VDD = 3.3V ± 5%, VGND= 0V, TA = 0 to 70° C)

°C
°C

PARAMETER SYM.

MIN. TYP. MAX.

Power Supply
Current

Input Leakage
Current

Output Leakage
Current

Input Low Voltage VIL - -0.3 - 0.8 V
Input High Voltage VIH - 2.0 - VDD +0.5 V
Output Low Voltage VOL IOL = 2.1 mA - - 0.45 V
Output High Voltage VOH IOH = -0.1mA 2.4

ICC In Read or Write mode, all DQs open

Address inputs = 3.0V/0V, at f = 3 MHz

ILI VIN = GND to VDD - - 10

ILO VOUT = GND to VDD - - 10

TEST CONDITIONS LIMITS UNIT

- 20

- - V

30 mA

µA

µA

Publication Release Date: February 19, 2002

- 13 - Revision A2

FWH interface Mode DC Operating Characteristics

Input Low Voltage for

(VDD = 3.3V ±5 %, VGND = 0V, TA = 0 to 70° C)

W49V002FA

Power Supply
Current

Standby Current ISB1 FWH4 = 0.9 VDD, CLK = 33 MHz,

Standby Current ISB2 FWH4 = 0.1 VDD, CLK = 33 MHz,

Input Low Voltage VIL - -0.5 - 0.3 VDD
Input High Voltage VIH - 0.5 VDD

#INIT
Input High Voltage

for #INIT
Output Low Voltage VOL IOL = 1.5 mA - - 0.1 VDD
Output High Voltage VOH IOH = -0.5 mA 0.9 VDD

PARAMETER SYM.

MIN. TYP. MAX.

ICC All Iout = 0A, CLK = 33 MHz,

VILI - -0.5V - 0.2 VDD

VIHI

TEST CONDITIONS LIMITS UNIT

in FWH mode operation.

all inputs = 0.9 VDD/ 0.1 VDD, no
internal operation

all inputs = 0.9 VDD/ 0.1 VDD,
no internal operation

- 1.35V

- 40 60 mA

- 20 100

- 3 10 mA

- VDD +0.5 V

- VDD +0.5 V

- - V

µA

V

V

V

Power-up Timing

PARAMETER SYMBOL TYPICAL UNIT

Power-up to Read Operation TPU. READ 100
Power-up to Write Operation TPU. WRITE 5 mS

µS

CAPACITANCE

(VDD = 3.3V, TA = 25° C, f = 1 MHz)

PARAMETER SYMBOL CONDITIONS MAX. UNIT

I/O Pin Capacitance CI/O VI/O = 0V 12 pF
Input Capacitance CIN VIN = 0V 6 pF

- 14 -

PROGRAMMER INTERFACE MODE AC CHARACTERISTICS

AC Test Conditions

PARAMETER CONDITIONS

Input Pulse Levels 0V to 0.9 VDD
Input Rise/Fall Time < 5 nS
Input/Output Timing Level 1.5V/1.5V
Output Load 1 TTL Gate and CL = 30 pF

AC Test Load and Waveform

+3.3V

W49V002FA

D

OUT

30 pF

(Including Jig and

Scope)

1.8K

1.3K

Ω

Input

0.9V

DD

Ω

0V

Test Point

1.5V

Output

1.5V

Test Point

Publication Release Date: February 19, 2002

- 15 - Revision A2

W49V002FA

Programmer Interface Mode AC Characteristics, continued

AC Characteristics

Read Cycle Timing Parameters

(VDD = 3.3V ± 5%, VGND = 0V, TA = 0 to 70° C)

PARAMETER SYMBOL W49V002FA UNIT

MIN. MAX.

Read Cycle Time TRC 300 - nS
Row/Column Address Set Up Time TAS 50 - nS
Row/Column Address Hold Time TAH 50 - nS
Address Access Time TAA - 200 nS
Output Enable Access Time TOE - 100 nS
#OE Low to Active Output TOLZ 0 - nS
#OE High to High-Z Output TOHZ - 50 nS
Output Hold from Address Change TOH 0 - nS

Write Cycle Timing Parameters

PARAMETER SYMBOL MIN. TYP. MAX. UNIT

Reset Time TRST 1 - ­Address Setup Time TAS 50 - - nS
Address Hold Time TAH 50 - - nS
R/#C to Write Enable High Time TCWH 50 - - nS
#WE Pulse Width TWP 100 - - nS
#WE High Width TWPH 100 - - nS
Data Setup Time TDS 50 - - nS
Data Hold Time TDH 50 - - nS
#OE Hold Time TOEH 0 - - nS
Byte programming Time TBP - 50 100
Erase Cycle Time TEC - 0.15 0.2 S

Note: All AC timing signals observe the following guidelines for determining setup and hold times:
(a) High level signal's reference level is input high and (b) low level signal's reference level is input low.
Ref. to the AC testing condition.

µS

µS

Data Polling and Toggle Bit Timing Parameters

PARAMETER SYMBOL W49V002FA UNIT

MIN. MAX.

#OE to Data Polling Output Delay TOEP - 40 nS
#OE to Toggle Bit Output Delay TOET - 40 nS

- 16 -

W49V002FA

TIMING WAVEFORMS FOR PROGRAMMER INTERFACE MODE

Read Cycle Timing Diagram

#RESET

A[10:0]

#C R/

#WE

#OE

DQ[7:0]

V

High-Z

T

RST

IH

Write Cycle Timing Diagram

T

RST

#RESET

T

RC

Row AddressColumn Address

T

T

AH

AS

T

T

AH

AS

T

AA

TOE

T

OLZ

Column Address

T OH

T

OHZ

Data Valid

Row Address

High-Z

A[10:0]

#C R/

#OE

#WE

DQ[7:0]

Column Address Row Address

T

AS

T

T

AH

AS

T

WP

T

AH

T

CWH

T

DS

Data Valid

T

OEH

T

WPH

T

DH

Publication Release Date: February 19, 2002

- 17 - Revision A2

Timing Waveforms for Programmer Interface Mode, continued

Note: The internal address A[17:0] are converted from external Column/Row address.

Program Cycle Timing Diagram

A[10:0]

(Internal A[17:0])

DQ[7:0]

#C R/

5555

AA

2AAA

Byte Program Cycle

5555

Programmed Address

A055

W49V002FA

Data-In

#OE

#WE

Column/Row Address are mapped to the Low/High order internal address.
i.e. Column Address A[10:0] are mapped to the internal A[10:0],
Row Address A[6:0] are mapped to the internal A[17:11].

WP

T

Byte 0

T

WPH

#DATA Polling Timing Diagram

A[10:0]

(Internal A[17:0])

#C R/

#WE

#OE

An An An An

Byte 1

Byte 2

Byte 3

BP

T

Internal Write Start

DQ7

X X

- 18 -

T

OEP

T

BP or

T

EC

X

Timing Waveforms for Programmer Interface Mode, continued

Note: The internal address A[17:0] are converted from external Column/Row address.

Column/Row Address are mapped to the Low/High order internal address.
Six-byte code for 3.3V-only software chip erase

Toggle Bit Timing Diagram

A[10:0]

#C R/

#WE

#OE

T

OET

DQ6

T

T

BP or

W49V002FA

EC

Boot Block Lockout Enable Timing Diagram

A[10:0]

(Internal A[17:0])

DQ[7:0]

#C R/

#OE
#WE

i.e. Column Address A[10:0] are mapped to the internal A[10:0],
Row Address A[6:0] are mapped to the internal A[17:11].

5555

SB0

2AAA

AA

WP

T

WPH

T

5555

55

SB1

SB2

5555

80

AA

SB3

2AAA

SB4

5555

55

SB5

40

WC

T

- 19 - Revision A2

Publication Release Date: February 19, 2002

Timing Waveforms for Programmer Interface Mode, continued

Note: The internal address A[17:0] are converted from external Column/Row address.

Column/Row Address are mapped to the Low/High order internal address.
Six-byte code for 3.3V-only software chip erase

Note: The internal address A[17:0] are converted from external Column/Row address.

Chip Erase Timing Diagram

A[10:0]

(Internal A[17:0])

5555

2AAA

5555

5555

2AAA

W49V002FA

5555

DQ[7:0]

#C R/

#OE

#WE

AA

T

WP

T

WPH

SB0 SB3

i.e. Column Address A[10:0] are mapped to the internal A[10:0],
Row Address A[6:0] are mapped to the internal A[17:11].

Sector Erase Timing Diagram

sector erase

A[10:0]

5555

(Internal A[17:0])

DQ[7:0]

2AAA

AA 55

55

Six-byte code for 3.3V-only software

80

SB2

SB1

5555 5555 2AAA

80

AA

AA

55

SB4

10

T

EC

Internal Erasure Starts

SB5

SA

55

30

#C R/

#OE
#WE

Column/Row Address are mapped to the Low/High order internal address.
i.e. Column Address A[10:0] are mapped to the internal A[10:0],
Row Address A[6:0] are mapped to the internal A[17:11].

SA = Sector Address, Please ref. to the "Table of Command Definition"

T

SB0

WP

T

WPH

- 20 -

SB1

SB2

SB3

SB4

SB5

T

EC

Internal Erase starts

FWH INTERFACE MODE AC CHARACTERISTICS

AC Test Conditions

PARAMETER CONDITIONS

Input Pulse Levels 0.6 VDD to 0.2 VDD
Input Rise/Fall Slew Rate 1 V/nS
Input/Output Timing Level 0.4 VDD / 0.4 VDD
Output Load 1 TTL Gate and CL = 10 pF

AC Test Load and Waveform

W49V002FA

D

OUT

10 pF

Test when output from low to high

25

Ω

D

OUT

10 pF

Test when output from high to low

V

25

DD

Ω

0.6V

0.2V

Input

DD

DD

Test Point

0.4V

DD

Output

Test Point

0.4V

DD

Read/Write Cycle Timing Parameters

(VDD = 3.3V ± 5%, VGND = 0V, TA = 0 to 70° C)

PARAMETER SYMBOL W49V002FA UNIT

MIN. MAX.

Clock Cycle Time TCYC 30 - nS
Input Set Up Time TSU 7 - nS
Input Hold Time THD 0 - nS
Clock to Data Valid TKQ - 11 nS

Reset Timing Parameters

PARAMETER SYM. MIN. TYP. MAX. UNIT

VDD stable to Reset Active TPRST 1 - - mS
Clock Stable to Reset Active TKRST 100 - ­Reset Pulse Width TRSTP 100 - - nS
Reset Active to Output Float TRSTF - - 50 nS
Reset Inactive to Input Active TRST 1 - -

Note: All AC timing signals observe the following guidelines for determining setup and hold times:
(a) High level signal's reference level is input high and (b) low level signal's reference level is input low.
Ref. to the AC testing condition.

µS

µS

Publication Release Date: February 19, 2002

- 21 - Revision A2

TIMING WAVEFORMS FOR FWH INTERFACE MODE

Next Start

Note: When A22 = high, the host will read the BIOS code from the FWH device.
While A22 = low, the host will read the GPI (Add = FFBC0100) or

Product ID (Add = FFBC0000/FFBC0001) from the FWH device

Next Start

Read Cycle Timing Diagram

T

CYC

CLK

W49V002FA

#RESET

FWH4

FWH[3:0]

T

SU

Start
FWH
Read

1101b

1 Clock

T

HD

IDSEL

0000b

1 Clock

XXXXb

XA[22]XXb XXA[17:16]

Load Address in 7 Clocks

Write Cycle Timing Diagram

CLK

#RESET

FWH4

Start
FWH

IDSEL

FWH[3:0]

Write

1110b

1 Clock

0000b

1 Clock

XXXXb XXXXb

Load Address in 7 Clocks

T

CYC

XXA[17:16]b

Address

A[15:12]

Address

A[15:12]

T

SU

A[11:8] A[7:4]

A[7:4]

A[11:8]

T

HD

A[3:0]

M Size

0000b]

1111b

TAR

Tri-State

2 Clocks

Sync

0000b

1 Clock

T

KQ

D[3:0]

Data out 2 Clocks

Data

D[7:4]

TAR

0000b

1 Clock

THDT

SU

A[3:0]

M Size

0000b

D[3:0]

Load Data in 2 Clocks

Data

D[7:4]

TAR

1111b

2 Clocks

Tri-State

Sync

0000b

1 Clock

TAR

0000b

1 Clock

- 22 -

Timing Waveforms for FWH Interface Mode, continued

Program Cycle Timing Diagram

CLK

#RESET

FWH4

FWH[3:0

IDSEL

CLK

FWH4

CLK

#RESET

]

1st Start

1110b

1 Clock

2nd Start

1110b

1 Clock

0000b

1 Clock

IDSEL

0000b

1 Clock

XXXXb

XXXXb

XXXXb

XXXXb

]

#RESET

FWH[3:0

Address

XXXXb

X101b

Load Address "5555" in 7 Clocks

Write the 1st command to the device in FWH mode.

Address

X010b

XXXXb

Load Address "2AAA" in 7 Clocks

Write the 2nd command to the device in FWH mode.

0101b 0101b 0101b

1010b 1010b 1010b

M Size

0000b

1010b 1010b

Load Data "AA" in 2 Clocks

M Size

0000b

0101b 0101b

Load Data "55"
in 2 Clocks

Data

Data

W49V002FA

TAR

1111b

TAR

1111b

2 Clocks

Tri-State

Tri-State

0000b

1 Clock2 Clocks

Sync

0000b

1 Clock

Sync

1111b Tri-State

1111b

TAR

2 Clocks

TAR

2 Clocks

Tri-State

Start next
command

1 Clock

Start next
command

1 Clock

FWH4

TAR

Tri-State

Start next
command

1 Clock

FWH[3:0

]

3rd Start

1110b

1 Clock

IDSEL

0000b

1 Clock

XXXXb

XXXXb

XXXXb

Load Address "5555" in 7 Clocks

Address

0101b 0101b 0101b

X101b

M Size

0000b

Data

1010b0000b

Load Data "A0"
in 2 Clocks

1111b

TAR

2 Clocks

Tri-State

Sync

0000b

1 Clock

1111b

2 Clocks

Write the 3rd command to the device in FWH mode.

CLK

#RESET

FWH4

FWH[3:0

]

4th Start

1110b

1 Clock

IDSEL

0000b

1 Clock

XXXXb

XXXXb

Address

A[15:12]

XXA[17:16]b

Load Ain in 7 Clocks

A[11:8] A[7:4] A[3:0]

M Size

0000b

D[3:0] 1111b

Load Din in 2 Clocks

Data

D[7:4]

TAR

2 Clocks

Tri-State

Sync

0000b

1 Clock

1111b

TAR

Tri-State

2 Clocks

Internal
program start

Internal
program start

Write the 4th command(target location to be programmed) to the device in FWH mode.

Publication Release Date: February 19, 2002

- 23 - Revision A2

Timing Waveforms for FWH Interface Mode, continued

#DATA Polling Timing Diagram

CLK

#RESET

FWH4

W49V002FA

FWH[3:0]

CLK

#RESET

FWH4

FWH[3:0]

CLK

#RESET

FWH4

FWH[3:0]

Start

1110b

1 Clock

Start

1101b

1 Clock

Start

1101b

1 Clock

IDSEL

0000b

1 Clock

IDSEL

0000b

1 Clock

IDSEL

0000b

1 Clock

XXXXb

XXXXb

XXXXb

Data

Dn[7:4]

Dn[3:0]

Load Data "Dn"
in 2 Clocks

TAR

Tri-State

1111b

XXXXb

XXA[17:16]b

Address

An[15:12]

An[11:8]

An[7:4] An[3:0]

M Size

0000b

Load Address "An" in 7 Clocks

Write the last command(program or erase) to the device in FWH mode.

XXXXb

XXXXb

XXA[17:16]b

Address

An[15:12]

An[11:8] An[7:4]

An[3:0]

M Size

0000b

Load Address in 7 Clocks

Read the DQ7 to see if the internal write complete or not.

XXXXb

XXA[17:16]b

Load Address in 7 Clocks

Address

An[15:12] An[11:8] An[7:4]

An[3:0]

M Size

0000b

1111b

TAR

Tri-State

2 Clocks

When internal write complete, the DQ7 will equal to Dn7.

1111b

Sync

0000b

1 Clock2 Clocks

Sync

0000b

1 Clock

TAR

Tri-State

2 Clocks

XXXXb

Data out 2 Clocks

Data out 2 Clocks

Data

Data

Sync

0000b

1 Clock

Dn7,xxx

Dn7,xxxXXXXb

1111b

1111b

1111b

TAR

Tri-State

2 Clocks

TAR

2 Clocks

TAR

2 Clocks

Next Start

1 Clock

Next Start

Tri-State

1 Clock

Next Start

Tri-State

1 Clock

- 24 -

Timing Waveforms for FWH Interface Mode, continued

Toggle Bit Timing Diagram

CLK

#RESET

FWH4

W49V002FA

FWH[3:0]

CLK

#RESET

FWH4

FWH[3:0]

CLK

#RESET

FWH4

FWH[3:0]

Start
1110b

1 Clock

Start
1101b

1 Clock

Start

1101b

1 Clock

IDSEL

0000b

1 Clock

IDSEL

0000b

1 Clock

IDSEL

0000b

1 Clock

XXXXb

XXXXb

XXXXb

Data

D[7:4]

D[3:0]

Load Data "Dn"
in 2 Clocks

TAR

Tri-State

1111b

XXXXb

XXA[17:16]b

Address

A[15:12]

A[7:4] A[3:0]

M Size

0000b

Load Address "An" in 7 Clocks

Write the last command(program or erase) to the device in FWH mode.

XXXXb

XXXXb

Address

XXXXb

XXXXb

XXXXb XXXXb

M Size

0000b

Load Address in 7 Clocks

Read the DQ6 to see if the internal write complete or not.

XXXXb

XXXXb

Load Address in 7 Clocks

Address

XXXXb

XXXXb

XXXXb

XXXXb

M Size

0000b

1111b

TAR

Tri-State

2 Clocks

When internal write complete, the DQ6 will stop toggle.

1111b

Sync

0000b

1 Clock2 Clocks

Sync

0000b

1 Clock

TAR

Tri-State

Data

XXXXb

Data out 2 Clocks

Data

XXXXb

Data out 2 Clocks

Sync

0000bA[11:8]

1 Clock2 Clocks

X,D6,XXb

X,D6,XXb

1111b

1111b

1111b

TAR

2 Clocks

TAR

2 Clocks

TAR

2 Clocks

Next Start

Tri-State

1 Clock

Next Start

Tri-State

1 Clock

Next Start

Tri-State

1 Clock

Publication Release Date: February 19, 2002

- 25 - Revision A2

Timing Waveforms for FWH Interface Mode, continued

0101b

Boot Block Lockout Enable Timing Diagram

CLK

#RESET

FWH4

FWH[3:0]

#RESET

FWH[3:0]

#RESET

FWH4

FWH[3:0]

#RESET

FWH[3:0]

#RESET

FWH4

CLK

FWH4

CLK

IDSEL

1st Start

1110b

1 Clock

CLK

2nd Start

1110b

1 Clock

CLK

3rd Start

1110b

1 Clock

4th Start

1110b

1 Clock

0000b

1 Clock

IDSEL

0000b

1 Clock

IDSEL

0000b

1 Clock

IDSEL

0000b

1 Clock

XXXXb

XXXXb

XXXXb

XXXXb

XXXXb

XXXXb

XXXXb

XXXXb

Address

XXXXb

X101b

0101b

0101b

0101b

Load Address "5555" in 7 Clocks

Write the 1st command to the device in FWH mode.

Address

XXXXb

X010b

1010b

1010b 1010b

Load Address "2AAA" in 7 Clocks

Write the 2nd command to the device in FWH mode.

Address

XXXXb

X101b 0101b

0101b

0101b

Load Address "5555" in 7 Clocks

Write the 3rd command to the device in FWH mode.

Address

XXXXb

X101b 0101b 0101b 0101b

Load Address "5555" in 7 Clocks

Write the 4th command to the device in FWH mode.

M Size

0000b

M Size

0000b

M Size

0000b

M Size

0000b

Data

1010b 1010b

Load Data "AA"
in 2 Clocks

Data

0101b 0101b

Load Data "55"
in 2 Clocks

Data

1000b0000b

Load Data "80"
in 2 Clocks

1010b 1010b

Load Data "AA"
in 2 Clocks

1111b

1111b

1111b

1111b

TAR

2 Clocks

TAR

Tri-State

2 Clocks

TAR

Tri-State

TARData

Tri-State

2 Clocks

Tri-State

W49V002FA

TAR

2 Clocks

TAR

2 Clocks

TAR

TAR

2 Clocks

Tri-State

Tri-State

Tri-State

Start next
command

1 Clock

Start next
command

1 Clock

Start next
command

1 Clock

Start next
command

1 Clock

Sync

0000b

1 Clock

Sync

0000b

1 Clocks

Sync

0000b

1 Clock2 Clocks

Sync

0000b

1 Clock

1111b

1111b

1111b Tri-State

2 Clocks

1111b

FWH4

FWH[3:0]

5th Start

1110b

1 Clock

IDSEL

0000b

1 Clock

XXXXb

XXXXb

Address

XXXXb

X010b

1010b 1010b

Load Address "2AAA" in 7 Clocks

1010b

Write the 5th command to the device in FWH mode.

CLK

#RESET

FWH4

FWH[3:0]

6th Start

1110b

1 Clock

IDSEL

0000b

1 Clock

XXXXb

XXXXb

Address

XXXXb

X101b

Load Address "5555" 7 Clocks

0101b 0101b

Write the 6th command to the device in FWH

- 26 -

M Size

0000b

M Size

0000b

Data

0101b 0101b

Load Data "55"
in 2 Clocks

Data

0100b

0000b

Load Data "40"
in 2 Clocks

mode.

1111b

1111b

TAR

Tri-State

TAR

2 Clocks

Tri-State

Sync

0000b

1 Clock2 Clocks

0000b

1 Clock

Sync

TAR

1111b Tri-State

2 Clocks

TAR

1111b

Tri-State

2 Clocks

Start next
command

1 Clock

Internal
program start

Internal
program start

Timing Waveforms for FWH Interface Mode, continued

Chip Erase Timing Diagram

CLK

#RESET

FWH4

FWH[3:0]

#RESET

FWH[3:0]

#RESET

FWH[3:0]

#RESET

FWH4

FWH[3:0]

#RESET

FWH4

FWH[3:0]

#RESET

FWH4

FWH[3:0]

FWH4

FWH4

CLK

CLK

1st Start

1110b

1 Clock

IDSEL

0000b

1 Clock

XXXXb

XXXXb

Address

X101b

XXXXb

Load Address "5555" in 7 Clocks

Write the 1st command to the device in FWH mode.

CLK

2th Start

1110b

1 Clock

IDSEL

0000b

1 Clock

XXXXb

XXXXb

Address

XXXXb

1010b 1010b 1010b

X010b

Load Address "2AAA" in 7 Clocks

Write the 2nd command to the device in FWH mode.

CLK

3th Start

1110b

1 Clock

IDSEL

0000b

1 Clock

XXXXb

XXXXb

Address

XXXXb

0101b 0101b 0101b

X101b

Load Address "5555" in 7 Clocks

Write the 3rd command to the device in FWH mode.

CLK

4th Start

1110b

1 Clock

IDSEL

0000b

1 Clock

XXXXb

XXXXb

Address

XXXXb

0101b 0101b 0101b

X101b

Load Address "5555" in 7 Clocks

Write the 4th command to the device in FWH mode.

5th Start

1110b

1 Clock

IDSEL

0000b

1 Clock

XXXXb

XXXXb

Address

XXXXb

1010b 1010b 1010b

X010b

Load Address "2AAA" in 7 Clocks

Write the 5th command to the device in FWH mode.

6th Start

1110b

1 Clock

IDSEL

0000b

1 Clock

XXXXb

XXXXb

Address

XXXXb

X101b

0101b 0101b 0101b

Load Address "5555" in 7 Clocks

Write the 6th command to the device in FWH mode.

0101b 0101b 0101b

M Size

M Size

0000b

M Size

0000b

M Size

0000b

0000b

M Size

0000b

M Size

0000b

1010b 1010b

Load Data "AA"
in 2 Clocks

Data

0101b 0101b

Load Data "55"
in 2 Clocks

Data

1000b

0000b

Load Data "80"
in 2 Clocks

Data

1010b 1010b

Load Data "AA"
in 2 Clocks

0101b 0101b

Load Data "55"
in 2 Clocks

Data

0001b

0000b

Load Data "10"
in 2 Clocks

1111b

1111b

1111b

1111b

1111b

1111b

TARData

2 Clocks

TAR

TAR

TAR

2 Clocks

TARData

TAR

2 Clocks

Tri-State

Tri-State

Tri-State

Tri-State

Tri-State

Tri-State

W49V002FA

TAR

2 Clocks

TAR

2 Clocks

TAR

2 Clocks

TAR

2 Clocks

TAR

TAR

Tri-State

2 Clocks

Tri-State

Tri-State

Tri-State

Tri-State

Tri-State

Start next
command

1 Clock

Start next
command

1 Clock

Start next
command

1 Clock

Start next
command

1 Clock

Start next
command

1 Clock

Internal
erase start

Internal
erase start

1 Clock

0000b

1 Clock2 Clocks

Sync

0000b

1 Clock2 Clocks

0000b

1 Clock

Sync

0000b

1 Clock2 Clocks

0000b

1 Clock

0000b

Sync

Sync

Sync

Sync

1111b

1111b

1111b

1111b

1111b

2 Clocks

1111b

Publication Release Date: February 19, 2002

- 27 - Revision A2

Timing Waveforms for FWH Interface Mode, continued

Sector Erase Timing Diagram

CLK

#RESET

FWH4

FWH[3:0]

#RESET

1st Start

IDSEL

XXXXb

1110b

0000b

XXXXb

1 Clock1 Clock

CLK

Address

XXXXb

X101b

Load Address "5555" in 7 Clocks

Write the 1st command to the device in FWH mode.

0101b 0101b 0101b

M Size

0000b

Data

1010b 1010b

Load Data "AA"
in 2 Clocks

1111b

TAR

2 Clocks

Tri-State

W49V002FA

Start next

TAR

Sync

0000b

1 Clock

1111b

2 Clocks

command

Tri-State

1 Clock

FWH[3:0]

#RESET

FWH4

FWH[3:0]

#RESET

FWH4

FWH[3:0]

#RESET

FWH4

FWH[3:0]

CLK

#RESET

FWH4

FWH[3:0]

FWH4

CLK

2nd Start

1110b

IDSEL

XXXXb

0000b

XXXXb

1 Clock1 Clock

Address

XXXXb

1010b 1010b 1010b

X010b

Load Address "2AAA" in 7 Clocks

Write the 2nd command to the device in FWH mode.

CLK

3rd Start

1110b

IDSEL

XXXXb

0000b

XXXXb

1 Clocks1 Clocks

Address

XXXXb

X101b

0101b 0101b 0101b

Load Address "5555" in 7 Clocks

Write the 3rd command to the device in FWH mode.

CLK

4th Start

1110b

1 Clock

IDSEL

0000b

1 Clock

XXXXb

XXXXb

Address

XXXXb

0101b 0101b 0101b

X101b

Load Address "5555" in 7 Clocks

Write the 4th command to the device in FWH mode.

5th Start

1110b

IDSEL

0000b

XXXXb

XXXXb

XXXXb

Address

X010b

1010b

1010b 1010b

Load Address "2AAA" in 7 Clocks1 Clock1 Clock

Write the 5th command to the device in FWH mode.

6th Start

1110b

1 Clock

IDSEL

0000b

1 Clock

XXXXb

XXXXb

Address

SA[15:12]

XXA[17:16]b

XXXXb XXXXb XXXXb

Load Sector Address in 7 Clocks

Write the 6th command(target sector to be erased) to the device in FWH mode.

M

0000b

M Size

0000b

M Size

0000b

M Size

0000b

M Size

0000b

Data

0101b 0101b

Load Data "55"
in 2 Clocks

1000b0000b

Load Data "80"
in 2 Clocks

Data

1010b 1010b

Load Data "AA"
in 2 Clocks

Data

0101b 0101b

Load Data "55"
in 2 Clocks

Data

0000b

Load Din
in 2 Clocks

0011b

TAR

1111b

Tri-State

TARData

Tri-State

1111b

2 Clocks

TAR

1111b Tri-State

2 Clocks

TAR

Tri-State 0000b

1111b

2 Clocks

TAR

1111b

Tri-State

2 Clocks

Sync

0000b

1 Clock2 Clocks

Sync

0000b

1 Clocks

Sync

0000b

1 Clock

Sync

1 Clock

Sync

0000b

1 Clock

1111b

1111b

1111b Tri-State

1111b

1111b

TAR

2 Clocks

TAR

2 Clocks

TAR

2 Clocks

TAR

2 Clocks

TAR

Tri-State

2 Clocks

Tri-State

Tri-State

Tri-State

Start next
command

1 Clock

Start next
command

1 Clocks

Start next
command

1 Clock

Start next
command

1 Clock

Internal
erase start

Internal
erase start

- 28 -

Timing Waveforms for FWH Interface Mode, continued

Note: During the GPI read out mode, the DQ[4:0] will capture the states(High or Low) of the FGPI[4:0] input pins. The DQ[7:5] are reserved pins.

/0001b

FGPI Register/Product ID Readout Timing Diagram

CLK

#RESET

FWH4

FWH[3:0]

Start
1101b

IDSEL

1 Clock1 Clock

0000b

Address

A[27:24]

A[23:20] A[19:16]

Load Address "FFBC0100(hex)" in 7 Clocks for GPI Register
& "FFBC0000(hex)/FFBC0001(hex) for Product ID

0000b

0001b
/0000b

0000b

0000b

M Size

0000b

Tri-State

TAR

1111b

Sync

0000b

1 Clock2 Clocks

W49V002FA

Next Start

Tri-State

TAR

1111b

2 Clocks

1 Clock

Data

D[7:4]

D[3:0]

Data out 2 Clocks

Reset Timing Diagram

VDD

CLK

#RESET

FWH[3:0]

FWH4

T

PRST

T

KRST

T

RSTP

T

T

RST

RST

- 29 - Revision A2

Publication Release Date: February 19, 2002

ORDERING INFORMATION

W49V002FA

PART NO. ACCESS

TIME

W49V002FAP 11 25 20 32L PLCC
W49V002FAQ 11 25 20 32L STSOP

Notes:

1. Winbond reserves the right to make changes to its products without prior notice.

2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in
applications where personal injury might occur as a consequence of product failure.

(nS)

POWER SUPPLY

CURRENT MAX.

(mA)

STANDBY VDD

CURRENT MAX.

(µA)

PACKAGE

HOW TO READ THE TOP MARKING

Example: The top marking of 32L-PLCC W49V002FA

W49V002FAP

2123055C-082

132GHSA

1st line: winbond logo
2nd line: the part number: W49V002FAP
3rd line: the lot number
4th line: the tracking code: 132 G H SA
132: Packages made in ’01, week 32
G: Assembly house ID: A means ASE, G means Greatek, ...etc.
H: IC revision; A means version A, H means version H, ...etc.
SA: Process code

- 30 -

PACKAGE DIMENSIONS

2. Dimension b1 does not include dambar protrusion/intrusion.

32L PLCC

H

E

E

30

1

32

20

e

b

1b

E

G

5

13

L

θ

Seating Plane

4

14

W49V002FA

Dimension in Inches Dimension in mm

Symbol

Min. Nom. Max. Max.Nom.Min.

A

0.020

1

A

2

A

1

b

0.016

29

D

HD

21

GD

b

0.008

c

0.547

D

0.447

E
e

0.490

D

G

0.390

E

G

0.585

D

H

0.485

E

H

0.075

L

y

θ

0.140

0.50

0.1150.105 0.110

0.66 0.81

0.0320.026

0.028

0.018

0.010

0.550

0.450

0.050

0.510

0.410

0.590

0.490

0.090

°

0

0.022

0.014

0.553

0.453

0.530

0.430

0.595

0.495

0.095

0.004

0.41

0.20

13.89

11.35

1.12 1.420.044 0.056

12.45

14.86

12.32

1.91

°

10

Notes:

c

2A

A

1

A

y

1. Dimensions D & E do not include interlead flash.

3. Controlling dimension: Inches

4. General appearance spec. should be based on final
visual inspection sepc.

3.56

2.802.67 2.93

0.71

0.56

0.46

0.35

0.25

14.05

13.97

11.51

11.43

1.27

12.95

13.46

9.91

10.92

10.41

15.11

14.99

12.57

12.45

2.41

2.29

0.10

°

0

°

10

32L STSOP (8 x 14 mm)

D

H

D

c

e

E

b

£c

L

L

1

A

1

A

Y

A

2

Publication Release Date: February 19, 2002

- 31 - Revision A2

Dimension in Inches

Symbol

A

1

A

2

A

b

c
D
E

D

H
e

L

1

L

Y

θ

Min.

Nom. Max. Min. Nom.

0.047

0.040

0.006

0.041

0.002

0.035

0.007 0.009 0.010

0.004

-----

0.008

0.488

0.315

0.551

0.020

0.020

0.024

0.028

0.031

0.000

0.004

0 3 5

Dimension in mm

Max.

1.20

0.05

0.95

0.17

0.10

0.50

0.00
0

1.00

0.22 0.27

----- 0.21

12.40

8.00

14.00

0.50

0.60

0.80

3 5

0.15

1.05

0.70

0.10

VERSION HISTORY

VERSION DATE PAGE DESCRIPTION

A1 April 2001 - Initial Issued
A2 Feb. 19, 2002

6 Modify the description on start in TABLE OF

13 Add in Input High Voltage for #INIT (VIHI) parameter
Change VIL (max.) from 0.2 VDD to 0.3 VDD; VIH (min.)

29

4 Modify VDD Power Up/Down Detection in Hardware

Data Protection

COMMAND DEFINITION

7 − 10

Delete old flow chart and add embedded algorithm

from 0.6 VDD to 0.5 VDD.
Add the VIHI/ VILI for the #INIT pin input spec.

Add HOW TO READ THE TOP MARKING

W49V002FA

Headquarters

No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: [phone]
FAX: [phone]
http://www.winbond.com.tw/

Taipei Office

9F, No.480, Rueiguang Rd.,

Neihu Chiu, Taipei, 114,

Taiwan, R.O.C.
TEL: [phone]
FAX: [phone]

Please note that all data and specifications are subject to change without notice.

All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.

Winbond Electronics Corporation America

2727 North First Street, San Jose,
CA 95134, U.S.A.
TEL: [phone]
FAX: [phone]

Winbond Electronics Corporation Japan

7F Daini-ueno BLDG, 3-7-18
Shinyokohama Kohoku-ku,
Yokohama, 222-0033
TEL: [phone]
FAX: [phone]

- 32 -

Winbond Electronics (Shanghai) Ltd.

27F, 2299 Yan An W. Rd. Shanghai,
200336 China

TEL: [phone]

FAX: [phone]

Winbond Electronics (H.K.) Ltd.

Unit 9-15, 22F, Millennium City,

No. 378 Kwun Tong Rd.,
Kowloon, Hong Kong
TEL: [phone]
FAX: [phone]