Datasheet W49F201T-55B, W49F201T-55, W49F201T-45B, W49F201T-45, W49F201S-55B Datasheet (Winbond Electronics)

Preliminary W49F201

128K × 16 CMOS FLASH MEMORY

GENERAL DESCRIPTION

The W49F201 is a 2-megabit, 5-volt only CMOS flash memory organized as 128K × 16 bits. The
device can be programmed and erased in-system with a standard 5V power supply. A 12-volt VPP is
not required. The unique cell architecture of the W49F201 results in fast program/erase operations
with extremely low current consumption (compared to other comparable 5-volt flash memory
products). The device can also be programmed and erased using standard EPROM programmers.

FEATURES

• Single 5-volt operations:

− 5-volt Read/Erase/Program

• Fast Program operation:

− Word-by-Word programming: 50 µS (max.)

• Fast Erase operation: 60 mS (typ.)

• Fast Read access time: 45/55 nS

• Endurance: 1K/10K cycles (typ.)

• Ten-year data retention

• Hardware data protection

• Sector configuration

− One 8K words boot block with lockout

protection

− Two 8K words parameter blocks

− One 104K words (208K bytes) Main Memory

Array Blocks

• Low power consumption

− Active current: 25 mA (typ.)

− Standby current: 20 µA (typ.)

• Automatic program and erase timing with

internal VPP generation

• End of program or erase detection

− Toggle bit

− Data polling

• Latched address and data

• TTL compatible I/O

• JEDEC standard word-wide pinouts

• Available packages: 44-pin SOP, 48-pin TSOP

Publication Release Date: June 1999

- 1 - Revision A1

Preliminary W49F201

CE

OE

WE

PIN CONFIGURATIONS

1

NC

2

NC

3

NC

4

A7

5

A6

6

A5

7

A4

8

A3

9

A2
A1
A0

CE

GND

OE
DQ0
DQ8
DQ1
DQ9
DQ2

DQ10

DQ3

DQ11

A15

A14

A13

A12

A11

A10

A9

A8
NC
NC

WE

RESET

NC
NC
NC
NC

NC

A7

A6

A5

A4

A3

A2

A1

10
11
12
13
14
15
16
17
18
19
20
21
22

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

21

22
23
24

44-pin

SOP

48-pin
TSOP

BLOCK DIAGRAM

V

DD

V

44

RESET

43

WE

42

A8

41

A9

A10

40

A11

39

A12

38
37

A13

36

A14

35

A15
A16

34

NC

33

GND

32
31

DQ15

DQ7

30

DQ14

29

DQ6

28

DQ13

27

DQ5

26

DQ12

25

DQ4

24

23

V

CC

48

A16

47

NC
GND

46
45

DQ15

DQ7

44

DQ14

43

DQ6

42

DQ13

41

DQ5

40

DQ12

39

DQ4

38

VCC

37

DQ11

36

DQ3

35

DQ10

34

DQ2

33

DQ9

32

DQ1

31

DQ8

30

DQ0

29
28

OE
GND

27
26

CE

25

A0

SS

CE
OE

CONTROL

OUTPUT
BUFFER

WE

RESET

MAIN MEMORY

A0

A16

.
.

DECODER

104K WORDS

PARAMETER
BLOCK2
8K WORDS

PARAMETER
BLOCK1
8K WORDS

BOOT BLOCK
8K WORDS

PIN DESCRIPTION

SYMBOL PIN NAME

RESET
A0−A16

DQ0−DQ15

VDD Power Supply

GND Ground

NC No Connection

Reset
Address Inputs

Data Inputs/Outputs
Chip Enable
Output Enable
Write Enable

DQ0

.
.

DQ15

1FFFF

06000
05FFF

04000
03FFF

02000
01FFF

00000

- 2 -

Preliminary W49F201

FUNCTIONAL DESCRIPTION

Read Mode

The read operation of the W49F201 is controlled by CE and OE, both of which have to be low for
the host to obtain data from the outputs. CE is used for device selection. When CE is high, the chip
is de-selected and only standby power will be consumed. OE is the output control and is used to gate
data to the output pins. The data bus is in high impedance state when either CE or OE is high. Refer

to the timing waveforms for further details.

Reset Operation

The RESET input pin can be used in some application. When RESET pin is at high state, the device
is in normal operation mode. When RESET pin is driven low for at least a period of TRP, it will halts

the device and all outputs are at high impedance state. The device also resets the internal state
machine to read array data. The operation that was interrupted should be reinitiated once the device
is ready to accept another command sequence to assure data integrity. As the high state re-asserted

to the RESET pin, the device will return to read or standby mode, it depends on the control signals.
The system can read data TRH after the RESET pin returns to VIH. The other function for RESET pin
is temporary reset the boot block. By applying the 12V to RESET pin, the boot block can be

reprogrammed even though the boot block lockout function is enabled.

Boot Block Operation

There is one 8K-word boot block in this device, which can be used to store boot code. It is located in
the first 8K words of the memory with the address range from 0000(hex) to 1FFF(hex).

See Command Codes for Boot Block Lockout Enable for the specific code. Once this feature is set
the data for the designated block cannot be erased or programmed (programming lockout); other
memory locations can be changed by the regular programming method.

There is one condition that the lockout feature can be overrides. Just apply 12V to RESET pin, the
lockout feature will temporary be inactivated and the boot block can be erased/programmed. Once

the RESET pin returns to TTL level, the lockout feature will be activated again.
In order to detect whether the boot block feature is set on the 8K-words block, users can perform

software command sequence: enter the product identification mode (see Command Codes for
Identification/Boot Block Lockout Detection for specific code), and then read from address "0002
hex". If the output data in DQ0 is "1", the boot block programming lockout feature is activated; if the
output data in DQ0 is "0", the lockout feature is inactivated and the block can be
erased/programmed.

To return to normal operation, perform a three-byte command sequence (or an alternate single-word
command) to exit the identification mode. For the specific code, see Command Codes for
Identification/Boot Block Lockout Detection.

Chip Erase Operation

The chip-erase mode can be initiated by a six-word command sequence. After the command loading
cycle, the device enters the internal chip erase mode, which is automatically timed and will be

Publication Release Date: June 1999

- 3 - Revision A1

Preliminary W49F201

completed in a fast 100 mS (typical). The host system is not required to provide any control or timing
during this operation. The entire memory array will be erased to FF(hex). by the chip erase operation
if the boot block programming lockout feature is not activated. Once the boot block lockout feature is
activated, the chip erase function will erase all the sectors except the boot mode.

Sector Erase Operation

The three sectors, main memory and two parameters blocks, can be erased individually by initiating a
six-word command sequence. Sector address is latched on the falling WE edge of the sixth cycle
while the 30(hex) data input command is latched at the rising edge of WE. After the command
loading cycle, the device enters the internal sector erase mode, which is automatically timed and will
be completed in a fast 100 mS (typical). The host system is not required to provide any control or
timing during this operation. The device will automatically return to normal read mode after the erase
operation completed. Data polling and/or Toggle Bits can be used to detect end of erase cycle.

When the boot block lockout feature is inactivated, the boot block and the main memory block will be
erased together. Once the boot block is locked, only the main memory block will be erased by the
execution of sector erase operation.

Program Operation

The W49F201 is programmed on a word-by-word basis. Program operation can only change logical
data "1" to logical data "0" The erase operation (changed entire data in main memory and/or boot
block from "0" to "1" is needed before programming.

The program operation is initiated by a 4-word command cycle (see Command Codes for Word
Programming). The device will internally enter the program operation immediately after the word­program command is entered. The internal program timer will automatically time-out (50 µS max. ­TBP) once completed and return to normal read mode. Data polling and/or Toggle Bits can be used to
detect end of program cycle.

Hardware Data Protection

The integrity of the data stored in the W49F201 is also hardware protected in the following ways:
(1) Noise/Glitch Protection: A WE pulse of less than 15 nS in duration will not initiate a write cycle.

(2) VDD Power Up/Down Detection: The programming operation is inhibited when VDD is less than

2.5V typical.

(3) Write Inhibit Mode: Forcing OE low, CE high, or WE high will inhibit the write operation. This

prevents inadvertent writes during power-up or power-down periods.

(4) VDD power-on delay: When VDD has reached its sense level, the device will automatically time-out

5 mS before any write (erase/program) operation.

Data Polling (DQ7)- Write Status Detection

The W49F201 includes a data polling feature to indicate the end of a program or erase cycle. When
the W49F201 is in the internal program or erase cycle, any attempt to read DQ7 of the last word
loaded will receive the complement of the true data. Once the program or erase cycle is completed,
DQ7 will show the true data. Note that DQ7 will show logical "0" during the erase cycle, and become
logical "1" or true data when the erase cycle has been completed.

- 4 -

Preliminary W49F201

WE

CEOEWE

RESET

Toggle Bit (DQ6)- Write Status Detection

In addition to data polling, the W49F201 provides another method for determining the end of a
program cycle. During the internal program or erase cycle, any consecutive attempts to read DQ6 will
produce alternating 0's and 1's. When the program or erase cycle is completed, this toggling between
0's and 1's will stop. The device is then ready for the next operation.

Product Identification

The product ID operation outputs the manufacturer code and device code. Programming equipment
automatically matches the device with its proper erase and programming algorithms.

The manufacturer and device codes can be accessed by software or hardware operation. In the
software access mode, a six-word (or JEDEC 3-word) command sequence can be used to access the
product ID. A read from address 0000H outputs the manufacturer code, 00DA(hex). A read from
address 0001(hex) outputs the device code, 00AE(hex). The product ID operation can be terminated
by a three-word command sequence or an alternative one-word command sequence (see Command
Definition table).

In the hardware access mode, access to the product ID is activated by forcing CE and OE low,
high, and raising A9 to 12 volts.

TABLE OF OPERATING MODES

Operating Mode Selection

(VHH = 12V ±5 %)

MODE PINS

ADDRESS DQ.

Read VIL VIL VIH VIH AIN Dout
Erase/Program VIL VIH VIL VIH AIN Din
Standby VIH X X VIH X High Z
Erase/Program X VIL X VIH X High Z/DOUT
Inhibit X X VIH VIH X High Z/DOUT
Output Disable X VIH X VIH X High Z
Product ID VIL VIL VIH VIH A0 = VIL;

A1−A15 = VIL; A9 = VHH

VIL VIL VIH VIH A0 = VIH;

A1−A15 = VIL; A9 = VHH

Reset X X X VIL X High Z

Manufacturer Code
00DA (Hex)

Device Code
00AE (Hex)

Publication Release Date: June 1999

- 5 - Revision A1

TABLE OF COMMAND DEFINITION

Preliminary W49F201

COMMAND

DESCRIPTION

Read 1
Chip Erase 6
Main Memory Erase 6
Word Program 4
Boot Block Lockout 6
Product ID Entry 3
Product ID Exit
Product ID Exit

Notes:

1. Address Format: A14−A0 (Hex); Data Format: DQ15−DQ8 (Don't Care); DQ7-DQ0 (Hex)

2. Either one of the two Product ID Exit commands can be used.

3. SA: Sector Address
SA = 03XXXh for Parameter Block1
SA = 05XXXh for Parameter Block2
SA = 1FXXXh

- for Main Memory Block when Boot Block lockout feature is activated

- for both Boot Block and Main Memory Block when Boot Block lockout feature is inactivated

NO. OF 1ST CYCLE 2ND CYCLE 3RD CYCLE 4TH CYCLE 5TH CYCLE 6TH CYCLE

Cycles Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data

AIN D

OUT

5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 10
5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 SA 30
5555 AA 2AAA 55 5555 A0 AIN D
5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 40
5555 AA 2AAA 55 5555 90

(1)
(1)

5555 AA 2AAA 55 5555 F0

3

XXXX F0

1

IN

- 6 -

Preliminary W49F201

Command Flow

Command Codes for Word Program

WORD SEQUENCE ADDRESS DATA

0 Write 5555H AAH
1 Write 2AAAH 55H
2 Write 5555H A0H
3 Write Programmed-address Programmed-data

Pause 50 µS

Word Program Flow Chart

Word Program

Load data AA

to

address 5555

Load data 55

to

address 2AAA

Load data A0

to

address 5555

Load data Din

to

programmed-

address

Pause 50 S

Notes for software program code:
Data Format: DQ15−DQ8: Don't Care; DQ7-DQ0 (Hex)
Address Format: A14−A0 (Hex)

*It is not allowed to assert read command during the 4-word command sequence(program).
To assert the read command during the 4-word command sequence will abort programming procedure.

µ

Exit

Publication Release Date: June 1999

- 7 - Revision A1

Command Codes for Chip Erase

BYTE SEQUENCE ADDRESS DATA

1 Write 5555H AAH
2 Write 2AAAH 55H
3 Write 5555H 80H
4 Write 5555H AAH
5 Write 2AAAH 55H
6 Write 5555H 10H

Chip Erase Acquisition Flow

Load data AA

to

address 5555

Preliminary W49F201

Pause 200 mS

Load data 55

to

address 2AAA

Load data 80

to

address 5555

Load data AA

to

address 5555

Load data 55

to

address 2AAA

Load data 10

to

address 5555

Pause 200 mS

Exit

Notes for chip erase:
Data Format: DQ15-DQ8: Don't Care; DQ7−DQ0 (Hex)
Address Format: A14−A0 (Hex)

- 8 -

Command Codes for Sector Erase

BYTE SEQUENCE ADDRESS DATA

1 Write 5555H AAH
2 Write 2AAAH 55H
3 Write 5555H 80H
4 Write 5555H AAH
5 Write 2AAAH 55H
6 Write SA* 30H

Sector Erase Acquisition Flow

Load data AA

to

address 5555

Load data 55

to

address 2AAA

Preliminary W49F201

Pause 200 mS

Load data 80

to

address 5555

Load data AA

to

address 5555

Load data 55

to

address 2AAA

Load data 30

to

address SA*

Pause 200 mS

Exit

Notes for chip erase:
Data Format: DQ15-DQ8: Don't Care; DQ7−DQ0 (Hex)
Address Format: A14−A0 (Hex)

SA = 03XXX for parameter block1
SA = 05XXX for parameter block2
SA = 1FXXX

- for Main Memory Block when Boot Block lockout feature is activated

- for both Boot Block and Main Memory Block when Boot Block lockout feature is inactivated

Publication Release Date: June 1999

- 9 - Revision A1

Preliminary W49F201

Command Codes for Product Identification and Boot Block Lockout Detection

BYTE

SEQUENCE

ALTERNATE PRODUCT (6)

IDENTIFICATION/BOOT BLOCK

LOCKOUT DETECTION ENTRY

SOFTWARE PRODUCT

IDENTIFICATION/BOOT BLOCK LOCKOUT

DETECTION EXIT (7)

ADDRESS DATA ADDRESS DATA

1 Write 5555 AA 5555H AAH
2 Write 2AAA 55 2AAAH 55H
3 Write 5555 90 5555H F0H

Pause 10 µS Pause 10 µS

Software Product Identification and Boot Block Lockout Detection Acquisition Flow

Product
Identification
Entry (1)

Load data AA

to

address 5555

Load data 55

to

address 2AAA

Product
Identification

and Boot Block
Lockout Detection

Mode (3)

Read address = 0000

data = 00DA

(2)

Product
Identification Exit(7)

Load data AA

to

address 5555

Load data 55

to

address 2AAA

Load data 90

to

address 5555

Pause 10 S

Notes for software product identification/boot block lockout detection:
(1) Data Format: DQ15-DQ8 (Don't Care), DQ7−DQ0 (Hex); Address Format: A14−A0 (Hex)
(2) A1−A16 = VIL; manufacture code is read for A0 = VIL; device code is read for A0 = VIH.

(3) The device does not remain in identification and boot block lockout detection mode if power down.
(4) If the output data in DQ0 = 1, the boot block programming lockout feature is activated; if the output data in DQ0 = 0, the lockout feature is

inactivated and the block can be programmed.
(5) The device returns to standard operation mode.
(6) Optional 1-write cycle (write F0 hex at XXXX address) can be used to exit the product identification/boot block lockout detection.

µ

Read address = 0001

data = 00AE

Read address = 0002

data in DQ0 =1/0

(2)

(4)

Load data F0

to

address 5555

Pause 10 S

Normal Mode

µ

(5)

- 10 -

Command Codes for Boot Block Lockout Enable

BYTE SEQUENCE BOOT BLOCK LOCKOUT FEATURE SET

ADDRESS DATA

1 Write 5555H AAH
2 Write 2AAAH 55H
3 Write 5555H 80H
4 Write 5555H AAH
5 Write 2AAAH 55H
6 Write 5555H 40H

Pause 200 mS

Boot Block Lockout Enable Acquisition Flow

Boot Block Lockout
Feature Set Flow

Load data AA

to

address 5555

Preliminary W49F201

Notes for boot block lockout enable:
Data Format: DQ15-DQ8 Don't Care), DQ7−DQ0 (Hex)
Address Format: A14−A0 (Hex)

Load data 55

to

address 2AAA

Load data 80

to

address 5555

Load data AA

to

address 5555

Load data 55

to

address 2AAA

Load data 40

to

address 5555

Pause 200 mS

Exit

Publication Release Date: June 1999

- 11 - Revision A1

Preliminary W49F201

OE

CE=OE

CE

CE

DC CHARACTERISTICS

Absolute Maximum Ratings

PARAMETER RATING UNIT

Power Supply Voltage to Vss Potential -0.5 to +7.0 V
Operating Temperature 0 to +70
Storage Temperature -65 to +150

D.C. Voltage on Any Pin to Ground Potential except
Transient Voltage (<20 nS ) on Any Pin to Ground Potential -1.0 to VDD +1.0 V

Voltage on OE Pin to Ground Potential

Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the

device.

-0.5 to VDD +1.0 V

-0.5 to 12.5 V

°C
°C

DC Operating Characteristics

(VDD = 5.0V ±10%, VSS = 0V, TA = 0 to 70° C)

PARAMETER SYM. TEST CONDITIONS LIMITS UNIT

MIN. TYP. MAX.

Power Supply
Current

Standby VDD
Current (TTL input)

Standby VDD
Current

(CMOS input)

ICC

Address inputs = VIL/VIH, at f = 5 MHz

ISB1

Other inputs = VIL/VIH

ISB2

Other inputs = VDD -0.3V/GND

= VIL, WE= VIH, all DQs open

= VIH, all DQs open

= VDD -0.3V, all DQs open

- 25 50 mA

- 2 3 mA

- 20 100

µA

Input Leakage
Current

Output Leakage
Current

Input Low Voltage VIL - -0.3 - 0.8 V
Input High Voltage VIH - 2.0 - VDD +0.5 V
Output Low Voltage VOL IOL = 2.1 mA - - 0.45 V
Output High Voltage VOH IOH = -0.4 mA 2.4 - - V

ILI VIN = GND to VDD - - 10

ILO VOUT = GND to VDD - - 10

Publication Release Date: June 1999

- 12 - Revision A1

µA

µA

Preliminary W49F201

Power-up Timing

PARAMETER SYMBOL TYPICAL UNIT

Power-up to Read Operation TPU. READ 100
Power-up to Write Operation TPU. WRITE 5 mS

CAPACITANCE

(VDD = 5.0V, TA = 25° C, f = 1 MHz)

PARAMETER SYMBOL CONDITIONS MAX. UNIT

I/O Pin Capacitance CI/O VI/O = 0V 12 pf

Input Capacitance CIN VIN = 0V 6 pf

AC CHARACTERISTICS

AC Test Conditions

PARAMETER CONDITIONS

Input Pulse Levels 0V to 3.0V
Input Rise/Fall Time < 5 nS
Input/Output Timing Level 1.5V/1.5V
Output Load 1 TTL Gate and CL = 30 pF

µS

AC Test Load and Waveform

Input

3V

0V

D

OUT

30 pF

(Including Jig and

Scope)

Test Point

1.5V

Output

1.5V

Test Point

+5V

1.8K

1.3K

Ω

Ω

Publication Release Date: June 1999

- 13 - Revision A1

Preliminary W49F201

AC Characteristics, continued

Read Cycle Timing Parameters

(VCC = 5.0V ±10 %, VCC = 0V, TA = 0 to 70° C)

PARAMETER SYM. W49F201-45 W49F201-55 UNIT

MIN. MAX. MIN. MAX.

Read Cycle Time TRC
Chip Enable Access Time TCE
Address Access Time TAA
Output Enable Access Time TOE

Low to Active Output

CE

Low to Active Output

OE

High to High-Z Output

CE

High to High-Z Output

OE

Output Hold from Address Change TOH 0 - 0 - nS

Note: The parameter of TCLZ, TOLZ, TCHZ, TOHZ are characterized only and is not 100% tested.

TCLZ

TOLZ
TCHZ
TOHZ

45 - 55 - nS

- 45 - 55 nS

- 45 - 55 nS

- 35 - 40 nS

0 - 0 - nS
0 - 0 - nS

- 25 - 25 nS

- 25 - 25 nS

Write Cycle Timing Parameters

PARAMETER SYMBOL MIN. TYP. MAX. UNIT

Address Setup Time TAS 0 - - nS
Address Hold Time TAH 50 - - nS

WE and
WE and

High Setup Time

OE

High Hold Time

OE

Pulse Width

CE
WE Pulse Width
WE High Width

Data Setup Time TDS 50 - - nS
Data Hold Time TDH 10 - - nS
Word programming Time TBC - 35 50
Erase Cycle Time TEC - 60 200 mS

Note: All AC timing signals observe the following guidelines for determining setup and hold times:

(a) High level signal's reference level is VIH and (b) low level signal's reference level is VIL.

Setup Time

CE

Hold Time

CE

TCS 0 - - nS
TCH 0 - - nS
TOES 0 - - nS
TOEH 0 - - nS
TCP 70 - - nS
TWP 70 - - nS
TWPH 100 - - nS

µS

- 14 -

AC Characteristics, continued

OE

CE

WE

OE

CE

WE

Data Polling and Toggle Bit Timing Parameters

PARAMETER SYM. W49F201-45 W49F201-55 UNIT

to Data Polling Output Delay
to Data Polling Output Delay

High to OE Low for Data Polling
to Toggle Bit Output Delay
to Toggle Bit Output Delay

High to OE Low for Toggle Bit

TOEP ­TCEP ­TOEHP 100
TOET ­TCET ­TOEHT 100

Hardware Reset Timing Parameters

Preliminary W49F201

MIN. MAX. MIN. MAX.

35 - 40
45 - 55

- 100 ­35 - 40
45 - 55

- 100 -

nS
nS
nS
nS
nS
nS

PARAMETER SYM. MIN. MAX. UNIT

RESET Pulse Width
RESET High Time Before Read(1)

Note: 1. The parameters are characterized only and is not 100% tested.

TRP 500 - nS
TRH 50 - nS

Publication Release Date: June 1999

- 15 - Revision A1

TIMING WAVEFORMS

WE

Read Cycle Timing Diagram

Address A16-0

CE

OE

V

WE

DQ15-0

IH

High-Z

Preliminary W49F201

T

RC

T

CE

T

OE

T

T

OLZ

T

CLZ

Data Valid

T

OH

AA

T

Data Valid

T

CHZ

OHZ

High-Z

Controlled Command Write Cycle Timing Diagram

Address A16-0

WE

DQ15-0

T

AS

CE

OE

T

CS

T

OES

T

AH

T

WP

Data Valid

T

CH

T

OEH

T

WPH

T

DS

T

DH

- 16 -

Timing Waveforms, continued

CE

Controlled Command Write Cycle Timing Diagram

AS

T

Address A16-0

CE

T

OES

OE

WE

Preliminary W49F201

AH

T

T

TCPH

OEH

TCP

DQ15-0

High Z

Program Cycle Timing Diagram

Address A16-0

DQ15-0

CE

OE

WE

*

*

*Note: It is not allowed to assert read operation(CE# &OE# are both active) during the
command sequence. If read command is asserted during the command
sequence, then the device will return to read mode(abort write).

5555

WP

T

Word 0 Word 1

AA

TDS

Data Valid

TDH

Word Program Cycle

55552AAA

T

WPH

Word 2

Address

A055

Data-In

Word 3

BP

T

Internal Write Start

Publication Release Date: June 1999

- 17 - Revision A1

Timing Waveforms, continued

DATA

Polling Timing Diagram

Preliminary W49F201

Address A16-0

WE

CE

OE

DQ7

Toggle Bit Timing Diagram

Address A16-0

WE

An

T

OEHP

T

OEP

X

An An An

TCEP

X

T

T

EC

BP or

X

TOES

X

CE

OE

DQ6

T

OEHT

BP orTEC

T

- 18 -

OES

T

Timing Waveforms, continued

Boot Block Lockout Enable Timing Diagram

Six-word code for Boot Block
Lockout Feature Enable

Preliminary W49F201

Address A16-0

DQ15-0

CE

OE

WE

Chip Erase Timing Diagram

Address A16-0

5555

XX80

SW23

5555 2AAA

XXAA

SW3

5555

2AAA

XXAA

T

SW0

*Note: It is not allowed to assert read operation(CE# &OE# are both active) during the
command sequence. If read command is asserted during the command
sequence, then the device will return to read mode(abort write).

5555

XX55

WP

T

WPH

SW1

Six-word code for 5V-only software
chip erase

2AAA

5555 5555 2AAA

5555

XX55 XX40

SW5

SW4

5555

T

EC

DQ15-0

WE

CE

OE

XXAA

T

WP

SW0

XX55 XX80

T

WPH

SW1

XXAA

SW2

SW3

XX55

SW4

XX10

SW5

T

EC

Internal Erase starts

Publication Release Date: June 1999

- 19 - Revision A1

Timing Waveforms, continued

Sector Erase Timing Diagram

Six-word code for 5V-only software
Main Memory Erase

Preliminary W49F201

Address A16-0

DQ15-0

CE

OE

WE

Reset Timing Diagram

5555 2AAA

XXAA

TWP

T

WPH

SW0

*Note: It is not allowed to assert read operation(CE# &OE# are both active) during the
command sequence. If read command is asserted during the 4-word command
sequence, then the device will return to read mode(abort write).

SA = Sector Address

5555 5555 2AAA SA

XX55 XX80

SW1

SW2

XXAA

SW3

XX55

SW4

XX30

SW5

TEC

Internal Erase starts

CE

OE

RESET

T

RH

T

RP

- 20 -

ORDERING INFORMATION

Preliminary W49F201

PART NO. ACCESS

TIME

(nS)

W49F201S-45 45 50 200 (CMOS) 44-pin SOP 1K
W49F201S-55 55 50 200 (CMOS) 44-pin SOP 1K
W49F201T-45 45 50 200 (CMOS)
W49F201T-55 55 50 200 (CMOS)
W49F201S-45B 45 50 200 (CMOS) 44-pin SOP 10K
W49F201S-55B 55 50 200 (CMOS) 44-pin SOP 10K
W49F201T-45B 45 50 200 (CMOS)
W49F201T-55B 55 50 200 (CMOS)

Notes:

1. Winbond reserves the right to make changes to its products without prior notice.

2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in
applications where personal injury might occur as a consequence of product failure.

POWER

SUPPLY

CURRENT

MAX.

(mA)

STANDBY

VDD

CURRENT

MAX.

(µA)

PACKAGE CYCLE

48-pin TSOP (12 mm × 20 mm)
48-pin TSOP (12 mm × 20 mm)

48-pin TSOP (12 mm × 20 mm)
48-pin TSOP (12 mm × 20 mm)

1K
1K

10K
10K

Publication Release Date: June 1999

- 21 - Revision A1

PACKAGE DIMENSIONS
48-pin TSOP (12 mm × 20 mm)

Preliminary W49F201

1

θ

L

44-pin SOP

1

Y

SEATING PLANE

48

e

E

D
H

D

L1

A2

A1

2344

E

22

b

c

A

Y

L

L1

H

E

c

θ

D

A2

A

e

b

A1

Symbol

A
A1
A2
D
H
E
b

c
e

L
L1
Y

θ

Symbol

Dimension in mm

MIN.

NOM.

MAX.

0.05

0.95

18.3

19.8

D

11.9

0.17

0.10

0.50

0

MIN. NOM. MAX. MAX.NOM.

A

0.10

A1

2.26

A2

b

0.36 0.500.41

0.10 0.210.15

c

28.07

D

13.10

E

15.80

H

E

e

1.12 1.421.27

L

0.60 1.000.80

L1

Y

θ

1.20

1.051.00

18.4 18.5

20.0 20.2

12.1

12.0

0.27

0.22

0.21

0.50

0.60

0.70

0.80

0.10
5

Dimension in mm

3.00

2.82

28.32

28.19

13.30

13.50

16.00

16.20

1.35

0

0.10
7

Dimension in Inches

NOM.

MIN.

0.002

0.037

0.720

0.780 0.787 0.795

0.468

0.007

0.004

0.020

0

MAX.

0.047

0.041

0.039

0.724 0.728

0.476

0.472

0.009

0.011

0.008

0.020

0.024

0.028

0.031

0.004
5

Dimension in Inches

MIN.

0.004

0.089

0.016

0.014 0.020

0.004 0.0080.006

1.105 1.1151.110

0.516

0.524

0.622

0.044 0.0560.050

0.024 0.0400.032

0.053

0

0.118

0.111

0.531

0.6380.630

0.004
7

- 22 -

Preliminary W49F201

VERSION HISTORY

VERSION DATE PAGE DESCRIPTION

A1 Jun. 1999 - Renamed from W29F201C

Headquarters

No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: [phone]
FAX: [phone]
http://www.winbond.com.tw/
Voice & Fax-on-demand: 886-2-27197006

Winbond Electronics (H.K.) Ltd.

Rm. 803, World Trade Square, Tower II,
123 Hoi Bun Rd., Kwun Tong,
Kowloon, Hong Kong
TEL: [phone]
FAX: [phone]

Taipei Office

11F, No. 115, Sec. 3, Min-Sheng East Rd.,
Taipei, Taiwan
TEL: [phone]
FAX: [phone]

Note: All data and specifications are subject to change without notice.

Winbond Electronics North America Corp.
Winbond Memory Lab.
Winbond Microelectronics Corp.
Winbond Systems Lab.

2727 N. First Street, San Jose,
CA 95134, U.S.A.
TEL: [phone]

FAX: [phone]

Publication Release Date: June 1999

- 23 - Revision A1