Datasheet W48S87-72H Datasheet (Cypress)

Desktop/Notebook Frequency Generator

W48S87-72

Cypress Semiconductor Corporation

• 3901 North First Street • San Jose • CA 95134 • 408-943-2600
August 4, 2000 rev. *A

Features

• Maximized EMI suppression usi ng Cypress’s Spread
Spectrum technology

• ±0. 5 % Spread S pectru m cl o ck i n g

• Equivalent to the W 48S67-72 wit h Spread Spect rum f or
Tilamook, MMO, and Deschutes processors

• Generates system clocks for CPU , I OAPIC, SDRAM,
PCI, USB plus 14.318-MHz (REF0:1)

• Serial data inte rface (SDA T A, SCLOCK inputs ) provides
additional CPU/PCI clock fr equency selections, individ­ual output clock disabling and other functions

• MODE input pin selects optional power management
input control pins (reconfigures pins 26 and 27)

• T wo fixed outputs separately selectabl e as 24-MHz or
48-MHz (default = 48-MHz)

•V

DDQ3

= 3.3V±5%, V

DDQ2

= 2.5V±5%

• Uses exte rnal 14.318-MHz crystal

• Available in 48-pin SSOP (300 mils)

•

10Ω CPU output impedance

Note:

1. Additional frequency selections provided by serial data interface; refer to

Tabl e 5

on page 8.

T able 1. Pin Selectable Frequency

[1]

60/66_SEL

CPU, SDRAM
Clocks (MHz)

PCI Clocks

(MHz)

06030
1 66.8 33.4

Block Diagram

Pin Configuration

VDDQ3
REF0

VDDQ2
IOAPIC

CPU0
CPU1
CPU2
CPU3

SDRAM0
SDRAM1
SDRAM2
SDRAM3
SDRAM4
SDRAM5
SDRAM6
SDRAM7

PCI_F
PCI0

XTAL

PLL Ref Freq

PLL 1

60/66_SEL

MODE

X2

X1

REF1

VDDQ3

Stop

Output

Control

Stop

Output

Control

PCI1

PWR_DWN#

Power
Down
Control

PCI2
PCI3
PCI4
PCI5

48/24MHZ
48/24MHZ

PLL2

÷2

OSC

I/O
Control

VDDQ2

CPU_STOP#

REF1
REF0

GND

X1
X2

MODE

VDDQ3

PCI_F

PCI0
GND
PCI1
PCI2
PCI3
PCI4

VDDQ3

PCI5
GND

60/66_SEL

SDATA

SCLOCK

VDDQ3
48/24MHZ
48/24MHZ

GND

W48S87-72

VDDQ3
CPU2.5#
VDDQ2
IOAPIC
PWR_DWN#
GND
CPU0
CPU1
VDDQ2
CPU2
CPU3
GND
SDRAM0
SDRAM1
VDDQ3
SDRAM2
SDRAM3
GND
SDRAM4
SDRAM5
VDDQ3
SDRAM6/CPU_STOP#
SDRAM7/PCI_STOP#
VDDQ3

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

W48S87-72

2

Pin Definitions

Pin Name

Pin
No.

Pin

Type Pin Description

CPU0:3 42, 41, 39, 38O

CPU Outputs 0 through 3:

These four CPU outp uts are controlled by the
CPU_STOP# co ntrol pin. Out put volt age swi ng is controll ed by vol tage appli ed
to VDDQ2.

PCI0:5 9, 11, 12,

13, 14, 16

O

PCI Bus Outputs 0 through 5:

These six PCI outputs are controlled by the
PCI_STO P# control pin. Output voltage swing is controlled by voltage applied
to VDDQ3.

PCI_F 8 O

Free Running PCI Output:

Unlike PCI0:5 out puts, t his output is not controll ed
by the PCI_STOP# control pin. Output voltage swing is controlled b y voltage
applied to VDDQ3.

SDRAM0:5 36, 35, 33,

32, 30, 29

O

SDRAM Clock Outputs 0 through 5:

These six SDRAM clock output s run
synchronous to the CPU clock outputs. Output voltage swing is controlled by
voltage applied to VDDQ3.

SDRAM6/
CPU_STOP#

27 I/O

SDRAM Clock Output 6 or CPU Clock Output Stop Control :

This pin has
dual functions, selectable by the MODE input pin. When MODE = 0, this pin
becomes the CPU_STOP# inpu t. When MODE = 1, thi s pin becomes SDRAM
clock output 6.

Regarding use as a CPU_STOP# input: When brought LOW, clock outputs
CPU0:3 are stopped LOW after completing a ful l cl ock cycle (2–3 CPU clock
latency). When brought HIGH, clock outputs CPU0:3 are st arted beginning with
a full clock cycle (2–3 CPU clock latenc y).

Regarding use as a SDRAM cloc k: Output voltag e swing is controlled b y voltage
applied to VDDQ3.

SDRAM7/
PCI_STOP#

26 I/O

SDRAM Clock Output 7 or PCI Clock Output Stop Control:

This pin has
dual functions, selectable by the MODE input pin. When MODE = 0, this pin
becomes the PCI_STOP# input. When MO DE = 1, this pin becomes SDRAM
clock output 7.

PCI_STO P# input: When br ought LOW , clock out puts PCI0:5 are st opped LOW
after completing a full clock cycl e. When brought HIGH, cloc k outputs PCI0:5
are started beginning with a full cloc k cycle . Clock latency provides one PCI_F
rising edge of PCI cloc k followi ng PCI_STOP# state change.

Regarding use as a SDRAM cloc k: Output voltag e swing is controlled b y voltage
applied to VDDQ3.

IOAPIC 45 O

I/O APIC Clock Output:

Provides 14.3 18-MHz fixed frequency. The output

voltage swing is controlled by VDDQ2.

48/24MHz 22, 23 O

48-MHz / 24-MHz O utpu t:

Fixed cloc k outputs that def ault to 48 MHz f ollo wing
device po w er-up. Either or both can be cha nged to 24 MH z through use of the
serial data interface (Byte 0, bits 2 and 3). Output voltage s wing is controlled
by voltage applied to VDDQ3

REF0:1 2, 1 O

Fixed 14.318- MHz Outputs 0 through 1:

Used for various system applica­tions. Output voltage swing is controlled by voltage applied to VDDQ3. REF0
is stronger than REF1 and should be used for driving ISA slo ts.

CPU_2.5# 47 I Set to logic 0 for V

DDQ2

= 2.5V (0 to 2.5V CPU output swing).

60/66_SEL 18 I

60- or 66-MHz Input Sel ection:

Selects power -up default CPU cloc k frequency
as shown in Table 1 on page 1 (also determines SDRAM and PCI clock fre­quency selecti ons). Can be used to change CPU clock frequen cy while de vice
is in operation if serial data port bits 0–2 of Byte 7 are logic 1 (defa ult power­up condition).

X1 4 I

Crystal Connection or External Reference Frequency Input:

This pin has
dual functions. It can be used as an ext ernal 14. 318-MHz crystal connection
or as an external reference frequency input.

X2 5 I

Crystal Connect ion:

An input conn ect ion f or an e xt ernal 14. 318-M Hz crystal .

If using an e xternal reference, this pin must be left unconnec ted.

W48S87-72

3

PWR_DWN# 44 I

Power-Down Con tro l:

When this input is LOW, the device goes into a low­power standby condition. All outputs are activel y held LOW while in power ­down. CPU, SDRAM, and PCI clock out puts are stopped LOW after completing
a full clock cycle (2–4 CPU clock cycle l atency). When brought HIGH, CPU,
SDRAM, and PCI out puts start with a full clock cycle at full oper ating f requency
(3 ms maximum latency).

MODE 6 I

Mode Control:

This input selects the function of dev ice pin 26
(SDRAM7/PCI_ST OP#) and pin 27 (SDRAM6/CPU_ST OP#). Refer to des crip­tion fo r those pins.

SDATA 19 I/O

Serial Data Input:

Data input for Serial Data Interface. Refer to Serial Data

Interface section that follows.

SCLOCK 20 I

Serial Clock Input:

Clock input for Serial Data Interface. Refer to Serial Data

Interface section that follows.

VDDQ3 7, 15, 21, 25

28, 34, 48

P

Po wer Connectio n:

Pow er supply f or PCI0:5, REF0:1, and 48/24MHz output

buffers. Connected to 3.3V supply.

VDDQ2 46, 40 P

Po wer Connection:

Power supply for IOAPIC0, CPU0:3 output buffer. Con-

nected to 2.5V supply.

GND 3 , 1 0 , 17,

24, 31, 37,

43

G

Ground Connection :

Connect all ground pin s to the comm on system gr ound

plane.

Pin Definitions

(continued)

Pin Name

Pin
No.

Pin

Type Pin Description

W48S87-72

4

Spread Sp ectrum Ge n er ator

The device generates a clock that is frequency modulated in
order to increase the bandwidth that it occu pies. By increas ing
the bandwidth of the fundamental and its harmonics, the am­plitudes of the radiated electromagnetic emissions are re­duced. This effect is depicted in Figure 1.

As depicted in Figure 1, a harmonic of a modulated clock has
a much lower amplitude than that of an unmodulated signal.
The reduction in am plitude is dependen t on the harmonic num­ber and the frequency deviation or spread. The equation for
the reductio n is

dB = 6.5 + 9*log

10

(P) + 9*log10(F)

Where P is the percent age of de v iati on and F is the freq uency
in MHz where the reduction is measured.

The output clock is modulated with a waveform depicted in
Figure 2. This waveform, as discussed in “Spread Spectrum
Clock Gener ation f or the Redu ct ion of Radiat ed Emiss ions” by
Bush, Fessler, and Hardin produces the maximum reduction
in the amplitude of radiated electromagnetic emissions. The
deviati on select ed f or thi s chip is ±0. 5% of the center frequen ­cy. Figure 2 details the Cypress spreading pattern. Cypress
does offer options with more spread and greater EMI reduc­tion. Contact your local Sales representative for details on
these devices.

Spread Spectrum clocking is activated or deactivated by se­lecting the appropriate v al ues fo r bits 1–0 in data byte 0 of the
I

2

C data stream. Refer to Ta ble 4 for more details.

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Figure 1. Clock Harmonic wit h and without SSCG Modulation Frequency Domain Represent ation

Figure 2. Typical Modulation Profil e

MAX (+.0.5%)

MIN. (–0.5%)

10%

20%

30%

40%

50%

60%

70%

80%

90%

100%

10%

20%

30%

40%

50%

60%

70%

80%

90%

100%

FREQUENCY

W48S87-72

5

Serial Data Interface

The W48S87-72 features a two-pin, serial data interface that
can be used to configure internal register settings that control
particular device functions. Upon power-up, the W48S87-72
initiali zes wit h defau lt regist er setti ngs, t heref ore the use of this
serial data interface is optional. The serial interface is write­only (to the clock chip) and is the dedicated function of de vice
pins SDATA and SCLOCK. In motherboard applications,
SDATA and SCLOCK are typically driven by two logic outputs

of the chipset. Clock device register changes are normally
made upon system init iali zati on, if any are r equire d. The int er­face can also be us ed during system oper ation f or power man­agement functions. Ta ble 2 summarizes the control functions
of the serial data interface.

Operation

Data is written to the W48S87-72 in ten bytes of eight bits
each. Bytes are written in the ord er shown in Table 3 .

Table 2. Serial Data Interface Control Functions Summary

Control Function Description Common Application

Clock Output Disa ble Any indivi dual clock output(s) can be disabled. Dis-

abled outputs are actively held LOW.

Unused outputs are disabled to reduce EMI
and system power. Examples are clock out­puts to unused SDRAM DIMM socket or PCI
slot.

48-/24-MHz Cloc k Output
Frequency Selection

48-/24-MHz clock outputs can be set to 48 MHz or
24 MHz.

Provides flexibility in Super I/O and USB de­vice selectio n.

CPU Clock Frequency
Selection

Provides CPU/PCI fr equency selections be yond the
60- and 66.6-MHz selections that are provided by
the SEL60/66 input pin. F req uency is changed i n a
smooth and controlled fashion.

For alternate CPU devices, and power man­agement options. Smooth frequency transi­tion allows CPU fr equency ch ange un der nor-

mal system operati on.
Output Three-state Puts all clock outputs into a high-impedance state. Production PCB testing.
Test Mode All clock outputs toggle in relation with X1 input ,

internal PLL is bypassed. Refer to Table 4.

Production PCB testing.

(Reserved) Reserved fu nction for future device re vision or pro-

duction device testing.

No user application . Regist er bit must be wri t-

ten as 0.

Table 3. Byte Writing Sequence

Byte Sequence Byte Name Bit Sequence Byte Description

1 Slave Address 11010010 Commands the W48S87-72 to accept the bits in Data Bytes 0–7 for

internal register configuration. Since other devices may exist on the
same common serial data bus, it is necessary to hav e a specific slave
address for each potential receiver. The slave recei ver address for the
W48S87-72 is 11010010. Register setti ng will not be made if the Sl av e
Address is not correct ( or is for an alternate slave receiver).

2 Command

Code

Don’t Care Unused by the W48S87-72, the refore bit values are ignored (don’t c are).

This byte m ust be incl uded in the dat a write sequence to maintain pro per
byte allocati on. The Command Code Byt e is part of the standard serial
communication protocol and may be used when writing to another ad­dressed slave receiver on the seri al data bus.

3 Byte Count Don’t Care Unused by the W48S87-72, the refore bit values are ignored (don’t c are).

This byte m ust be incl uded in the dat a write sequence to maintain pro per
byte allocation. The Byte Coun t Byte is part of the standard serial com­munication protocol and may be used when writing to anot her ad­dressed slave receiver on the seri al data bus.

4 Data Byte 0 Refer to Table 4 The data bits in Data Bytes 0–7 set internal W48S87-72 registers that

control de vice operation. The data bits are only accepted when the Ad­dress Byte bit sequence is 11010010, as noted abov e. For descrip ti on
of bit control functions, ref er t o Ta ble 4 , Data Byte Serial Configuration
Map.

5 Data Byte 1
6 Data Byte 2
7 Data Byte 3
8 Data Byte 4

9 Data Byte 5
10 Data Byte 6
11 Data Byte 7

W48S87-72

6

Writing Data Bytes

Each bit in the data bytes control a particular device function
excep t for the “reserved” bits which must be written as a logic

0. Bits are written MSB (most significant bit) first, which is bit

7. Ta bl e 4 gives the bit formats for registers located in Data
Bytes 0–7.

Table 5 details additional frequency selections that are avail­able through t he seri al dat a interface .

Table 6 details the select functions for Byte 0, bits 1 and 0.

Table 4. Data Bytes 0–7 Serial Configuration Map

Bit(s)

Affected Pin

Control Function

Bit Control

DefaultPin No. Pin Name 0 1

Data Byte 0

7-- --(Reserved) -- -- 0
6 -- -- (Reserved) Refer to Table 5 0
5 -- -- SEL_4 Refer to Table 5 0
4 -- -- SEL_3 Refer to Table 5 0
3 23 48/24MHZ 48-/24-MHz Clock Output Frequency Selection 24 MHz 48 MHz 0
2 22 48/24MHZ 48-/24-MHz Clock Output Frequency Selection 24 MHz 48 MHz 0

1–0 -- -- Bit 1 Bit 0 Function (See Table 6 for function details)

0 0 Normal Operation
0 1 Test Mode
1 0 Spread Spec trum On
1 1 All Outputs Three-stated

00

Data Byte 1

7 23 48/24MHZ Cl ock Output Disable Low Active 1
6 22 48/24MHZ Cl ock Output Disable Low Active 1
5-- --(Reserved) -- -- 0
4-- --(Reserved) -- -- 0
3 38 CPU3 Clo ck O utput Disable L ow Active 1
2 39 CPU2 Clo ck O utput Disable L ow Active 1
1 41 CPU1 Clo ck O utput Disable L ow Active 1
0 42 CPU0 Clo ck O utput Disable L ow Active 1

Data Byte 2

7-- --(Reserved) -- -- 0
6 8 PCI_F Clock Output Dis able L ow Active 1
5 16 PCI5 Clo ck O u t p ut Disable Low Active 1
4 14 PCI4 Clo ck O u t p ut Disable Low Active 1
3 13 PCI3 Clo ck O u t p ut Disable Low Active 1
2 12 PCI2 Clo ck O u t p ut Disable Low Active 1
1 11 PCI1 Clo ck O u t p ut Disable Low Active 1
0 9 PCI0 Clock Output Disable Low Active 1

Data Byte 3

7 26 SDRAM7 Clock Output Disable Low Active 1
6 27 SDRAM6 Clock Output Disable Low Active 1
5 29 SDRAM5 Clock Output Disable Low Active 1
4 30 SDRAM4 Clock Output Disable Low Active 1
3 32 SDRAM3 Clock Output Disable Low Active 1
2 33 SDRAM2 Clock Output Disable Low Active 1
1 35 SDRAM1 Clock Output Disable Low Active 1
0 36 SDRAM0 Clock Output Disable Low Active 1

W48S87-72

7

Data Byte 4

7-- --(Reserved) -- -- 0
6-- --(Reserved) -- -- 0
5-- --(Reserved) -- -- 0
4-- --(Reserved) -- -- 0
3-- --(Reserved) -- -- 0
2-- --(Reserved) -- -- 0
1-- --(Reserved) -- -- 0
0-- --(Reserved) -- -- 0

Data Byte 5

7-- --(Reserved) -- -- 0
6-- --(Reserved) -- -- 0
5-- --(Reserved) -- -- 0
4 45 IOAPIC Clock Ou tput Disable Low Active 1
3-- --(Reserved) -- -- 0
2-- --(Reserved) -- -- 0
1 1 REF1 Clock Output Disable Low Active 1
0 2 REF0 Clock Output Disable Low Active 1

Data Byte 6

7-- --(Reserved) -- -- 0
6-- --(Reserved) -- -- 0
5-- --(Reserved) -- -- 0
4-- --(Reserved) -- -- 0
3-- --(Reserved) -- -- 0
2-- --(Reserved) -- -- 0
1-- --(Reserved) -- -- 0
0-- --(Reserved) -- -- 0

Data Byte 7

7-- --(Reserved) -- -- 0
6-- --(Reserved) -- -- 0
5-- --(Reserved) -- -- 0
4-- --(Reserved) -- -- 0
3-- --(Reserved) -- -- 0
2 -- -- SEL_2 Refer to Table 5 1
1 -- -- SEL_1 Refer to Table 5 1
0 -- -- SEL_0 Refer to Table 5 1

Table 4. Data Bytes 0–7 Serial Configuration Map

(continued)

Bit(s)

Affected Pin

Control Function

Bit Control

DefaultPin No. Pin Name 0 1

W48S87-72

8

Notes:

2. CPU, SDRAM, and PCI frequency selections are listed in

Table 1

and

Table 5

.

3. In Test Mode, the 48-/24-MHz clock outputs are:

- X1/2 if 48-MHz is selected.

- X1/4 if 24-MHz is selected.

Table 5. Additional Frequency Selections through Serial Data In terface Data Bytes

Date Byte 0

60/66_SEL

(Pin 18)

Date Byte 7

CPU0:3

SDRAM0:7

PCI_F

PCI0:5

Spread

Spectrum%

Bit 5

SEL_4

Bit 4

SEL_3

Bit 2

SEL_2

BIT 1

SEL_1

BIT 0

SEL_0

00X00075.0CPU/2±0.5
0 0 X 0 0 1 75.0 32 ±0.5
0 0 X 0 1 0 83.31 32 ±0.5
0 0 X 0 1 1 33.41 CPU/2 ±0.5
0 0 X 1 0 0 50.11 CPU/2 ±0.5
0 0 X 1 0 1 68.52 CPU/2 ±0.5
0 0 X 1 1 0 60.0 CPU/2 ±0.5
0 0 0 1 1 1 60.0 CPU/2 ±0.5
0 0 1 1 1 1 66.82 CPU/2 ±0.5
0 1 0 X X X 60.0 CPU/2 ±0.5
0 1 1 X X X 66.6 CPU/2 –0.5
1 0 0 X X X 60.0 CPU/2 ±0.5
1 0 1 X X X 66.6 CPU/ 2 –0.5
1 1 0 X X X 60.0 CPU/2 ±0.5
1 1 1 X X X 66.6 CPU/2 –0.5

Table 6. Select Function for Data Byte 0, Bits 0:1

Function

Input Conditions Output Conditions

Data Byte 0

CPU0:3,

SRAM0:7

PCI_F,
PCI0:5 REF0:2, IOAPIC 48/24MHZBit 1 Bit 0

Normal Operation 0 0 Note 2 Note 2 14.318 MHz 48 or 24 MHz
Test Mode 0 1 X1/2 X1/4 X1 Note 3
Spread Spectrum On 1 0 Note 2 Note 2 14.318 MHz 48 or 24 MHz
Three-state 1 1 Hi-Z Hi-Z Hi-Z Hi-Z

W48S87-72

9

How To Use the Serial Data Interface

Electrical Requirements

Figure 3 illust rat es el ectrical ch aract eristi cs for the serial i nter­face bus used with the W48S87-72. Devices send data over
the bus with an open drain logi c output that can (a) pull the b us
line LO W, or (b) let the b us d ef ault t o log ic 1. The p ull- up r esis­tors on the bus (both clock and data lines) establish a default
logic 1. All bus devices generally have logic inputs to receive
data.

Although the W48S87-72 is a receive-only device (no data
write-back capabil ity), it does transmit an “acknowledge” data
pulse after each byte is received. Thus, the SDATA line can
both transmit and receive data.

The pull-up resistor should be sized to meet the rise and fall
times specif ied i n A C p aramete rs , ta king i nto con si derat ion to ­tal bus line capacitance.

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Figure 3. Serial Interface Bus Electrical Characteristics

W48S87-72

10

Sign aling R equirements

As shown in Fi gure 4, v alid dat a bits are def ined as st able logic
0 or 1 condition on the data line during a clock HIGH (logic 1)
pulse. A trans iti oning dat a line during a cl oc k HIGH pulse ma y
be interpreted as a start or stop pulse (it will be interpreted as
a start or stop pulse if the start/stop timing parameters are
met).

A write sequence is i nitiat ed b y a “start bit” as sho wn i n Figure

5. A “stop bit” signifies that a transmission has ended.
As stated p re vio usly, the W48S87-72 s ends an “acknowledge”

pulse after receiving eight data bits in each byte as shown in
Figure 6.

Sending Data to the W48S87-72

The device accepts data once it has detected a valid start bit
and address byte sequence. Device functionality is changed
upon the receipt of each dat a bit (registe rs are not doub le buff ­ered). Pa rtial transmiss ion is allo wed meaning that a transmis ­sion can be truncated as soon as the desired data bits are
transmitted ( remaining r egister s will be unmodified ). Transmis­sion is truncated with either a stop bit or new start bit (restart
condition).

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W48S87-72

11

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W48S87-72

12

Absolute Maximum Ratings

Stresses greater than those listed in this table may cause per­manent damage to the de vice . These represent a stress ratin g
only. Operation of the device at these or any other conditions

above those specified in the operating secti ons of this specifi­cation is not implied. Maximum conditions for extended peri­ods may affect reliability.

.

Parameter Description Rating Unit

V

DD

, V

IN

Voltage on any pin with respect to GND –0.5 to +7 .0 V

T

STG

Storage Temperature –65 to +150 °C

T

A

Operating Temperature 0 to +70 °C

T

B

Ambient Temperature under Bias –55 to +125 °C

ESD

PROT

Input ESD Protection 2 (min.) kV

DC Electr i cal C h ar acteristics:

TA = 0°C to +70°C, V

DDQ3

= 3.3V±5% (3.135–3.465V) f

XTL

= 14.31818 MHz, V

DDQ2

= 2.5±5%

Parameter Description Te st Condi tion Min. Typ. Max. Unit

Supply Current

I

DDQ3

Supply Current (3.3V) CPUCLK =66.8 MHz

Outputs Loaded

[4]

120 150 200 mA

I

DDQ2

Supply Current (2.5V) CPUCLK =66.8 MHz

Outputs Loaded

[4]

50 mA

Logic Inputs

V

IL

Input Low Voltage 0.8 V

V

IH

Input High Voltage 2.0 V

I

IL

Input Low Current

[5]

10 µA

I

IH

Input High Current

[5]

10 µA

Clock Outputs

V

OL

Output Low Voltage I

OL

= 1 mA 50 mV

V

OH

Output High Voltage IOH = –1 mA 3.1 V

V

OH

Output High Voltage (CPU, IOAPIC) IOH = –1 mA 2.2 V

I

OL

Output Low Current CPU0:3 VOL = 1.25V 155 mA

SDRAM0:7 V

OL

= 1.5V 100 mA

PCI_F, PCI0:5 V

OL

= 1.5V 95 mA

IOAPIC V

OL

= 1.25V 85 mA

REF0 V

OL

= 1.5V 75 mA

REF1 V

OL

= 1.5V 60 mA

48/24MHZ V

OL

= 1.5V 60 mA

I

OH

Output High Current CPU0:3 VOL = 1.25V 125 mA

SDRAM0:7 V

OL

= 1.5V 95 mA

PCI_F, PCI0:5 V

OL

= 1.5V 100 mA

IOAPIC V

OL

= 1.25V 80 mA

REF0 V

OL

= 1.5V 80 mA

REF1 V

OL

= 1.5V 65 mA

48/24MHZ V

OL

= 1.5V 60 mA

Notes:

4. All clock outputs loaded with maximum lump capacitance test load specified in AC Electrical Characteristics section.

5. W48S87-72 logic inputs have internal pull-up devices. (Not CMOS level.)

W48S87-72

13

Crystal Oscillator

V

TH

X1 Input Threshold Voltage

[6]

VDD = 3.3V 1.65 V

C

LOAD

Load Capacitance, Imposed on
External Crystal

[7]

14 pF

C

IN,X1

X1 Input Capacitance

[8]

Pin X2 unconnected 28 pF

Pin Capacitance/Induct ance

C

IN

Input Pin Capacitance Except X1 and X2 5 pF

C

OUT

Output Pin Capacitance 6 pF

L

IN

Input Pin Inductance 7nH

Serial Input Port

V

IL

Input Low Voltage VDD = 3.3V 0.4 0.3V

DD

V

V

IH

Input High Voltage VDD = 3.3V 0.7V

DD

2.4 V

I

IL

Input Low Current No internal pul l- up/down

on SCLOCK

10 10 µA

I

IH

Input High Current No i nternal pull-up/down

on SCLOCK

10 10 µA

I

OL

Sink Current into SDATA or SCLOCK,
Open Drain N-Channel Device On

IOL = 0.3V

DD

51015mA

C

IN

Input Capacitance of SDAT A and
SCLOCK

510pF

C

SDATA

Total Capacitance of SDATA Bus 400 pF

C

SCLOCK

Total Capacitance of SCLOCK Bus 400 pF

Notes:

6. X1 input threshold voltage (typical) is V

DDQ3

/2.

7. The W48S87-72 contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. Total load placed on crystal
is 14 pF; this includes typical stray capacitance of short PCB traces to crystal.

8. X1 input capacitance is applicable when driving X1 with an external clock source (X2 is left unconnected).

DC Electr i cal C h ar acteristics:

(continued)

T

A

= 0°C to +70°C, V

DDQ3

= 3.3V±5% (3.135–3.465V) f

XTL

= 14.31818 MHz, V

DDQ2

= 2.5±5%

Parameter Description Te st Condi tion Min. Typ. Max. Unit

W48S87-72

14

AC Electrical Characteristics

TA = 0°C to +70°C, VDD = V

DDQ3

= 3.3V±5% (3.135–3.465V) f

XTL

= 14.31818 MHz, V

DDQ2

= 2.5±5%

AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the
clock output.

CPU Clock Outputs, CPU0:3 (Lump Capaci tance Test Load = 20 pF)

Parameter Description Test Condition/Comments

CPU = 66.8 MHz CPU = 60 MHz

UnitMin. Typ. Max. Min. Typ. Max.

t

P

Period Measured on rising edge at 1.5V 15 16.7 ns

f Frequency, Actual Determined by PLL divider ratio 6 6.8 59.876 MH

z

t

H

High Time Duration of clock cycle above 2.4V 5.2 6 ns

t

L

Low Time Duration of clock cycle below 0. 4V 5 5.8 ns

t

R

Output Rise Edge Rate Measured from 0.4V to 2.4V 1 4 1 4 V/ns

t

F

Output Fall Edge Rate Measured from 2.4V to 0.4V 1 4 1 4 V/ns

t

D

Duty Cycle Measured on rising and falli ng edge at

1.25V

45 52 55 45 52 55 %

t

JC

Jitter, Cycle-to-Cy cle Measured on rising edge at 1.25V.

Maximum difference of cycle time be­tween two adjacent cycles.

250 250 ps

t

SK

Output Skew Measured on rising edge at 1.25V 250 250 ps

f

ST

Frequen cy Stabilization
from Power-up (cold
start)

Assumes full suppl y voltage reached
within 1 ms from power- up. Short cy­cles exist prior to frequency stabil iza­tion.

33ms

Z

o

AC Output Impedance Averag e v alue during switching trans i-

tion. Used for determining series ter­mination value.

10 10 Ω

SDRAM Clock Outputs, SDRAM0:7 (Lump Capacitance Test Load = 30 pF)

Parameter Description Test Condition/Comments

CPU = 66.8 MHz CPU = 60 MHz

UnitMin. Typ. Max. Min. Typ. Max.

t

P

Period Measured on rising edge at 1.5V 15 16.7 ns
f Frequency, Actual Determi ned by PLL divider ratio 66.8 59.876 MHz
t

R

Output Rise Edge Rate Measured from 0.4V to 2.4V 1 4 1 4 V/ns
t

F

Output Fall Edge Rate Measured from 2.4V to 0.4V 1 4 1 4 V/ns
t

D

Duty Cycle Measured on rising and f alling edge at

1.5V

45 50 55 45 50 55 %

t

JC

Jitter, Cycle-to-Cycle Measured on rising edge at 1.5V. Max-

imum difference of cycle time between
two adjacent cycles.

250 250 ps

t

SK

Output Skew Measured on rising edge at 1.5V 100 100 ps
t

SK

CPU to SDRAM Clock

Skew

Covers all CPU/SDRAM outputs. Mea­sured on rising edge at 1.5V.

500 500 ps

f

ST

Frequency Stabiliza-

tion from Power-up

(cold start)

Assumes full supply voltage reached
within 1 ms from pow er-up. Short cycles
exist prior to fr equency stabilizati on.

33ms

Z

o

AC Output Imped ance Average value during switching transi-

tion. Used for determinin g series termi­nation value.

16 16 Ω

W48S87-72

15

PCI Clock Outputs, PCI0:5 (Lump Capacitance Test Load = 30 pF)

Parameter Description Test Condition/Comments

CPU = 66.8 MHz CPU = 60 MHz

UnitMin. Typ. Max. Min. Typ. Max.

t

P

Period Measured on rising edge at 1.5V 30 33.3 ns
f F requency, Actual Determined by PLL di vider ratio 33.4 29.938 MHz
t

H

High Time Duration of clock cycle above 2.4 V 12 13.3 ns
t

L

Low Time Duration of clock cycle below 0.4V 12 13.3 ns
t

R

Output Rise Edge Rate 1 4 1 4 V/ns
t

F

Out p ut Fall Edge R a t e 1 4 1 4 V/ns
t

D

Duty Cycle Measured on rising and falling edge at

1.5V

45 51 55 45 51 55 %

t

JC

Jitter, Cycle-to-Cycle Measured on rising edge at 1.5V. Maxi-

mum difference of cycle time between
two adjacent cycles.

250 250 ps

t

SK

Output Skew M easured on rising edge at 1.5V 250 250 ps
t

O

CPU to PCI Clock

Skew

Covers al l CPU/ PCI outpu ts. M easured
on rising edge at 1.5V. CPU leads PCI
output.

1414ns

f

ST

Frequency Stabiliza-

tion from Power-up

(cold start)

Assumes full suppl y voltage reached
within 1 ms from po wer-up . Short cycles
exist prior to frequency stabili zation.

33ms

Z

o

AC Output Impedance Average value during switching transi-

tion. Used for determining series termi­nation val ue.

30 30 Ω

I/O APIC Clock Output (Lump Capaci tance Test Load = 20 pF)

Parameter Description Test Condition/Comment s

CPU = 60/66.8 MHz

UnitMin. Typ. Max.

f Frequency, Actual Frequency generated by crystal oscillator 14.31818 MHz
t

R

Output Rise Edge Rate 1 4 V/n s

t

F

Out p ut Fall Edge R a t e 1 4 V/ns

t

D

Duty Cycle Measured on rising and falling edge at 1.25V 45 52.5 55 %

f

ST

Frequency Stabilization
from Power-up (cold start)

Assumes full supply voltage reached within
1 ms from power-up . Sh ort cycles e xist prior to
frequency stabi li zation.

1.5 ms

Z

o

AC Output Imped ance Aver age value during s w it ching transition.

Used for determining series t erminat ion value.

15 Ω

W48S87-72

16

REF0 Clock Output (Lump Capaci tance Test Load = 45 pF)

Parameter Description Test Condition/Comments

CPU = 60/66.8 MHz

UnitMin. Typ. Max.

f Frequency, Actual Frequen cy generated by crystal oscillator 14.31818 MHz
t

R

Output Rise Edge Rate Measured from 0.4V to 2.4V 1 4 V/ns

t

F

Output Fall Edge Rate Measured from 2.4V to 0.4V 1 4 V/ns

t

D

Duty Cycle Measured on rising and falling edge at 1.5V 45 50 55 %

f

ST

Frequency Stabilization
from Power-up (cold start)

Assumes full supply voltage reached withi n
1 ms from power-up . Short cycles ex ist prior to
frequency stabilization.

1.5 ms

Z

o

AC Output Impedance Average value during switching transition.

Used for determining series termination value.

16 Ω

REF1 Clock Output (Lump Capaci tance Test Load = 20 pF)

Parameter Description Test Condition/Comments

CPU = 60/66.8 MHz

UnitMin. Typ. Max.

f Frequency, Actual Frequency generated by crystal oscillator 14.31818 M Hz
t

R

Output Rise Edge Rate 0.5 2 V/ns

t

F

Out p ut Fall Edge R a t e 0.5 2 V/n s

t

D

Duty Cycle Measured on rising and falling edge at 1.5V 45 55 %

f

ST

Frequency Stabilization
from Power-up (cold start)

Assumes full supply voltage reached within
1 ms from power- up. Short cycles e xist pri or to
frequency stabi li zation.

1.5 ms

Z

o

AC Output Imped ance Aver age value during s w it ching transition.

Used for dete rmining series termination value .

40 Ω

48/24MHZ Clock Output s (Lump Capacitance Test Load = 20 pF)

Parameter Description Test Condition/Comments

CPU = 60/66.8 MHz

UnitMin. Typ. Max.

f F requency, Actual Determined by PLL divider ratio

(see n/m below)

48.008/24.004 MHz

f

D

Deviatio n fro m 48 MHz (48.008 – 48)/48 +167 ppm
m/n PLL Ratio (14.31818 MHz x 57/17 = 48.008 MHz) 57/17
t

R

Output Rise Edge Rate 0.5 2 V/ns
t

F

Out p ut Fall Edge R a t e 0 . 5 2 V/ns
t

D

Duty Cycle Measured on rising and falli ng edge at 1.5V 45 50 55 %
f

ST

Frequency Stabilization

from Po wer-up (cold start)

Assumes full supply voltage reached withi n
1 ms from powe r-up. Short cycles ex ist prior to
frequency stabilization.

3ms

Z

o

AC Output Impedance Average value during switching transition.

Used for det ermining series termina tion va lue.

40 Ω

W48S87-72

17

Document #: 38-00855-*A

Serial Input Port

Parameter Description Test Condition Min. Typ. Max. Unit

f

SCLOCK

SCLOCK Frequency Normal Mode 0 100 kHz
t

STHD

Start Hold Time 4.0

µs

t

LOW

SCLOCK Low Time 4.7

µs

t

HIGH

SCLOCK High Time 4.0

µs

t

DSU

Data Set-up Time 250 ns
t

DHD

Data Hold Time (T ransmitter sho uld provide a 300-ns hold

time to ensu re proper timing at the receiv er .)

0ns

t

R

Rise Time, SD ATA and

SCLOCK

From 0.3VDD to 0.7V

DD

1000 ns

t

F

Fall Time, SDATA and

SCLOCK

From 0.7VDD to 0.3V

DD

300 ns

t

STSU

Stop Set-up Time 4.0

µs

t

SPF

Bus Free Time between

Stop and Start Condition

4.7

µs

t

SP

Allowable Noise Spike

Pulse Width

50

ns

Ordering Information

Ordering Code

Freq. Mask

Code

Package

Name

Pac kage Type

W48S87 72 H

X

48-pin SSOP (300 mils)
48-pin TSSOP

W48S87-72

18

Package Diagrams

48-Pin Small Shrink Outline Package (SSOP, 300 mils)

Summary of nominal dimensions in inches:
Body Width: 0.296

Lead Pitch: 0.025
Body Length: 0.625
Body Height: 0.102

W48S87-72

© Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it conv ey or imply any lice nse under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

Package Diagrams

(continued)

48-Pin Thin Shrink Small Outline P ackage (TSSOP)

8°0°

COMMON

DIMENSIONS

MIN. MAX.

C

O

N

E

T

D

4NOTE
VARI­ATIONS

SEE VARIA TIO NS

SEE VARIA TIO NS

L

CO

1

N

H

e

E

D

b1

b

A

A

O

L

Y

M
B

S

MAX.MIN.

NOM.

4°

NOM.

34389

2 OF 2

A

2

THIS TABLE IN MILLIMETERS

8/1

0.50 BSC

0.10

0.90

0.27

0.15

1.10

0.05

0.17

6.00 6.10 6.20

7.95

0.50 0.60

8.10 8.25

0.75

AA
AB

6

4
4

5

12.40 12.50 12. 60

13.90 14.00 14. 10

THIS TABLE IN INCHES

.555.551.547

.496.492.488

5

4

4

6

AB

AA

.030

.325.319

.024.020

.313

.244.240.236

.0433

.0197 BSC

2

A

NOM.

4°

NOM.

MIN. MAX.

S

B

M

Y

L

O

A
A

b

b1

D
E

e

H

N

1

OC

L

SEE VARIA TIO NS

SEE VARIA TIO NS

ATIONS

VARI-

NOTE 4

D

T

E

N

O

C

MAX.MIN.

DIMENSIONS

COMMON

0° 8°

.004.002 .006

.0354

8

0.250.12

0.500.37
56

48

NOM.MIN. MAX.

S

6
N

N

6

S

MAX.MIN. NOM.

48
56

02

A1

0.090 0.1600.127

C

C1

8

0.090 0.200

0.230.200.17

C1

C

.0067 .0078 .0090

.0078.0035

8

.0050 .0063.0035

8

.0067 .011

.0146 .0197
.0047 .0098

0.950.85

.0335 .0374

REV.DWG. N O.SIZE

SHEET

SCALE

TITLE

12

A

B

C

D

E

F

G

H

B

C

D

E

F

G

H

A

12

1110987654321

1110987654321

PACKAGE OUTLINE, 6.10mm (.240") BODY,

TSSOP, 0.50mm LEAD PITCH