Datasheet W42C31-06 Datasheet (Cypress)

W42C31-06

Spread Spectrum Frequency Timing Generator

Features

• Maximized EMI suppression usi ng Cypress’s Spread
Spec trum te chnol ogy

• Generates a spread spectrum 3X copy of the input

• Integrated loop filter components

• Operates with a 5V supply

• Low-power CMOS design

• Available in 8-pin SOIC (Small Outline Integrated
Circuit)

Overview

The W42C31-06 incorporates the latest advances in PLL
spread spectrum frequency synthesizer techniques. By fre­quency modulating the output with a low-frequency carrier,
EMI is greatly reduced. Use of this technology allows systems

Simplified Block Diagram

5.0V

X1

XTAL
Input

X2

W42C31-06

Spread Spectrum
Output

(EMI suppressed)

to pass increasingly difficult EMI testing without resorting to
costly shiel ding or redesign.

In a system, not on ly is EMI reduced i n the v ari ous cl oc k lin es,
but also in all signals which are synchronized to the clock.
Therefore, the benefits of using this technology increase with
the number of address and data lines in the system. The Sim­plified Block Diagram shows a simple implementation.

T able 1. Frequency Spread Selection

W42C31-06 Oscillator

Input

Frequency

(MHz)

0 14 to 20 14 to 20 3f
1 14 to 20 14 to 20 3f

XTAL Input

Frequency

(MHz)

Output

Frequency

(MHz)FS0

±0.75%

IN

±1.25%

IN

Pin Configuration

SOIC

X1
X2

GND

FS0

W42C31-06

1
2
3
4

8
7
6
5

SSON#
NC
VDD
CLKOUT

5.0V

Oscillator or Refer ence
Input

W42C31-06

Cypress Semiconductor Corporation

Spread Spectr um

(EMI suppressed)

Output

• 3901 North First Street • San Jose • CA 95134 • 408-943-2600
September 29, 1999, r ev. **

Pin Definitions

W42C31-06

Pin Name Pin No.

CLKOUT 5 O

T ype Pin Description

Output Modulated Fr equency

clock (multiplier of 3).

Pin

X1 1 I

Crystal Connection or External Reference Frequency Input:

functions. I t ma y e ither b e connec ted to an e xternal crystal, or to an ex ternal ref er ence

clock.
X2 2 I
SSON# 8 I

Crystal Connection:

Spread Spectrum (Active LOW):

modulating waveform off. This pin has an inte rnal pul l-down resistor.
FS0 4 I

Frequency Selection Bit 0:

characteristics. Refer to Table 1 . This pin has an internal pull -up resistor.
NC 7 NC
VDD 6 P
GND 3 G

No Connect:

This pin must be left unconnected.

Power Connection:

Ground Connection:

Functional Description

The W42C31-06 uses a p hase- loc k ed loop ( PLL) t o freq uency
modulate an input clock. The result is an output clock whose
frequency is slowly swept over a narrow band near the input
signal. The basic circuit topology is shown in Figure 1. An
on-chip crystal driver causes the crystal to oscillate at its fun­damental. The resulting reference signal is divided by Q and
fed to the phase det ector. A signal from the VCO is divided by
P and fed back to the phase detector also. The PLL will force
the frequency of the VCO output signal to change until the
divided output signal and the divided reference signal match
at the phas e detector input. The output frequenc y is th en equal
to the ratio of P/Q times the reference frequency. The unique
featur e of the Spread Spect rum Clock Generat or is t hat a mod­ulating waveform is superimposed at the input to the VCO.
This causes the VCO output to be slowly swept across a pre­determined frequen cy band.

Because the modulating frequency is typically 1000 times
slower than the fundamental clock, the spread spectrum pro­cess has litt le i m pact on system performance.

: Fre quenc y modul ated cop y of the un modul ate d input

This pin has dual

If usi ng an external reference , thi s pin mus t be l eft unc onnected .

Pulling this inp ut si gnal HIGH turns the internal

This pin selects the fre quency spreadi ng

Connected to 5V power supply.

This should be connect ed to the common ground plane.

Frequency Selection With SSFTG

In Spread Spectrum Frequency Timing Generati on, EMI re­duction depends on the shape, modulation percentage, and
frequency of the modulating waveform. While the shape and
frequency of the modulating waveform are fixed, the modula­tion percentage may be varied.

Using the frequency select bit (FS0), the spreading percent­age can be chosen (see Table 1).

A larger spreading per centage improves EMI reduction . How­ever, large spread percentages may either exceed system
maximum frequ ency ra tings or lo wer the a v erag e fr equency t o
a point where performance is affected. For these reasons,
spreading percentages between ±0.5% and ±2.5% are most
common.

The W42C31 feat ures t he abil ity to sel ect from v arious spread
spectrum characteristics. Selections specific to the
W42C31-06 are shown in Table 1. Other spreading character-
istics are available (see separate data sheets) or can be cre­ated w i th a custom mask.

XTAL

Crystal load
capacitors
as needed

X1

X2

Freq.

Q

V

DD

Phase

Detector

Feedback

Divider

P

Charge

Pump

GND

Σ

Modulating

Waveform

PLL

Figure 1. System Block Diagram

2

VCO

Post

DividersDivider

CLKOUT

Spread Spectrum Frequency Tim ing

SSFTG

Typi cal Cl oc k

5dB/div

Amplitude (dB)

Figure 2. Typic al Clo ck and SSFTG Comparison

Generation

The benefits of using Spread Spectrum Frequency Timing
Generation are depicted in Figure 2. An EMI emission profile
of a clock harmonic is shown.

Contrast the typical clock EMI wi th the Cypress Spread Spec­trum Frequency Timing Generation EMI. Notice the spike in
the typical clo c k. This sp ike can mak e system s f ail quas i-peak
EMI testing. The FCC and other regulatory agencies test for
peak emissions. With spread spectrum enab led, the peak en­ergy is much lower (at least 8 dB) because the energy is
spread out across a wider ban dwidth.

Modulating Waveform

The shape of the modul ating wa vef orm is critica l to EMI reduc­tion. The modulation scheme used to accomplish the maxi­mum reduction in EMI is shown in Figure 3. The period of the
modulation is shown as a percentage of the period length
along the X axis. The amount that the frequency is varied is
shown along the Y axis, also shown as a percentage of the
total frequency spread.

Cypress frequency selection tables express the modulation
percentage in two wa y s . The firs t method di spla y s the spr ead­ing frequency band as a percent of the programmed average
output frequency, symmetric about the programmed average
frequency. This met hod is always shown using the expression
f

Center ± XMOD

The second approach is to specify the maximum operating
frequency and th e spreadi ng band as a percent age of thi s fre­quency. The output signal is swept from the lower edge of the
band to the maximum frequency. The expression for this ap­proach is f
Cypress has taken care to ensure that f
ceeded. This is important in applications where the clock
drives componen ts with tight maxi mu m clock sp eed spec ifi ca­tions.

% in the frequency spread selection table.

MAX – XMOD

%. Whenever this expression i s used,

will never be ex-

MAX

W42C31-06

SSON# Pin

An internal pull-down resistor defaults the chip into spread
spectrum mode. The SSO N# pin enables the spreading fea­ture when set LOW. When disabled (SSON# HIGH), the
W42C31-06 simply passes through the input clock. Upon go­ing LOW, the de vice t ak es 2 m s to re-t rac k t he spr eadi ng algo ­rithm.

100%

80%
60%
40%
20%

0%

–20%
–40%

Frequency Shift

–60%
–80%

–100%

10%

20%

30%

40%

50%

60%

70%

80%

90%

100%

Time

Figure 3. Modulation W aveform Profile

3

10%

20%

30%

40%

50%

60%

70%

80%

90%

100%

Absolute Maximum Ratings

W42C31-06

Stresses gre ater th an those li sted i n this tab le may cause per­manent damage to the de vice. These represent a stress ratin g
only. Operation of the device at these or any other conditions

above those specified in the operating sections of this specifi­cation is not implied. Maximum conditions for extended per i­ods may affect reliability.

Parameter Description Rating Unit

V

, V

DD

IN

T

STG

T

A

T

B

P

D

DC Electr i cal C h ar acteristics:

Voltage on any pin with respect to GND –0.5 to +7 .0 V
Storage Temperature –65 to +150 °C
Operating Temperature 0 to +70 °C
Ambient Temperature under Bias –55 to +125 °C
Power Dissipation 0.5 W

0°C < T

< 70°C, VDD = 5V ±10%

A

Parameter Description Test Condition Min Typ Max Unit

I

DD

t

ON

Supply Current 20 40 mA
Power Up Time First l o cke d c l o ck c yc l e after

5ms

Powe r Good
V
V
V
V
I
I
I
I
C
C

R
Z

IL
IH
OL

OH
IL
IH
OL
OH

I

L

P

OUT

Input Low Voltage 0.15V
Input High Voltage 0.7V

DD

DD

Output Low Voltage 0.4 V
Output High Voltage 2.5 V
Input Low Current Note 1 –100 µA
Input High Current Note 1 10 µA
Output Low Current @ 0.4V, VDD = 5V 24 mA
Output High Current @ 2.4V, VDD = 5V 24 mA
Input Capacit ance All pins except X1, X2 7 pF
Load Capacitance (as seen

Pins X1, X2

[2]

17 pF

by XTAL)
Input Pull-Up Resistor 500 kΩ
Clock Output Impedance 20 Ω

TA = 0°C to +70°C, VDD = 5V±10%

AC Electrical Characteristics:

Paramet er Description Tes t Condition Min Typ Max Unit

f

IN

f

OUT

t

R

t

F

t

OD

t

ID

t

JCYC

Input Frequency Input Clock 14 20 MHz
Output Frequency Spread Off 42 60 MHz
Output Rise Time VDD, 15-pF load 0.8–2.4 2 5 ns
Output Fall Time VDD, 15-pF load 2.4–0.8 2 5 ns
Output Duty Cycle 15-pF load 45 55 %
Input Duty Cycle 40 60 %
Jitter, Cycle- to - C yc le 250 300 ps
Harmonic Reduction 8 dB

Notes:

1. Input FS0 has a pull-up resistor; Input SSON# has a pull-down resistor.

2. Pins X1 and X2 each have a 34-pF capacitance. When used with a XTAL, the two capacitors combined load the crystal with 17 pF. If driving X1 with a

reference clock signal, the load capacitance will be 34 pF (typical).

V
V

4

W42C31-06

Application Information

Recommended Circuit Configuration

For optimum performance in system applications the power
supply decoupli ng scheme sho wn in Figure 4 should be used.

decoupling is impor tant to both reduce phase jitter and

V

DD

EMI radiation. The 0.1-µF decoupling capacitor should be
placed as close to the V
creased trace inductance will negate its decoupling capability.

C1
6 pF

C2
6 pF

Optional Guard Ring for
XTAL Oscil la tor Circu itr y

G

C1

pin as possible, otherwise the in-

DD

1

XTAL1

GND

2
3
4

5V System Supply

Figure 4. Recommended Circuit Configuration

W42C31-06

The 10-µF decoupling capacitor shown should be a tantalum
type. For further EMI protection, the V
made via a ferrite bead, as shown.

connection can be

DD

The 6-pF XTAL load capacitors can be used to raise the inte­grated 17-pF capacitance up to a total load of 20 pF on the
crystal.

Recommended Board Layout

Figure 5 shows a recommended 2-layer board layout.

8
7
6
5

V

DD

Output

R1

C3

µF

0.1

FB

C1, C2 =

C3 =

C4 =

FB Ferrite Bead

=

G

=

C4

µF Tantalum

10

XTAL load capacitors (optional; use
is not required for operation).
Typical value is 6 pF.

High frequency supply decoupling
capacitor (0.1-

Common supply low frequency
decoupling capacitor (10­recommended).

Match valu e to li ne imp e d an ceR1 =

Via To GND Plane

µF recommended).

µF tantalum

G

C2

XTAL1

C3

G

G

C4

Power Supply In put

(5V)

FB

G

Figure 5. Recommended Board Layout (2-Layer Board)

Ordering Information

Ordering Code

Code

W42C31 06 G 8-pin Plastic SOIC (150-mil )

Document #: 38-00800

Freq. Mask

Package

Name Package Type

5

G

R1

Clock Output

Package Diagram

W42C31-06

8-Pin Small Outline Integrated Circuit (SOIC, 150-mil)

© Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it con vey or imply any lice nse under patent or other rights. Cypress Semicondu ctor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.