Datasheet W29C020S-90B, W29C020S-90A, W29C020S-90, W29C020S-70B, W29C020S-70A Datasheet (Winbond Electronics)

W29C020

256K × 8 CMOS FLASH MEMORY

GENERAL DESCRIPTION

The W29C020 is a 2-megabit, 5-volt only CMOS flash memory organized as 256K × 8 bits. The
device can be written (erased and programmed) in-system with a standard 5V power supply. A 12-volt
VPP is not required. The unique cell architecture of the W29C020 results in fast write (erase/program)
operations with extremely low current consumption compared to other comparable 5-volt flash
memory products. The device can also be written (erased and programmed) by using standard
EPROM programmers.

FEATURES

• Single 5-volt write (erase and program)

operations

• Fast page-write operations

− 128 bytes per page

− Page write (erase/program) cycle: 10 mS

(max.)

− Effective byte-write (erase/program) cycle
time: 39 µS

− Optional software-protected data write

• Fast chip-erase operation: 50 mS

• Two 8 KB boot blocks with lockout

• Typical page write (erase/program) cycles:

100/1K/10K

• Read access time: 70/90/120 nS

• Ten-year data retention

• Software and hardware data protection

• Low power consumption

− Active current: 25 mA (typ.)

− Standby current: 20 µA (typ.)

• Automatic write (erase/program) timing with

internal VPP generation

• End of write (erase/program) detection

− Toggle bit

− Data polling

• Latched address and data

• All inputs and outputs directly TTL compatible

• JEDEC standard byte-wide pinouts

• Available packages: 32-pin 600 mil DIP, 450 mil

SOP, TSOP, and 32-pin PLCC

Publication Release Date: February 1998

- 1 - Revision A3

PIN CONFIGURATIONS BLOCK DIAGRAM

1

789

111213

14

16

V

DD

E

3

4

678

DQ1

DQ2

V

A13

DD

CE

OE

WE

W29C020

32-pin

DIP

A
16N

C

32-pin
PLCC

G

D

N

Q

D

3

32-pin
TSOP

32
31

WE

30

A17

29

A14

28

A13

27

A8

26

A9

25

A11

24

OE

23

A10

22

CE

21

DQ7

20

DQ6

19

DQ5

18

DQ4

17

DQ3

V

/

A

D

W

1

D

7

30313212

29

A14

28

A13

27

A8

26

A9

25

A11

24

OE

23

A10

22

CE

21

DQ7

20191817161514

D

D

D

Q

Q

Q

4

5

6

NC

2

A16

3

A15

4

A12

5

A7

6

A6

A5
A4
A3

10

A2
A1
A0

DQ0
DQ1

15

DQ2
GND

A

A

1

1

2

5

34

5

A7

6

A6

7

A5

8

A4

9

A3

10

A2

11

A1

12

A0

13

DQ0

D

D

Q

Q

1

2

A11

2

A9
A8

5

A14

A17

WE

9

NC

10

A16

11

A15

12

A12

13

A7

14

A6

15

A5

16 A3

A4

V

DD

V

SS

CE
OE

WE

A0

CONTROL

OUTPUT
BUFFER

8K Byte Boot Block (Optional)

DQ0

.
.

DQ7

.

CORE

ARRAY

8K Byte Boot Block (Optional)

A17

.

DECODER

.

PIN DESCRIPTION

SYMBOL PIN NAME

A0−A17

32

OE
A10

31
30

CE
DQ7

29

DQ6

28

DQ5

27

DQ4

26

DQ3

25

GND

24
23
22

DQ0

21
20

A0
A1

19

A2

18
17

DQ0−DQ7

VDD Power Supply

GND Ground

Address Inputs
Data Inputs/Outputs
Chip Enable
Output Enable
Write Enable

NC No Connection

- 2 -

W29C020

WE

FUNCTIONAL DESCRIPTION

Read Mode

The read operation of the W29C020 is controlled by CE and OE, both of which have to be low for
the host to obtain data from the outputs. CE is used for device selection. When CE is high, the chip
is de-selected and only standby power will be consumed. OE is the output control and is used to gate
data from the output pins. The data bus is in high impedance state when either CE or OE is high.
Refer to the read cycle timing waveforms for further details.

Page Write Mode

The W29C020 is written (erased/programmed) on a page basis. Every page contains 128 bytes of
data. If a byte of data within a page is to be changed, data for the entire page must be loaded into the
device. Any byte that is not loaded will be erased to "FF hex" during the write operation of the page.

The write operation is initiated by forcing CE and WE low and OE high. The write procedure
consists of two steps. Step 1 is the byte-load cycle, in which the host writes to the page buffer of the
device.

Step 2 is an internal write (erase/program) cycle, during which the data in the page buffers are
simultaneously written into the memory array for non-volatile storage.

During the byte-load cycle, the addresses are latched by the falling edge of either CE or WE,
whichever occurs last. The data are latched by the rising edge of either CE or

occurs first. If the host loads a second byte into the page buffer within a byte-load cycle time (TBLC) of
200 µS after the initial byte-load cycle, the W29C020 will stay in the page load cycle. Additional bytes
can then be loaded consecutively. The page load cycle will be terminated and the internal write
(erase/program) cycle will start if no additional byte is loaded into the page buffer A7 to A17 specify
the page address. All bytes that are loaded into the page buffer must have the same page address.
A0 to A6 specify the byte address within the page. The bytes may be loaded in any order; sequential
loading is not required.

In the internal write cycle, all data in the page buffers, i.e., 128 bytes of data, are written
simultaneously into the memory array. Before the completion of the internal write cycle, the host is
free to perform other tasks such as fetching data from other locations in the system to prepare to
write the next page.

, whichever

Software-protected Data Write

The device provides a JEDEC-approved optional software-protected data write. Once this scheme is
enabled, any write operation requires a three-byte command sequence (with specific data to a
specific address) to be performed before the data load operation. The three-byte load command
sequence begins the page load cycle, without which the write operation will not be activated. This
write scheme provides optimal protection against inadvertent write cycles, such as cycles triggered by
noise during system power-up and power-down.

The W29C020 is shipped with the software data protection enabled. To enable the software data
protection scheme, perform the three-byte command cycle at the beginning of a page load cycle. The
device will then enter the software data protection mode, and any subsequent write operation must be
preceded by the three-byte command sequence cycle. Once enabled, the software data protection

Publication Release Date: February 1998

- 3 - Revision A3

W29C020

DATA

will remain enabled unless the disable commands are issued. A power transition will not reset the
software data protection feature. To reset the device to unprotected mode, a six-byte command
sequence is required. For information about specific codes, see the Command Codes for Software
Data Protection in the Table of Operating Modes. For information about timing waveforms, see the
timing diagrams below.

Hardware Data Protection

The integrity of the data stored in the W29C020 is also hardware protected in the following ways:
(1) Noise/Glitch Protection: A WE pulse of less than 15 nS in duration will not initiate a write cycle.

(2) VDD Power Up/Down Detection: The write operation is inhibited when VDD is less than 2.5V.
(3) Write Inhibit Mode: Forcing OE low, CE high, or WE high will inhibit the write operation. This

prevents inadvertent writes during power-up or power-down periods.

(4) VDD power-on delay: When VDD reaches its sense level, the device will automatically timeout for

5 mS before any write (erase/program) operation.

Chip Erase Modes

The entire device can be erased by using a six-byte software command code. See the Software Chip
Erase Timing Diagram.

Boot Block Operation

There are two boot blocks (8K bytes each) in this device, which can be used to store boot code. One
of them is located in the first 8K bytes and the other is located in the last 8K bytes of the memory.
The first 8K or last 8K of the memory can be set as a boot block by using a seven-byte command
sequence.

See Command Codes for Boot Block Lockout Enable for the specific code. Once this feature is set
the data for the designated block cannot be erased or programmed (programming lockout); other
memory locations can be changed by the regular programming method. Once the boot block
programming lockout feature is activated, the chip erase function will be disabled. In order to detect
whether the boot block feature is set on the two 8K blocks, users can perform a six-byte command
sequence: enter the product identification mode (see Command Codes for Identification/Boot Block
Lockout Detection for specific code), and then read from address "00002 hex" (for the first 8K bytes)
or "3FFF2 hex" (for the last 8K bytes). If the output data is "FF hex," the boot block programming
lockout feature is activated; if the output data is "FE hex," the lockout feature is deactivated and the
block can be programmed.

To return to normal operation, perform a three-byte command sequence to exit the identification
mode. For the specific code, see Command Codes for Identification/Boot Block Lockout Detection.

Data Polling (DQ7)- Write Status Detection

The W29C020 includes a data polling feature to indicate the end of a write cycle. When the
W29C020 is in the internal write cycle, any attempt to read DQ7 from the last byte loaded during the
page/byte-load cycle will receive the complement of the true data. Once the write cycle is completed.

DQ7 will show the true data. See the

Polling Timing Diagram.

- 4 -

W29C020

WE

CEOEWE

Toggle Bit (DQ6)- Write Status Detection

In addition to data polling, the W29C020 provides another method for determining the end of a write
cycle. During the internal write cycle, any consecutive attempts to read DQ6 will produce alternating
0's and 1's. When the write cycle is completed, this toggling between 0's and 1's will stop. The device
is then ready for the next operation. See Toggle Bit Timing Diagram.

Product Identification

The product ID operation outputs the manufacturer code and device code. The programming
equipment automatically matches the device with its proper erase and programming algorithms.

The manufacturer and device codes can be accessed through software or by hardware operation. In
the software access mode, a six-byte command sequence can be used to access the product ID. A
read from address "00000 hex" outputs the manufacturer code "DA hex." A read from address "00001
hex" outputs the device code "45 hex." The product ID operation can be terminated by a three-byte
command sequence.

In the hardware access mode, access to the product ID is activated by forcing CE and OE low,
high, and raising A9 to 12 volts.

TABLE OF OPERATING MODES

Operating Mode Selection

Operating Range: 0 to 70° C (Ambient Temperature), VDD = 5V ±10%, VSS = 0V, VHH = 12V

MODE PINS

ADDRESS DQ.

Read VIL VIL VIH AIN Dout
Write VIL VIH VIL AIN Din
Standby VIH X X X High Z
Write Inhibit X VIL X X High Z/DOUT

X X VIH X High Z/DOUT
Output Disable X VIH X X High Z
5-Volt Software Chip Erase VIL VIH VIL AIN DIN
Product ID VIL VIL VIH

VIL VIL VIH

A0 = VIL; A1−A17 = VIL;
A9 = VHH

A0 = VIH; A1−A17 = VIL;
A9 = VHH

Manufacturer Code DA
(Hex)

Device Code
45 (Hex)

Publication Release Date: February 1998

- 5 - Revision A3

W29C020

Command Codes for Software Data Protection

BYTE SEQUENCE TO ENABLE PROTECTION TO DISABLE PROTECTION

ADDRESS DATA ADDRESS DATA

0 Write 5555H AAH 5555H AAH
1 Write 2AAAH 55H 2AAAH 55H
2 Write 5555H A0H 5555H 80H
3 Write - - 5555H AAH
4 Write - - 2AAAH 55H
5 Write - - 5555H 20H

Software Data Protection Acquisition Flow

(Optional page-load

operation)

Software Data Protection
Enable Flow

Load data AA

to

address 5555

Load data 55

to

address 2AAA

Load data A0

to

address 5555

Sequentially load

up to 128 bytes

of page data

Pause 10 mS

Exit

Software Data Protection
Disable Flow

Load data AA

to

address 5555

Load data 55

to

address 2AAA

Load data 80

to

address 5555

Load data AA

to

address 5555

Load data 55

to

address 2AAA

Load data 20

to

address 5555

Notes for software program code:
Data Format: DQ7−DQ0 (Hex)
Address Format: A14−A0 (Hex)

Pause 10 mS

Exit

- 6 -

Command Codes for Software Chip Erase

BYTE SEQUENCE ADDRESS DATA

0 Write 5555H AAH
1 Write 2AAAH 55H
2 Write 5555H 80H
3 Write 5555H AAH
4 Write 2AAAH 55H
5 Write 5555H 10H

Software Chip Erase Acquisition Flow

Load data AA

address 5555

Load data 55

address 2AAA

W29C020

to

to

Notes for software chip erase:
Data Format: DQ7−DQ0 (Hex)
Address Format: A14−A0 (Hex)

Load data 80

to

address 5555

Load data AA

to

address 5555

Load data 55

to

address 2AAA

Load data 10

to

address 5555

Pause 50 mS

Exit

Publication Release Date: February 1998

- 7 - Revision A3

W29C020

Command Codes for Product Identification and Boot Block Lockout Detection

BYTE

SEQUENCE

0 Write 5555 AA 5555H AAH 5555H AAH
1 Write 2AAA 55 2AAAH 55H 2AAAH 55H
2 Write 5555 90 5555H 80H 5555H F0H
3 Write - - 5555H AAH - ­4 Write - - 2AAAH 55H - ­5 Write - - 5555H 60H - -

Software Product Identification and Boot Block Lockout Detection Acquisition Flow

ALTERNATE PRODUCT (7)
IDENTIFICATION/BOOT BLOCK
LOCKOUT DETECTION ENTRY

SOFTWARE PRODUCT

IDENTIFICATION/BOOT BLOCK

LOCKOUT DETECTION ENTRY

SOFTWARE PRODUCT

IDENTIFICATION/BOOT BLOCK

LOCKOUT DETECTION EXIT

ADDRESS DATA ADDRESS DATA ADDRESS DATA

Pause 10 µS Pause 10 µS Pause 10 µS

Product
Identification
Entry (1)

Load data AA

to

address 5555

Load data 55

to

address 2AAA

Load data 80

to

address 5555

Load data AA

to

address 5555

Load data 55

to

address 2AAA

Load data 60

to

address 5555

Pause 10 Sµ

Product
Identification
and Boot Block
Lockout Detection
Mode (3)

Read address = 00000

data = DA

Read address = 00001

data = 45

Read address = 00002

data = FF/FE

Read address = 3FFF2

data = FF/FE

(2)

(2)

(4)

(5)

Product
Identification
Exit (1)

Load data AA

address 5555

Load data 55

address 2AAA

Load data F0

address 5555

Pause 10 S

Normal Mode

to

to

to

µ

(6)

Notes for software product identification/boot block lockout detection:
(1) Data Format: DQ7−DQ0 (Hex); Address Format: A14−A0 (Hex)
(2) A1−A16 = VIL; manufacture code is read for A0 = VIL; device code is read for A0 = VIH.

(3) The device does not remain in identification and boot block (address 0002 Hex/3FFF2 Hex respond to first 8K/last 8K) lockout detection mode if

power down.

(4), (5) If the output data is "FF Hex," the boot block programming lockout feature is activated; if the output data "FE Hex," the lockout feature is

inactivated and the block can be programmed.
(6) The device returns to standard operation mode.
(7) This product supports both the JEDEC standard 3 byte command code sequence and original 6 byte command code sequence. For new

designs, Winbond recommends that the 3 byte command code sequence be used.

- 8 -

Command Codes for Boot Block Lockout Enable

BYTE SEQUENCE BOOT BLOCK LOCKOUT FEATURE SET

0 Write 5555H AAH 5555H AAH
1 Write 2AAAH 55H 2AAAH 55H
2 Write 5555H 80H 5555H 80H
3 Write 5555H AAH 5555H AAH
4 Write 2AAAH 55H 2AAAH 55H
5 Write 5555H 40H 5555H 40H
6 Write 00000H 00H 3FFFFH FFH

ON FIRST 8K ADDRESS BOOT BLOCK

ADDRESS DATA ADDRESS DATA

Pause 10 mS Pause 10 mS

Boot Block Lockout Enable Acquisition Flow

Boot Block Lockout
Feature Set on First 8K
Address Boot Block

Load data AA

to

address 5555

Boot Block Lockout
Feature Set on Last 8K
Address Boot Block

Load data AA
address 5555

W29C020

BOOT BLOCK LOCKOUT FEATURE SET

ON LAST 8K ADDRESS BOOT BLOCK

to

Load data 55

to

address 2AAA

Load data 80

to

address 5555

Load data AA

to

address 5555

Load data 55

to

address 2AAA

Load data 40

to

address 5555

Load data 00

to

address 00000

Pause 10 mS

Load data 55

to

address 2AAA

Load data 80

to

address 5555

Load data AA

to

address 5555

Load data 55

to

address 2AAA

Load data 40

to

address 5555

Load data FF

to

address 3FFFF

Pause 10 mS

Notes for boot block lockout enable:

1. Data Format: DQ7−DQ0 (Hex)

2. Address Format: A14−A0 (Hex)

3. If you have any questions about this commend sequence, please contact the local distributor or Winbond Electronics Corp.

Publication Release Date: February 1998

- 9 - Revision A3

W29C020

CE

CE

CE

DC CHARACTERISTICS

Absolute Maximum Ratings

PARAMETER RATING UNIT

Power Supply Voltage to VSS Potential -0.5 to +7.0 V
Operating Temperature 0 to +70
Storage Temperature -65 to +150
D.C. Voltage on Any Pin to Ground Potential Except A9 -0.5 to VDD +1.0 V
Transient Voltage (<20 nS ) on Any Pin to Ground Potential -1.0 to VDD +1.0 V

Voltage on A9 and OE Pin to Ground Potential

Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the

device.

-0.5 to 12.5 V

Operating Characteristics

(VDD = 5.0V ±10%, VSS = 0V, TA = 0 to 70° C)

°C
°C

PARAMETER SYM. TEST CONDITIONS LIMITS UNIT

MIN. TYP. MAX.

Power Supply Current

Standby VDD Current
(TTL input)

Standby VDD Current
(CMOS input)

Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Output High Voltage

CMOS

ICC

ISB1

ISB2

ILI VIN = GND to VDD - - 10
ILO VIN = GND to VDD - - 10
VIL
VIH
VOL IOL = 2.0 mA - - 0.45 V
VOH1
VOH2

= OE = VIL, WE = VIH,

all DQs open
Address inputs = VIL/VIH,

at f = 5 MHz

= VIH, all DQs open

Other inputs = VIL/VIH

= VDD -0.3V, all DQs

open

-

-

IOH = -400 µA
IOH = -100 µA; VCC = 4.5V

- - 50 mA

- 2 3 mA

- 20 100

- - 0.8 V

2.0 - - V

2.4 - - V

4.2 - - V

µA

µA
µA

- 10 -

W29C020

Power-up Timing

PARAMETER SYMBOL TYPICAL UNIT

Power-up to Read Operation TPU. READ 100
Power-up to Write Operation TPU. WRITE 5 mS

CAPACITANCE

(VDD = 5.0V, TA = 25° C, f = 1 MHz)

PARAMETER SYMBOL CONDITIONS MAX. UNIT

DQ Pin Capacitance CDQ VDQ = 0V 12 pF
Input Pin Capacitance CIN VIN = 0V 6 pF

AC CHARACTERISTICS

AC Test Conditions

(VDD = 5.0V ±10% for 90 nS and 120 nS; VDD = 5.0V ±5% for 70 nS)

PARAMETER CONDITIONS

Input Pulse Levels 0V to 3V

Input Rise/Fall Time <5 nS

Input/Output Timing Level 1.5V/1.5V

Output Load 1 TTL Gate and CL = 100 pF for 90/120 nS

CL = 30 pF for 70 nS

µS

AC Test Load and Waveform

D

OUT

100 pF for 90/120 nS

30 pF for 70 nS

(Including Jig and Scope)

Input

3V

0V

Test Point Test Point

+5V

1.8K

Ω

1.3K

Ω

Output

1.5V

1.5V

Publication Release Date: February 1998

- 11 - Revision A3

W29C020

CE

OE

WE

WE

OE

OE

CE

WE

WE

AC Characteristics, continued

Read Cycle Timing Parameters

(VDD = 5.0V ±10% for 90 nS and 120 nS; VDD = 5.0V ±5% for 70 nS, VSS = 0V, TA = 0 to 70° C)

PARAMETER SYM. W29C020-70 W29C020-90 W29C020-12 UNIT

MIN. MAX. MIN. MAX. MIN. MAX.

Read Cycle Time TRC 70 - 90 - 120 - nS
Chip Enable Access Time TCE - 70 - 90 - 120 nS
Address Access Time TAA - 70 - 90 - 120 nS
Output Enable Access Time TOE - 35 - 40 - 50 nS

High to High-Z Output

High to High-Z Output

Output Hold from Address change TOH 0 - 0 - 0 - nS

Byte/Page-write Cycle Timing Parameters

TCHZ - 25 - 25 - 30 nS
TOHZ - 25 - 25 - 30 nS

PARAMETER SYMBOL MIN. TYP. MAX. UNIT

Write Cycle (erase and program) TWC - - 10 mS
Address Setup Time TAS 0 - - nS
Address Hold Time TAH 50 - - nS

and CE Setup Time

and CE Hold Time
High Setup Time
High Hold Time

Pulse Width

Pulse Width

High Width

Data Setup Time TDS 50 - - nS
Data Hold Time TDH 0 - - nS
Byte Load Cycle Time TBLC - - 150

Note: All AC timing signals observe the following guideline for determining setup and hold times:

Reference level is VIH for high-level signal and VIL for low-level signal.

TCS 0 - - nS
TCH 0 - - nS
TOES 0 - - nS
TOEH 0 - - nS
TCP 70 - - nS
TWP 70 - - nS
TWPH 100 - - nS

µS

- 12 -

AC Characteristics, continued

OE

OE

OE

OE

OE

W29C020

DA TA Polling Characteristics

(1)

PARAMETER SYMBOL MIN. TYP. MAX. UNIT

Data Hold Time TDH 10 - - nS

Hold Time
to Output Delay

(2)

TOEH 10 - - nS
TOE - - - nS

Write Recovery Time TWR 0 - - nS

Notes:

(1) These parameters are characterized and not 100% tested.
(2) See TOE spec in A.C. Read Cycle Timing Parameters.

Toggle Bit Characteristics

(1)

PARAMETER SYMBOL MIN. TYP. MAX. UNIT

Data Hold Time TDH 10 - - nS

Hold Time
to Output Delay
High Pulse

(2)

TOEH 10 - - nS
TOE - - - nS
TOEHP 150 - - nS

Write Recovery Time TWR 0 - - nS

Notes:

(1) These parameters are characterized and not 100% tested.
(2) See TOE spec in A.C. Read Cycle Timing Parameters.

TIMING WAVEFORMS

Read Cycle Timing Diagram

Address A17-0

CE

OE

V

WE

DQ7-0

IH

High-Z

T

RC

T

CE

T

OE

T

OHZ

T

OH

AA

T

T

CHZ

Data ValidData Valid

High-Z

Publication Release Date: February 1998

- 13 - Revision A3

Timing Waveforms, continued

WPH

WE Controlled Write Cycle Timing Diagram

Address A17-0

T

AS

T

AH

W29C020

T

WC

CE

OE

WE

DQ7-0

T

CS

T

OES

T

CE Controlled Write Cycle Timing Diagram

AS

Address A17-0

CE

OE

WE

DQ7-0

High Z

T

T

OES

AH

T

TCS

WP

TCP

T

DS

Data Valid

T

DS

Data Valid

T

CH

T

OEH

T

T

DH

T

WPH

T

OEH

CH

T

Internal write starts

TWC

- 14 -

T

DH

Internal Write Starts

Timing Waveforms, continued

Page Write Cycle Timing Diagram

Address A17-0

DQ7-0

CE

W29C020

TWC

OE

WE

DA TA Polling Timing Diagram

Address A15-0

WE

CE

T

OEH

OE

DQ7

T

DH

T

WPH

WP

T

Byte 0 Byte 1

T

OE

TBLC

HIGH-Z

Byte 2

Byte N-1

Internal Write Start

T

WR

Byte N

Publication Release Date: February 1998

- 15 - Revision A3

Timing Waveforms, continued

Toggle Bit Timing Diagram

WE

W29C020

CE

OE

DQ6

T

OEH

T

DH

T

OE

HIGH-Z

Page Write Timing Diagram Software Data Protection Mode

Byte/page load
cycle starts

Word N-1

Address A15-0

DQ7-0

CE

OE
WE

Three-byte sequence for

software data protection mode

2AAA

5555

AA 55 A0

TWP

SW0

TBLC

TWPH

SW1

5555

Word 0SW2

T

Word N

(last word)

WR

TWC

Internal write starts

- 16 -

Timing Waveforms, continued

Reset Software Data Protection Timing Diagram

W29C020

Address A15-0

DQ7-0

CE

OE

WE

5555 2AAA

AA

T

WP

T

WPH

SW0

SW1

55

T

Software Chip Erase Timing Diagram

Address A15-0

5555 2AAA

Six-byte sequence for resetting
software data protection mode

5555

5555 2AAA

80 AA

BLC

SW2

SW3

Six-byte code for 5V-only software
chip erase

5555 5555 2AAA 5555

SW4

55

5555

20

SW5

Internal programming starts

T

WC

T

WC

DQ7-0

WE

CE

OE

AA

T

WP

SW0

55 80 AA

T

BLC

T

WPH

SW1

SW2

SW3

55

SW4

10

SW5

Internal erasing starts

Publication Release Date: February 1998

- 17 - Revision A3

ORDERING INFORMATION

W29C020

PART NO. ACCESS

TIME

(nS)

W29C020-70A 70 50 100 600 mil DIP 100
W29C020-90A 90 50 100 600 mil DIP 100
W29C020-12A 120 50 100 600 mil DIP 100
W29C020S-70A 70 50 100 450 mil SOP 100
W29C020S-90A 90 50 100 450 mil SOP 100
W29C020S-12A 120 50 100 450 mil SOP 100
W29C020T-70A 70 50 100 Type one TSOP 100
W29C020T-90A 90 50 100 Type one TSOP 100
W29C020T-12A 120 50 100 Type one TSOP 100
W29C020P-70A 70 50 100 32-pin PLCC 100
W29C020P-90A 90 50 100 32-pin PLCC 100
W29C020P-12A 120 50 100 32-pin PLCC 100
W29C020-70 70 50 100 600 mil DIP 1K
W29C020-90 90 50 100 600 mil DIP 1K
W29C020-12 120 50 100 600 mil DIP 1K
W29C020S-70 70 50 100 450 mil SOP 1K
W29C020S-90 90 50 100 450 mil SOP 1K
W29C020S-12 120 50 100 450 mil SOP 1K
W29C020T-70 70 50 100 Type one TSOP 1K
W29C020T-90 90 50 100 Type one TSOP 1K
W29C020T-12 120 50 100 Type one TSOP 1K
W29C020P-70 70 50 100 32-pin PLCC 1K
W29C020P-90 90 50 100 32-pin PLCC 1K
W29C020P-12 120 50 100 32-pin PLCC 1K
W29C020-70B 70 50 100 600 mil DIP 10K
W29C020-90B 90 50 100 600 mil DIP 10K
W29C020-12B 120 50 100 600 mil DIP 10K
W29C020S-70B 70 50 100 450 mil SOP 10K
W29C020S-90B 90 50 100 450 mil SOP 10K
W29C020S-12B 120 50 100 450 mil SOP 10K
W29C020T-70B 70 50 100 Type one TSOP 10K
W29C020T-90B 90 50 100 Type one TSOP 10K
W29C020T-12B 120 50 100 Type one TSOP 10K
W29C020P-70B 70 50 100 32-pin PLCC 10K
W29C020P-90B 90 50 100 32-pin PLCC 10K
W29C020P-12B 120 50 100 32-pin PLCC 10K

Notes:

1. Winbond reserves the right to make changes to its products without prior notice.

2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in
applications where personal injury might occur as a consequence of product failure.

POWER

SUPPLY CURRENT

MAX. (mA)

STANDBY

VDD CURRENT

MAX. (µA)

PACKAGE CYCLING

- 18 -

PACKAGE DIMENSIONS

3.Dimensions D & E1 include mold mismatch and

32-pin P-DIP

W29C020

32

1E

1

S

2A

A

L

32-pin SO Wide Body

32

1

D

S

Seating Plane

Dimension in inches

Symbol

Min. Nom. Max. Max.Nom.Min.

A

0.010

A

1

0.150

A
B

D

B

1

e

1B

17

16

1A

Base Plane

Seating Plane

a

17

E H

E

E

e

A

e

1

L

16

b

Detail F

e

1

c

A

A

2

y

e

A

1

See Detail F

L

E

B
c
D
E
E1
e
L

a

e
S

Notes:

1.Dimensions D Max. & S include mold flash or

c

2.Dimension E1 does not include interlead flash.

4.Dimension B1 does not include dambar

5.Controlling dimension: Inches.

6.General appearance spec. should be based on

Symbol

HE

Notes:

1. Dimensions D Max. & S include mold flash
or tie bar burrs.

2. Dimension b does not include dambar
protrusion/intrusion.

3. Dimensions D & E include mold mismatch
and determined at the mold parting line.

4. Controlling dimension: Inches.

5. General appearance spec should be based
on final visual inspection spec.

0.155

2

0.016

0.018

0.050 1.27

1

0.010

0.008

1.650 1.660

0.6000.590

0.545

0.550

1

0.120

0.130

0 15

0.6500.630 16.00 16.51

A

tie bar burrs.

are determined at the mold parting line.
protrusion/intrusion.

final visual inspection spec.

Dimension in Inches Dimension in mm

Nom.

Min.

A

0.004

A

1

0.106

0.101

A

2

0.014

b
c
D
E
e

L
LE
S

y

θ

0.016

0.0080.006

0.805

0.5560.546 14.3814.1213.87

0.023

0.031

0.047

0.055

0

Dimension in mm

0.210

0.25

0.160

3.81

3.94

0.41

0.20

14.99

13.84

3.05

2.29 2.54 2.790.090 0.100 0.110

0.46

0.25

41.91 42.16

15.49

15.24

13.97

3.30

0.022

0.0540.048

0.014

0.610

0.555

0.140

0.670

0.085

.

Min.

0.10

2.57

0.36

11.18

1.12 1.27 1.420.044 0.050

0.58 0.79 0.99

10

Nom.

2.69

0.41

0.200.15

20.45

11.30

1.40

0

Max. Max.

0.118

0.111

0.020

0.012 0.31

0.817

0.4500.4450.440

0.056

0.556

0.039

0.063 1.19

0.036

0.004

.

5.33

4.06

0.56

1.371.22

0.36

14.10

3.56
150

17.02

2.16

3.00

2.82

0.51

20.75

11.43

1.60

0.91

0.10
10

Publication Release Date: February 1998

- 19 - Revision A3

Package Dimensions, continued

32-pin PLCC

H

E

E

1

324

5

13

14

L

θ

Seating Plane

e

b

1b

E

G

W29C020

30

29

D

D

H D

21

20

2A

A

1

A

y

G

c

Dimension in Inches Dimension in mm

Symbol

Min. Nom. Max. Max.Nom.Min.

A

0.020

A

1

A

2

b

1

0.016

b

0.008

c

0.547

D

0.447

E

e
GD

0.390

G

E

0.585

H

D

0.485

H

E

0.075

L
y

°

0

θ

0.140

0.50

0.1150.105 0.110

0.66 0.81

0.0320.026

0.028

0.018

0.010

0.550

0.450

0.050

0.410

0.590

0.490

0.090

0.41

0.022

0.20

0.014

13.89

0.553

11.35

0.453

1.12 1.420.044 0.056

12.45

0.5300.5100.490

9.91

0.430

14.86

0.595

12.32

0.495

1.91

0.095

0.004

°

10

0

°

2.802.67 2.93

0.71

0.46

0.25

13.97

11.43

1.27

12.95

10.41

14.99

12.45

2.29

3.56

0.56

0.35

14.05

11.51

13.46

10.92

15.11

12.57

2.41

0.10

°

10

Notes:

1. Dimensions D & E do not include interlead flash.

2. Dimension b1 does not include dambar protrusion/intrusion.

3. Controlling dimension: Inches.

4. General appearance spec. should be based on final
visual inspection sepc.

32-pin TSOP

M

e

0.10(0.004)

b

θ

L

L

1

D

H

D

c

E

A

A

2

A

1

Y

Symbol

Note:

A
A

1

2

A

b

c
D
E

H D
e

L
L

1

Y

θ

Dimension in Inches

Min. Nom. Max.

__

__

0.002

0.037

0.007 0.008

0.005 0.006

0.720 0.724

0.311 0.315

0.780 0.787

__

0.016 0.020

__

0.000 0.004
1

__

0.039

0.020

0.031

__

3 5

0.047

0.006

0.041

0.009

0.007

0.728

0.319

0.795

0.024

__

__

Dimension in mm

Min.

Nom.

__

__

__

0.05

0.95

0.17

0.20 0.23

0.12

0.15 0.17

18.30

18.40 18.50

7.90

8.00 8.10

19.80

20.00 20.20

__

0.50

0.40

0.50 0.60

__

0.80

__

0.00
1

3 5

Max.

1.20

0.15

1.051.00

__

__

0.10

Controlling dimension: Millimeters

- 20 -

VERSION HISTORY

Note: All data and specifications are subject to change without notice.

VERSION DATE PAGE DESCRIPTION

A1 Apr. 1997 Initial Issued
A2 Nov. 1997 4, 8 Correct the address from 3FFF2 to 7FFF2

9 Correct the boot block from 8K to 16K

15 Modify page write cycle timing diagram waveform

1, 18 Delete cycling 100K item

A3 Feb. 1998 6 Add. pause 10 mS

7 Add. pause 50 mS

W29C020

1, 18 Add. cycling 100 item

Headquarters

No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: [phone]
FAX: [phone]
http://www.winbond.com.tw/
Voice & Fax-on-demand: 886-2-27197006

Taipei Office

11F, No. 115, Sec. 3, Min-Sheng East Rd.,
Taipei, Taiwan
TEL: [phone]
FAX: [phone]

Winbond Electronics (H.K.) Ltd.

Rm. 803, World Trade Square, Tower II,
123 Hoi Bun Rd., Kwun Tong,
Kowloon, Hong Kong
TEL: [phone]
FAX: [phone]

8

Correct the time from 10 mS to 10 µS

Winbond Electronics North America Corp.
Winbond Memory Lab.
Winbond Microelectronics Corp.
Winbond Systems Lab.

2727 N. First Street, San Jose,
CA 95134, U.S.A.
TEL: [phone]

FAX: [phone]

Publication Release Date: February 1998

- 21 - Revision A3