Datasheet W27E512S-90, W27E512S-70, W27E512S-45, W27E512S-55, W27E512S-15 Datasheet (Winbond Electronics)

W27E512

A3

CE

OE

64K × 8 ELECTRICALLY ERASABLE EPROM

GENERAL DESCRIPTION

The W27E512 is a high speed, low power Electrically Erasable and Programmable Read Only
Memory organized as 65536 × 8 bits that operates on a single 5 volt power supply. The W27E512
provides an electrical chip erase function.

FEATURES

• High speed access time:

45/55/70/90/120/150 nS (max.)

• Read operating current: 30 mA (max.)

• Erase/Programming operating current

30 mA (max.)

• Standby current: 1 mA (max.)

• Single 5V power supply

• +14V erase/+12V programming voltage

• Fully static operation

• All inputs and outputs directly TTL/CMOS

compatible

• Three-state outputs

• Available packages: 28-pin 600 mil DIP, 330 mil

SOP, TSOP and 32-pin PLCC

PIN CONFIGURATIONS

1

OE/Vpp

V

A6
A5
A4
A3
A2
A1
A0
NC
Q0

A11

A13
A14

A15
A12

A15

2

A12

3

A7

4

A6

5

A5

6

A4

7

A3

8

A2

9

A1

10

A0

11

Q0

12

Q1

13

Q2

14

GND

A

A7N

1
2

4 3 2 1
5
6

7
8
9
10
11
12

1

151

13

4

Q1Q

1
2

A9

3

A8

4
5
6

CC

7
8
9
10

A7

11

A6

12

A5

13

A4

14

28
27
26
25
24
23

28-pin

DIP

22
21
20
19
18
17
16
15

A

A

V

A

1

1

C

1

C

4

3

C

5

3

3

3

2

1

0 29

32-pin
PLCC

18192

1

0

7

6

Q

Q

G

N

2

3Q4

N

5

C

D

28-pin
TSOP

28
27
26
25
24
23
22
21

28
27
26
25
24
23
22
21
20
19
18
17
16
15

V

CC

A14
A13
A8
A9
A11

OE/Vpp
A10

CE
Q7

Q6
Q5
Q4
Q3

A8
A9
A11
NC

OE/Vpp
A10

CE
Q7
Q6

A10
CE

Q7
Q6
Q5
Q4
Q3

GND
Q2
Q1
Q0
A0
A1
A2

BLOCK DIAGRAM

Q0

.
.

Q7

OE/V

CE

PP

CONTROL

OUTPUT
BUFFER

A0

.

DECODER

.

CORE

ARRAY

A15

V

CC

GND

PIN DESCRIPTION

SYMBOL DESCRIPTION

A0−A15

Q0−Q7

/VPP

VCC Power Supply

GND Ground

NC No Connection

Address Inputs
Data Inputs/Outputs
Chip Enable
Output Enable, Program/Erase

Supply Voltage

Publication Release Date: June 2000

- 1 - Revision A9

W27E512

CE

FUNCTIONAL DESCRIPTION

Read Mode

Like conventional UVEPROMs, the W27E512 has two control functions, both of which produce data
at the outputs. CE is for power control and chip select. OE/VPP controls the output buffer to gate data

to the output pins. When addresses are stable, the address access time (T
from CE to output (TCE), and data are available at the outputs TOE after the falling edge of OE/VPP,

ACC

if T

and TCE timings are met.

Erase Mode

The erase operation is the only way to change data from "0" to "1." Unlike conventional UVEPROMs,
which use ultraviolet light to erase the contents of the entire chip (a procedure that requires up to half
an hour), the W27E512 uses electrical erasure. Generally, the chip can be erased within 100 mS by
using an EPROM writer with a special erase algorithm.

Erase mode is entered when OE/VPP is raised to VPE (14V), VCC = VCE (5V), A9 = VPE (14V), A0
low, and all other address pins low and data input pins high. Pulsing CE low starts the erase

operation.

Erase Verify Mode

After an erase operation, all of the bytes in the chip must be verified to check whether they have been
successfully erased to "1" or not. The erase verify mode ensures a substantial erase margin if VCC =

VCE (3.75V), CE low, and OE/VPP low.

ACC

) is equal to the delay

Program Mode

Programming is performed exactly as it is in conventional UVEPROMs, and programming is the only
way to change cell data from "1" to "0." The program mode is entered when OE/VPP is raised to VPP

(12V), VCC = VCP (5V), the address pins equal the desired addresses, and the input pins equal the
desired inputs. Pulsing CE low starts the programming operation.

Program Verify Mode

All of the bytes in the chip must be verified to check whether they have been successfully
programmed with the desired data or not. Hence, after each byte is programmed, a program verify
operation should be performed. The program verify mode automatically ensures a substantial

program margin. This mode will be entered after the program operation if OE/VPP low and CE low.

Erase/Program Inhibit

Erase or program inhibit mode allows parallel erasing or programming of multiple chips with different
data. When CE high, erasing or programming of non-target chips is inhibited, so that except for the

and OE/VPP pins, the W27E512 may have common inputs.

- 2 -

W27E512

CE OE

Standby Mode

The standby mode significantly reduces VCC current. This mode is entered when CE high. In standby
mode, all outputs are in a high impedance state, independent of OE/VPP.

Two-line Output Control

Since EPROMs are often used in large memory arrays, the W27E512 provides two control inputs for
multiple memory connections. Two-line control provides for lowest possible memory power
dissipation and ensures that data bus contention will not occur.

System Considerations

An EPROM's power switching characteristics require careful device decoupling. System designers are
interested in three supply current issues: standby current levels (ISB), active current levels (ICC), and

transient current peaks produced by the falling and rising edges of CE. Transient current magnitudes
depend on the device output's capacitive and inductive loading. Two-line control and proper
decoupling capacitor selection will suppress transient voltage peaks. Each device should have a 0.1 µ
F ceramic capacitor connected between its VCC and GND. This high frequency, low inherent­inductance capacitor should be placed as close as possible to the device. Additionally, for every eight
devices, a 4.7 µF electrolytic capacitor should be placed at the array's power supply connection
between VCC and GND. The bulk capacitor will overcome voltage slumps caused by PC board trace
inductances.

TABLE OF OPERATING MODES

(VPP = 12V, VPE = 14V, VHH = 12V, VCP = 5V, VCE = 5V, X = VIH or VIL)

MODE PINS

Read VIL VIL X X VCC D
Output Disable VIL VIH X X VCC High Z
Standby (TTL) VIH X X X VCC High Z
Standby (CMOS)
Program VIL VPP X X VCP DIN
Program Verify VIL VIL X X VCC D
Program Inhibit VIH VPP X X VCP High Z
Erase VIL VPE VIL VPE VCE DIH
Erase Verify VIL VIL X X 3.75 D
Erase Inhibit VIH VPE X X VCE High Z
Product Identifier-manufacturer VIL VIL VIL VHH VCC DA (Hex)
Product Identifier-device VIL VIL VIH VHH VCC 08 (Hex)

VCC ±0.3V

/VPP

X X X VCC High Z

A0 A9 VCC OUTPUTS

OUT

OUT

OUT

Publication Release Date: June 2000

- 3 - Revision A9

DC CHARACTERISTICS

OE

CE

CE

OE

Absolute Maximum Ratings

PARAMETER RATING UNIT

W27E512

Ambient Temperature with Power Applied -55 to +125
Storage Temperature -65 to +125
Voltage on all Pins with Respect to Ground Except

PP,

/V

A9 and VCC Pins

Voltage on OE/VPP Pin with Respect to Ground
Voltage on A9 Pin with Respect to Ground -0.5 to +14.5 V
Voltage VCC Pin with Respect to Ground -0.5 to +7 V

Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability
of the device.

-0.5 to VCC +0.5 V

-0.5 to +14.5 V

°

C

°

C

DC Erase Characteristics

(TA = 25° C ±5° C, VCC = 5.0V ±10%)

PARAMETER SYM.

Input Load Current ILI VIN = VIL or VIH -10 - 10
VCC Erase Current ICP
VPP Erase Current IPP

Input Low Voltage VIL - -0.3 - 0.8 V
Input High Voltage VIH - 2.4 - 5.5 V
Output Low Voltage (Verify) VOL IOL = 2.1 mA - - 0.45 V
Output High Voltage (Verify) VOH IOH = -0.4 mA 2.4 - - ­A9 Erase Voltage VID - 13.25 14 14.25 V
VPP Erase Voltage VPE - 13.25 14 14.25 V
VCC Supply Voltage (Erase) VCE - 4.5 5.0 5.5 V
VCC Supply Voltage

(Erase Verify)

Note: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP.

VCE - 3.5 3.75 4.0 V

CONDITIONS LIMITS UNIT

MIN. TYP. MAX.

µ

IL,

= V

OE/VPP = VPE

IL,

= V

/VPP = VPE

- - 30 mA

- - 30 mA

A

- 4 -

W27E512

100 pF for 90/120/150 nS (Including Jig and Scope)

Input

CAPACITANCE

(VCC = 5V, TA = 25° C, f = 1 MHz)

PARAMETER SYMBOL CONDITIONS MAX. UNIT

Input Capacitance CIN VIN = 0V 6 pF
Output Capacitance C

OUT

V

AC CHARACTERISTICS

AC Test Conditions

PARAMETER CONDITIONS

Input Pulse Levels 0 to 3.0V
Input Rise and Fall Times 5 nS
Input and Output Timing Reference Level 1.5V/1.5V
Output Load CL = 30 pF,

AC Test Load and Waveforms

OUT

= 0V 12 pF

IOH/IOL = -0.4 mA/2.1 mA

D

OUT

3.0V

+1.3V

(IN914)

3.3K ohm

30 pF for 45/55/70 nS (Including Jig and Scope)

Output

Test Point Test Point

0V

1.5V

1.5V

- 5 - Revision A9

Publication Release Date: June 2000

W27E512

CE

CE

CE

READ OPERATION DC CHARACTERISTICS

(VCC = 5.0V ±10%, TA = 0 to 70° C)

PARAMETER SYM. CONDITIONS LIMITS UNIT

MIN. TYP. MAX.
Input Load Current
Output Leakage

ILI
ILO

VIN = 0V to VCC -5 - 5

OUT

V

= 0V to VCC -10 - 10

µ
µ

Current
Standby VCC Current

ISB

= VIH

- - 1.0 mA

(TTL input)

SB1

I

Standby VCC Current

= VCC ±0.2V

- 5 100

µ

(CMOS input)
VCC Operating Current

ICC

OUT

I

= V

IL

= 0 mA

- - 30 mA

f = 5 MHz
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage

VIL
VIH
VOL
VOH

- -0.3 - 0.8 V

- 2.0 - V

CC

+0.5 V
IOL = 2.1 mA - - 0.45 V
IOH = -0.4 mA 2.4 - - V

READ OPERATION AC CHARACTERISTICS

(VCC = 5.0V ±10%, TA = 0 to 70° C)

PARAMETER SYM. W27E512-45 W27E512-55 W27E512-70 W27E512-90 W27E512-12 W27E512-15 UNIT

Read Cycle Time TRC 45 - 55 - 70 - 90 - 120 - 150 - nS
Chip Enable

Access Time
Address Access

Time
Output Enable

Access Time

OE /VPP High to

High-Z Output
Output Hold from

Address Change

Note: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP.

MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.

TCE - 45 - 55 - 70 - 90 - 120 - 150 nS

ACC

T

- 45 - 55 - 70 - 90 - 120 - 150 nS

TOE - 20 - 25 - 30 - 40 - 55 - 60 nS

TDF - 20 - 20 - 30 - 30 - 30 - 50 nS

TOH 0 - 0 - 0 - 0 - 0 - 0 - nS

A
A

A

- 6 -

DC PROGRAMMING CHARACTERISTICS

(VCC = 5.0V ±10%, TA = 25° C ±5° C)

PARAMETER SYM. CONDITIONS LIMITS UNIT

Input Load Current
VCC Program Current I

VPP Program Current

Input Low Voltage
Input High Voltage
Output Low Voltage (Verify)
Output High Voltage (Verify)
A9 Silicon I.D. Voltage
VPP Program Voltage
VCC Supply Voltage (Program)

ILI

CP

IPP

VIL
VIH
VOL IOL
VOH IOH
VID
VPP
VCP

VIN = VIL or VIH -10 - 10

CE

= VIL,

OE

/VPP = VPP

CE

= VIL,

OE

/VPP = VPP

- -0.3 - 0.8 V

- 2.4 - 5.5 V

= 2.1 mA - - 0.45 V

= -0.4 mA 2.4 - - V

- 11.5 12.0 12.5 V

- 11.75 12.0 12.25 V

- 4.5 5.0 5.5 V

MIN. TYP. MAX.

- - 30 mA

- - 30 mA

AC PROGRAMMING/ERASE CHARACTERISTICS

(VCC = 5.0V ±10%, TA = 25° C ±5° C)

PARAMETER SYM. LIMITS UNIT

PRT

OE

/VPP Pulse Rise Time

Data Setup Time T

CE

Program Pulse Width

CE

Erase Pulse Width

Data Hold Time T

OE

/VPP Setup Time

OE

/VPP Hold Time

Data Valid from CE
Data Valid from Address Change T

CE

High to Output High Z

Address Setup Time T
Address Hold Time T

Address Hold Time after CE High (Erase)

OE

/VPP Valid after CE High

OE

/VPP Recovery Time
Address Access Time during Erase Verify (VCC = 3.75V) T
Output Enable Access Time during Erase Verify (VCC = 3.75V) T

Note: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP.

T

DS
PWP

T

PWE

T

DH
OES

T

OEH

T

DV1

T

DV2
DFP

T

AS
AH
AHC

T

VS

T

VR

T

ACV
OEV

MIN. TYP. MAX.

50 - - nS

2.0 - ­95 100 105

95 100 105 mS

2.0 - -

2.0 - -

2.0 - ­25 - 1
25 - 1

0 - 130 nS

2.0 - -

0 - -

2.0 - -

2.0 - -

2.0 - -

- - 250 nS

- - 150 nS

W27E512

µA

µS
µS

S

µ
µS

µS

S

µ
µS

µS
µS
µS

µS
µS

Publication Release Date: June 2000

- 7 - Revision A9

TIMING WAVEFORMS

Address Valid

AC Read Waveform

IH

V

Address

OE/Vpp

CE

Outputs

V
VIH
V

V

V

IL

IL

IH

IL

High Z

Address Valid

CE

T

TACC

TOE

Valid Output

W27E512

DF

T

OH

T

High Z

Erase Waveform

Data

Vcc

CE

V

V

5V

14.0V

V
V

V

V

Address

OE/Vpp

Read

Read

Company

Device

SID

SID

A9=12.0V

Others=V

IH

IL

T

OE

IH
IL

T

IH

IL

IL

A0=V

A0=V

IL

Others=V

T

T

ACC

ACC

DA 08

T

OE

CE T

IH

IL

VS

Others=V

T

AS

T

DS

T

OES

T

PRT

Chip Erase
A9= 14.0V

IL

T

Data All One

T

T

T

PWE

AHC

DH

OEH

Address Valid

T

VCS

V

IH

T

VR

T

ACV

T

=250 nS

OEV

Erase Verify

Address Valid Address Valid

T

=250 nS

ACV

D

OUT

=150 nS

Always=V

3.75V

D

OUT

IL

V

IH

Blank Check
Read Verify

T

ACC

D

OUT

T

OE

- 8 -

Timing Waveforms, continued

Programming Waveform

W27E512

Address

Data

OE/Vpp

CE

V

IH

V

IL

V

IH

V

IL

12.0V

V

IH

V

IL

V

IH

IL

V

Address Stable

T

T

DS

T

OES

T

PRT

AS

Data In Stable

T

PWP

Program Program

Address
Stable

T

AH

T

AS

Data In
Stable

T

DS

T

DH

Address
Stable

T

T

Address
Valid

T

AH

Data

Out

DH

T

DV1

OEH

VIL

T

VR

V

IL

CE should not be toggled
during program verify period

Verify

T

DV2

Read
Verify

Address
Valid

T

OH

T

DFP

Data
Out

T

ACC

T

OH

T

OE

T

CE

Publication Release Date: June 2000

- 9 - Revision A9

SMART PROGRAMMING ALGORITHM 1

Start

Address = First Location

Vcc = 5.0V

OE/Vpp = 12V

W27E512

Increment

Address

Increment

Address

Last

Address?

Yes

No

No

Program One 100 S Pulse

Address = First Location

Pass

Program One 100 S Pulse

Last

Address?

Yes

X = 0

Verify

Byte

Vcc = 5.0V
OE/Vpp = V

µ

Fail

µ

IL

No

Increment X

X = 25 ?

Yes

Compare

All Bytes to

Original

Data

Pass

Device
Passed

- 10 -

Fail

Device

Failed

SMART PROGRAMMING ALGORITHM 2

Start

Address = First Location

Vcc = 5.0V

X = 0

W27E512

Increment

Address

Fail

Program One 100 S Pulse

OE/V = 12V

µ

PP

Increment X

X = 25?

No

Verify One Byte

OE/V = V

IL

PP

Pass

No

Last Address
?

Yes

Compare

All Bytes to

Original

Data

Pass

Device
Passed

Yes

Verify One Byte

OE/V = V

PP

Fail

IL

Pass

Fail

Device

Failed

Publication Release Date: June 2000

- 11 - Revision A9

SMART ERASE ALGORITHM

W27E512

Start

X = 0

Vcc = 5V

OE/Vpp = 14V

Increment
Address

A9 = 14V; A0 = V

Chip Erase 100 mS Pulse

Address = First Location

Increment X

Vcc = 3.75V

OE/Vpp = V

Erase
Verify

No

Last
Address?

Vcc = 5V

OE/Vpp = V

IL

IL

Fail

Pass

Yes

IL

No

X = 20 ?

Yes

Compare
All Bytes to
FFs (HEX)

Pass

Pass
Device

- 12 -

Fail

Fail
Device

ORDERING INFORMATION

W27E512

PART NO. ACCESS

TIME

(nS)

W27E512-45 45 30 100 600 mil DIP
W27E512-55 55 30 100 600 mil DIP
W27E512-70 70 30 100 600 mil DIP
W27E512-90 90 30 100 600 mil DIP
W27E512-12 120 30 100 600 mil DIP
W27E512-15 150 30 100 600 mil DIP
W27E512S-45 45 30 100 300 mil SOP
W27E512S-55 55 30 100 300 mil SOP
W27E512S-70 70 30 100 300 mil SOP
W27E512S-90 90 30 100 300 mil SOP
W27E512S-12 120 30 100 300 mil SOP
W27E512S-15 150 30 100 300 mil SOP
W27E512Q-45 45 30 100 28-pin TSOP
W27E512Q-55 55 30 100 28-pin TSOP
W27E512Q-70 70 30 100 28-pin TSOP
W27E512Q-90 90 30 100 28-pin TSOP
W27E512Q-12 120 30 100 28-pin TSOP
W27E512Q-15 150 30 100 28-pin TSOP
W27E512P-45 45 30 100 32-pin PLCC
W27E512P-55 55 30 100 32-pin PLCC
W27E512P-70 70 30 100 32-pin PLCC
W27E512P-90 90 30 100 32-pin PLCC
W27E512P-12 120 30 100 32-pin PLCC
W27E512P-15 150 30 100 32-pin PLCC

OPERATING

CURRENT
MAX. (mA)

STANDBY
CURRENT

MAX. (µA)

PACKAGE

Notes:

1. Winbond reserves the right to make changes to its products without prior notice.

2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications
where personal injury might occur as a consequence of product failure.

Publication Release Date: June 2000

- 13 - Revision A9

PACKAGE DIMENSIONS

3. Dimensions D & E1 include mold mismatch and

28-pin P-DIP

W27E512

28

E

1

1

S

2

A

A

L

D

B
B

1

28-pin SO Wide Body

28

1

D

S

Seating Plane

e

Dimension in Inches

Symbol

A
A
A
B
B
c
D

15

14

E

1

A

Base Plane
Seating Plane

e

1

e

a

A

c

E
E1
e
L

a

e
S

Notes:

1. Dimensions D Max. & S include mold flash or
tie bar burrs.

2. Dimension E1 does not include interlead flash.
are determined at the mold parting line.

4. Dimension B1 does not include dambar
protrusion/intrusion.

5. Controlling dimension: Inches.

6. General appearance spec. should be based on
final visual inspection spec.

Symbol

A
A
A
b

15

E

E H

14

b

A

A

2

1

y

A

See Detail F

1

e

θ

L

Detail F

e

1

c

E

L

c
D
E

e
HE
L

LE
S
y

θ

Notes:

1. Dimensions D Max. & S include mold flash
or tie bar burrs.

2. Dimension b does not include dambar
protrusion/intrusion.

3. Dimensions D & E include mold mismatch
and determined at the mold parting line.

4. Controlling dimension: Inches.

5. General appearance spec should be based
on final visual inspection spec.

Nom.

Min.

0.010

1

0.155

0.150

2

0.016

0.018

0.060 1.52

1

0.008

0.010

1.460 1.470

0.6000.590

0.540 0.5500.545

1

0.120

0.130

0 15

0.630

0.650

A

Dimension in Inches Dimension in mm

Nom.

Min.

0.004

1

0.098

0.093

2

0.014

0.016

0.713

0.028

0.036

0.059

0.067

0 10

Dimension in mm

Nom.

Max. Max.

Min.

0.210

0.25

0.160

3.81

0.41

0.20

14.99

13.72 13.9713.84

2.29 2.54 2.790.090 0.100

3.05

16.00 16.51

Nom.

Min.

0.10

2.36

2.49

0.36

0.41

0.250.200.0100.008

18.11

8.28

8.41

1.12 1.27 1.420.044 0.050 0.056

0.91 1.12

0.71

1.70

0

3.94

0.46

0.25

37.08

15.24

3.30

2.85

2.62

0.51

18.62

8.53

1.91

0.022

0.0640.058

0.014

0.610

0.110

0.140

0.670

0.090

Max. Max.

0.112

0.103

0.020

0.014 0.36

0.733

0.3360.3310.326

0.4770.4650.453 12.1211.8111.51

0.044

0.075 1.50

0.004

.

5.33

4.06

0.56

1.631.47

0.36

37.34

15.49

3.56
150

17.02

2.29

1.190.047

0.10
10

- 14 -

Package Dimensions, continued

28-pin Standard Type One TSOP

W27E512

1

e

b

θ

L

L

32-pin PLCC

5

13

14

L

θ

Seating Plane

H

D

D

c

E

A

2

A

A

1

Y

1

H

E

E

1

324

30

29

D

D H

21

20

2A

A

e

b

1b

EG

1

A

y

GD

c

Symbol

A
A
A

b

c
D
E
H
e

L

L

Y

θ

1
2

D

1

Dimension In Inches

Min.

Nom. Max. Min. Nom.

0.002

0.040

0.035

0.007 0.008 0.011

0.004

0.006

0.461 0.465 0.469

0.311 0.315 0.319

0.520 0.528 0.536

0.022

0.020

0.024 0.028

0.010

0.000 0.004
0

3

0.047

0.006

0.041

0.008

5

Dimension In mm

0.05

0.95

1.00

0.17

0.20 0.27

0.10

0.15 0.21

11.70

11.80

7.90

8.00 8.10

13.20

13.40

0.55

0.50

0.60

0.25

0.00
0

3

Max.

1.20

0.15

1.05

11.90

13.60

0.70

0.10
5

Controlling dimension: Millimeters

0.140

0.1150.105 0.110

0.0320.026

0.022

0.014

0.553

0.453

0.530

0.430

0.595

0.495

0.095

0.004

°

10

Dimension in mm

0.50

2.802.67 2.93

0.66 0.81

0.71

0.41

0.46

0.20

0.25

13.89

13.97

11.35

11.43

1.12 1.420.044 0.056

1.27

12.95

12.45

9.91

10.41

14.86

14.99

12.32

12.45

1.91

2.29

°

0

3.56

0.56

0.35

14.05

11.51

13.46

10.92

15.11

12.57

2.41

0.10

°

10

Dimension in Inches

Symbol

Min. Nom. Max. Max.Nom.Min.

A

0.020

A

1

A

2

b
b

c
D
E

e
G
G

H

H

L

y

θ

Notes:

1. Dimension D & E do not include interlead flash.

2. Dimension b does not include dambar protrusion/intrusion.

3. Controlling dimension: Inches.

4. General appearance spec. should be based on final visual
inspection spec.

0.028

1

0.016

0.018

0.008

0.010

0.547

0.550

0.447

0.450

0.050

0.490

0.510

D

0.390

0.410

E

0.585

0.590

D

0.485

0.49

E

0.075

0.090

°

0

Publication Release Date: June 2000

- 15 - Revision A9

W27E512

Winbond Electronics North America Corp.

Winbond Electronics North America Corp.

VERSION HISTORY

VERSION DATE PAGE DESCRIPTION

A6 Apr. 1997 1, 13, 14 Add SOP package
A7 Feb. 1998 1, 2, 3, 5, 6, 13 Add 45/55 nS bining
A8 Nov. 1999 2, 3 Modify function description ( VIL and VIH):

VIL → Low. VIH → High.

4 Modify A9 and VPP Erase Voltage (VID and VPP):

from 13.75V (min) to 13.25V (min)

6 Modify VCC description

A9 Jun. 2000 5 Modify Input Pulse Levels in AC Test Conditions

Headquarters

Headquarters

No. 4, Creation Rd. III,

No. 4, Creation Rd. III,
Science-Based Industrial Park,

Science-Based Industrial Park,
Hsinchu, Taiwan

Hsinchu, Taiwan
TEL: [phone]

TEL: [phone]
FAX: [phone]

FAX: [phone]
http://www.winbond.com.tw/

http://www.winbond.com.tw/
Voice & Fax-on-demand: 886-2-27197006

Voice & Fax-on-demand: 886-2-27197006

Taipei Office

Taipei Office

11F, No. 115, Sec. 3, Min-Sheng East Rd.,

11F, No. 115, Sec. 3, Min-Sheng East Rd.,
Taipei, Taiwan

Taipei, Taiwan
TEL: [phone]

TEL: [phone]
FAX: [phone]

FAX: [phone]

Note: All data and specifications are subject to change withou t notice.

Note: All data and specifications are subject to change withou t notice.

Winbond Electronics (H.K.) Ltd.

Winbond Electronics (H.K.) Ltd.

Unit 9-15, 22F, Millennium City,

Unit 9-15, 22F, Millennium City,
No. 378 Kwun Tong Rd;

No. 378 Kwun Tong Rd;
Kowloon, Hong Kong

Kowloon, Hong Kong
TEL: [phone]

TEL: [phone]
FAX: [phone]

FAX: [phone]

- 16 -

Winbond Memory Lab.

Winbond Memory Lab.
Winbond Microelectronics Corp.

Winbond Microelectronics Corp.
Winbond Systems Lab.

Winbond Systems Lab.

2727 N. First Street, San Jose,

2727 N. First Street, San Jose,
CA 95134, U.S.A.

CA 95134, U.S.A.
TEL: [phone]

TEL: [phone]
FAX: [phone]

FAX: [phone]