Datasheet W27E020P-90, W27E020P-12, W27E020P-70, W27E020-90, W27E020-70 Datasheet (Winbond Electronics)

Preliminary W27E020

CE

OE

PGM

256K × 8 ELECTRICALLY ERASABLE EPROM

GENERAL DESCRIPTION

The W27E020 is a high speed, low power Electrically Erasable and Programmable Read Only Memory organized as 262144 × 8 bits that operates on a single 5 volt power supply. The W27E020 provides an electrical chip erase function.

FEATURES

• High speed access time:

70/90/120 nS (max.)

• Read operating current: 30 mA (max.)

• Erase/Programming operating current:

30 mA (max.)

• Standby current: 1 mA (max.)

• Single 5V power supply

• +14V erase/+12V programming voltage

• Fully static operation

• All inputs and outputs directly TTL/CMOS

compatible

• Three-state outputs

• Available packages: 32-pin 600 mil DIP and

PLCC

PIN CONFIGURATIONS

Vpp

1

A16

2

A15

3

A12

4

A7

5

A6

6

A5

7

A4

8

A3

9

A2

10

A1

11

A0

12

Q0

13 14

Q1 Q2

5 6

7 8 9 10 11 12 13

15 16

A

1

5

2

3 2 1

4

32-pin PLCC

1

151

4

Q

2

1

/

A

V

P

1

c

p

G

6

c

p

M

3

2

1

18192

1 7

6

Q4Q

G

Q

5

N

3

D

GND

A7 A6 A5 A4 A3 A2 A1 A0

Q0

BLOCK DIAGRAM

Vcc

32 31

PGM A17

30

A14

29

A13

28

A8

27 26

A9 A11

25 24

OE

23

A10

22

CE

21

Q7

20

Q6

19

Q5

18

Q4

17

Q3

A 1 7

3 0

0

Q 6

A14

29

A13

28

A8

27

A9

26

A11

25

OE

24

A10

23 22

CE

21

Q7

PGM

CE OE

GND

A0

.

A17

V

CONTROL

DECODER

CC

PP

OUTPUT

BUFFER

CORE

ARRAY

PIN DESCRIPTION

SYMBOL DESCRIPTION

A0−A17

Q0−Q7

VPP Program/Erase Supply Voltage VCC Power Supply

Address Inputs Data Inputs/Outputs Chip Enable Output Enable Program Enable

GND Ground

Q0

.

Q7

Publication Release Date: December 1997

- 1 - Revision A1

Preliminary W27E020

CE

PGM

OE

PGM

CE

FUNCTIONAL DESCRIPTION

Read Mode

Like conventional UVEPROMs, the W27E020 has two control functions, both of which produce data at the outputs.

is for power control and chip select. OE controls the output buffer to gate data to the output pins. When addresses are stable, the address access time (TACC) is equal to the delay from CE to output (TCE), and data are available at the outputs TOE after the falling edge of OE, if TACC and TCE timings

are met.

Erase Mode

The erase operation is the only way to change data from "0" to "1." Unlike conventional UVEPROMs, which use ultraviolet light to erase the contents of the entire chip (a procedure that requires up to half an hour), the W27E020 uses electrical erasure. Generally, the chip can be erased within 100 mS by using an EPROM writer with a special erase algorithm.

Erase mode is entered when VPP is raised to VPE (14V), VCC = VCE (5V), CE = VIL, (0.8V or below but higher than GND), OE = VIH (2V or above but lower than VCC), A9 = VID (14V), A0 = VIL, and all other address pins equal VIL and data input pins equal VIH. Pulsing

operation.

low starts the erase

Erase Verify Mode

After an erase operation, all of the bytes in the chip must be verified to check whether they have been successfully erased to "1" or not. The erase verify mode automatically ensures a substantial erase

margin. This mode will be entered after the erase operation if VPP = VPE (14V), CE = VIL, and OE = VIL,

= VIH.

Program Mode

Programming is performed exactly as it is in conventional UVEPROMs, and programming is the only way to change cell data from "1" to "0." The program mode is entered when VPP is raised to VPP

(12V), VCC = VCP (5V), CE = VIL, OE = VIH, the address pins equal the desired addresses, and the input pins equal the desired inputs. Pulsing

low starts the programming operation.

Program Verify Mode

All of the bytes in the chip must be verified to check whether they have been successfully programmed with the desired data or not. Hence, after each byte is programmed, a program verify operation should be performed. The program verify mode automatically ensures a substantial

program margin. This mode will be entered after the program operation if VPP = VPP (12V), CE = VIL,

= VIL, and

= VIH.

Erase/Program Inhibit

Erase or program inhibit mode allows parallel erasing or programming of multiple chips with different data. When CE = VIH, erasing or programming of non-target chips is inhibited, so that except for the

, the W27E020 may have common inputs.

- 2 -

Preliminary W27E020

PGM

CE

OE

PGM

Standby Mode

The standby mode significantly reduces VCC current. This mode is entered when CE = VIH. In standby mode, all outputs are in a high impedance state, independent of OE and

Two-line Output Control

Since EPROMs are often used in large memory arrays, the W27E020 provides two control inputs for multiple memory connections. Two-line control provides for lowest possible memory power dissipation and ensures that data bus contention will not occur.

System Considerations

EPROM power switching characteristics require careful device decoupling. System designers are concerned with three supply current issues: standby current levels (ISB), active current levels (ICC),

and transient current peaks produced by the falling and rising edges of CE. Transient current magnitudes depend on the device output's capacitive and inductive loading. Two-line control and proper decoupling capacitor selection will suppress transient voltage peaks. Each device should have a 0.1 µF ceramic capacitor connected between its VCC and GND. This high frequency, low inherentinductance capacitor should be placed as close as possible to the device. Additionally, for every eight devices, a 4.7 µF electrolytic capacitor should be placed at the array's power supply connection between VCC and GND. The bulk capacitor will overcome voltage slumps caused by PC board trace inductances.

.

TABLE OF OPERATING MODES

VPP = 12V, VPE = 14V, VHH = 12V, VCP = 5V, VCE = 5V, VID = 14V, X = VIH or VIL

MODE PINS

A0 A9 VCC VPP OUTPUTS

Read VIL VIL X X X VCC VCC DOUT Output Disable VIL VIH X X X VCC VCC High Z Standby (TTL) VIH X X X X VCC VCC High Z Standby (CMOS) Program VIL VIH VIL X X VCP VPP DIN Program Verify VIL VIL VIH X X VCC VPP DOUT Program Inhibit VIH X X X X VCP VPP High Z Erase VIL VIH VIL VIL VID VCE VPE FF (Hex) Erase Verify VIL VIL VIH X X VCC VPE DOUT Erase Inhibit VIH X X X X VCE VPE High Z Product Identifier-

manufacturer Product Identifier-device VIL VIL X VIH VHH VCC VCC 85 (Hex)

VCC ±0.3V

VIL VIL X VIL VHH VCC VCC DA (Hex)

X X X X VCC VCC High Z

Publication Release Date: December 1997

- 3 - Revision A1

DC CHARACTERISTICS

CE

PGM

CE

PGM

Absolute Maximum Ratings

PARAMETER RATING UNIT

Preliminary W27E020

Ambient Temperature with Power Applied -55 to +125 Storage Temperature -65 to +125 Voltage on all Pins with Respect to Ground Except VCC, VPP

and A9 Pins Voltage on VCC Pin with Respect to Ground -0.5 to +7 V Voltage on VPP Pin with Respect to Ground -0.5 to +14.5 V Voltage on A9 Pin with Respect to Ground -0.5 to +14.5 V

Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability

of the device.

-0.5 to VCC +0.5 V

DC Erase Characteristics

(TA = 25° C ±5° C, VCC = 5.0V ±10%, VHH = 14V)

PARAMETER SYM. CONDITIONS LIMITS UNIT

MIN. TYP. MAX.

Input Load Current ILI VIN = VIL or VIH -10 - 10 VCC Erase Current ICP

VPP Erase Current IPP

= VIL, OE = VIH,

= VIL, A9 = VHH

= VIL, OE = VIH,

- - 30 mA

°C °C

µA

= VIL, A9 = VHH Input Low Voltage VIL - -0.3 - 0.8 V Input High Voltage VIH - 2.4 - 5.5 V Output Low Voltage (Verify) VOL IOL = 2.1 mA - - 0.45 V Output High Voltage

(Verify) A9 Erase Voltage VID - 13.75 14.0 14.25 V VPP Erase Voltage VPE - 13.75 14.0 14.25 V VCC Supply Voltage

(Erase)

Note: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP.

VOH IOH = -0.4 mA 2.4 - - V

VCE - 4.5 5.0 5.5 V

- 4 -

Preliminary W27E020

CAPACITANCE

(VCC = 5V, TA = 25° C, f = 1 MHz)

PARAMETER SYMBOL CONDITIONS MAX. UNIT

Input Capacitance CIN VIN = 0V 6 pF Output Capacitance COUT VOUT = 0V 12 pF

AC CHARACTERISTICS

AC Test Conditions

PARAMETER CONDITIONS

70 nS 90/120 nS

Input Pulse Levels 0 to 3.0V 0.45V to 2.4V Input Rise and Fall Times 5 nS 10 nS Input and Output Timing Reference

Level Output Load CL = 30 pF,

1.5V/1.5V 0.8V/2.0V

CL = 100 pF,

IOH/IOL = -0.4 mA/2.1 mA

AC Test Load and Waveforms

D

OUT

Input/Output

For 90/120 nS

2.4V

0.45V

3.0V

+1.3V

(IN914)

3.3K ohm

100 pF for 90/120 nS (Including Jig and Scope)

30 pF for 70 nS (Including Jig and Scope)

Test Points Test Points

Test Point Test Point

0V

1.5V

2.0V

0.8V

2.0V

0.8V

1.5VFor 70 nS

Publication Release Date: December 1997

- 5 - Revision A1

Preliminary W27E020

CE

OE

READ OPERATION DC CHARACTERISTICS

(Vcc = 5.0V ±10%)

PARAMETER SYM. CONDITIONS LIMITS UNIT

MIN. TYP. MAX.

Input Load Current ILI VIN = 0V to VCC -5 - 5 Output Leakage Current ILO VOUT = 0V to VCC -10 - 10 Standby VCC Current

(TTL input) Standby VCC Current

(CMOS input) VCC Operating Current ICC

VPP Operating Current IPP VPP = VCC - - 10 Input Low Voltage VIL - -0.3 - 0.8 V Input High Voltage VIH - 2.0 - VCC +0.5 V Output Low Voltage VOL IOL = 2.1 mA - - 0.45 V Output High Voltage VOH IOH = -0.4 mA 2.4 - - V VPP Operating Voltage VPP - VCC -0.7 - VCC V

ISB

ISB1

= VIH

= VCC ±0.2V

= VIL IOUT = 0 mA f = 5 MHz

- - 1.0 mA

- 5 100

- - 30 mA

READ OPERATION AC CHARACTERISTICS

(VCC = 5.0V ±10%, for 70, 90 and 120 nS; TA = 0 to 70° C)

µA µA

µA

PARAMETER SYM. W27E020-70 W27E020-90 W27E020-12 UNIT

MIN. MAX. MIN. MAX. MIN. MAX.

Read Cycle Time TRC 70 - 90 - 120 - nS Chip Enable Access Time TCE - 70 - 90 - 120 nS Address Access Time TACC - 70 - 90 - 120 nS Output Enable Access

Time

High to High-Z Output

Output Hold from Address Change

Note: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP.

TOE - 30 - 40 - 55 nS

TDF - 25 - 25 - 30 nS TOH 0 - 0 - 0 - nS

- 6 -

Preliminary W27E020

CE

PGM

CE

PGM

OE

PGM

CE

DC PROGRAMMING CHARACTERISTICS

(VCC = 5.0V ±10%, TA = 25° C ±5° C)

PARAMETER SYM. CONDITIONS LIMITS UNIT

MIN. TYP. MAX.

Input Load Current ILI VIN = VIL or VIH - VCC Program Current ICP

VPP Program Current IPP

Input Low Voltage VIL - -0.3 - 0.8 V Input High Voltage VIH - 2.4 - 5.5 V Output Low Voltage (Verify) VOL IOL = 2.1 mA - - 0.45 V Output High Voltage (Verify) VOH IOH = -0.4 mA 2.4 - - V A9 Silicon I. D. Voltage VID - 11.5 12.0 12.5 V VPP Program Voltage VPP - 11.75 12.0 12.25 V VCC Supply Voltage (Program) VCP - 4.5 5.0 5.5 V

= VIL, OE = VIH,

= VIL

= VIL, OE = VIH,

= VIL

- - 30 mA

±10 µA

AC PROGRAMMING/ERASE CHARACTERISTICS

(VCC = 5.0V ±10%, TA = 25° C ±5° C)

PARAMETER SYM. LIMITS UNIT

MIN. TYP. MAX.

VPP Setup Time TVPS 2.0 - Address Setup Time TAS 2.0 - Data Setup Time TDS 2.0 - -

Program Pulse Width Erase Pulse Width

Data Hold Time TDH 2.0 - -

Setup Time

Data Valid from

High to Output High Z

Address Hold Time after Address Hold Time (Erase) TAHE 2.0 - -

Setup Time

Note: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP.

High

TPWP 95 100 105 TPWE 95 100 105 mS

TOES 2.0 - TOEV - - 150 nS TDFP 0 - 130 nS TAH 0 - -

TCES 2.0 - -

µS µS µS µS

µS µS

µS µS µS

Publication Release Date: December 1997

- 7 - Revision A1

TIMING WAVEFORMS

V

AC Read Waveform

V

IH

Address Address Valid

V

IL

V

IH

CE

IL

IH

OE

V

IL

Outputs

High Z

Preliminary W27E020

T

CE

T

DF

T

ACC

OE

Valid Output

T

OH

High Z

Erase Waveform

V

Data

V

PGM

IH

V

IL

14.0V

5.0V

PP

V

IH

CE

V

IL

V

IH

OE

V

IL

Address

Read

Manufacturer

SID

A9 = 12.0V

Others = V

A0 = V

T

AS

DA 01

T

CE

T

OE

IL

T

OE

Device

IL

A0=V

Others=V

T

AS

Read

SID

Chip Erase

A9 = 14.0V

Others = V

IH

IL

T

AS

AHC

Data All One

T

DS

Erase Verify

IL

Address Stable

T

DFP

T

DH

Address

Stable

D

OUT D

T

AH

D

OUT

Blank Check Read Verify

Address Stable

T

ACC

OUT

5V

T

VPS

T

OES

T

CES

PWE

OEV

T

OE

- 8 -

Timing Waveforms, continued

Programming Waveform

Preliminary W27E020

Address

Data

V

CE

OE

PGM

PP

12.0V

5.0V

Program

V

IH

T

AS

T

VPS

T

CES

Address Stable

Data In Stable

DS

T

PWP

V

IL

V

IH

V

IL

V

IH

V

IL

V

IH

V

IL

Program

Verify

Address Stable

T

DFP

D

OUT

T

DH

T

OES

T

AH

T

OEV

D

OUT

Read Verify

Address Valid

T

ACC

T

OE

D

OUT

5V

Publication Release Date: December 1997

- 9 - Revision A1

SMART PROGRAMMING ALGORITHM

Start

Address = First Location

Vcc = 5V Vpp = 12V

X = 0

Preliminary W27E020

Increment Address

Program One 100 S Pulse

Increment X

X = 25?

Fail

No

Verify

One Byte

Last Address?

Vcc = 5V

Vpp = 5V

Compare All Bytes to

Original Data

µ

Yes

No

Pass

Yes

Fail

Verify

One Byte

Pass

Fail

Pass Device

Pass

Fail Device

- 10 -

SMART ERASE ALGORITHM

Preliminary W27E020

Start

X = 0

Vcc = 5V

Vpp = 14V

Increment

Address

A9 = 14V; A0 = V

Chip Erase 100 mS Pulse

Address = First Location

Increment X

Erase Verify

No

Last Address?

Vcc = 5V

Vpp = 5V

IL

Fail

Pass

Yes

No

X = 20?

Yes

Compare All Bytes to

FFs (HEX)

Pass

Pass Device

Fail

Fail Device

Publication Release Date: December 1997

- 11 - Revision A1

ORDERING INFORMATION

Preliminary W27E020

PART NO. ACCESS

TIME

(nS)

W27E020-70 70 30 100 600 mil DIP W27E020-90 90 30 100 600 mil DIP W27E020-12 120 30 100 600 mil DIP W27E020P-70 70 30 100 32-pin PLCC W27E020P-90 90 30 100 32-pin PLCC W27E020P-12 120 30 100 32-pin PLCC

Notes:

1. Winbond reserves the right to make changes to its products without prior notice.

2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure.

POWER SUPPLY

CURRENT MAX.

(mA)

STANDBY VCC

CURRENT MAX.

(µA)

PACKAGE

- 12 -

PACKAGE DIMENSIONS

1

1. Dimensions D Max. & S include mold flash or

2. Dimension E1 does not include interlead flash.

3. Dimensions D & E1 include mold mismatch and

6. General appearance spec. should be based on

2. Dimension b does not include dambar protrusion/intrusion.

32-pin P-DIP

32

1E

1 16

S

2

A

L

D

B

e

1B

Preliminary W27E020

Dimension in Inches Dimension in mm

Symbol

Min. Nom. Max.

A A

1

A

2

B

1

B c D

17

E E1 e

1

L

a

e

A

S

0.210 5.33

0.010

0.150

0.155

0.160

0.016

0.018

0.022

0.050 1.27

0.0540.048

0.010

0.014

0.008

1.650 1.660

0.6000.590 0.610

0.540

0.5550.550

0.110

0.120

0.130

0.140

0 15

0.670

0.6500.630 16.00 16.51

0.085 2.16

Notes:

tie bar burrs.

c

are determined at the mold parting line.

4. Dimension B1 does not include dambar protrusion/intrusion.

5. Controlling dimension: Inches. final visual inspection spec.

1

A

Base Plane

Seating Plane

E

eA

a

Min.

0.25

3.81

3.94

0.41

0.46

0.20

0.25

41.91

15.2414.99

13.84 14.1013.97

2.29 2.54 2.790.090 0.100

3.05

3.30

Max.Nom.

4.06

0.56

0.36

42.16

15.49

17.02

1.371.22

3.56 150

32-Lead PLCC

4

5

13

14 20

L

θ

Seating Plane

H

E

1

30

32

29

D

H

21

G

c

Dimension in Inches

Symbol

Min. Nom. Max. Max.Nom.Min.

A

0.020

A

1

A

2 1

b

0.016

b

0.008

c

0.547

D

0.447

E

e

0.490

D

G

E

0.390

G

0.585

D

H

0.485

HE

0.075

L

y

θ

0.028

0.018

0.010

0.550

0.450

0.050

0.510

0.410

0.590

0.490

0.090

°

0

0.140

0.1150.105 0.110

0.66 0.81

0.0320.026

0.41

0.022

0.20

0.014

13.89

0.553

11.35

0.453

1.12 1.420.044 0.056

12.45 12.95 13.460.530

0.430

14.86

0.595

12.32

0.495

1.91 2.29

0.095

0.004

°

10

Dimension in mm

0.50

2.802.67 2.93

0.71

0.46

0.25

13.97

11.43

1.27

9.91

10.41

14.99

12.45

°

0

3.56

0.56

0.35

14.05

11.51

10.92

15.11

12.57

2.41

0.10

°

10

Notes:

2

A

e

b b

1

G

E

1

A

y

1. Dimensions D & E do not include interlead flash.

3. Controlling dimension: Inches.

4. General appearance spec. should be based on

visual inspection sepc.

final

Publication Release Date: December 1997

- 13 - Revision A1

Preliminary W27E020

VERSION HISTORY

VERSION DATE PAGE DESCRIPTION

A1 Dec. 1997 Initial Issued

Headquarters

No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5796096 http://www.winbond.com.tw/ Voice & Fax-on-demand: 886-2-7197006

Winbond Electronics (H.K.) Ltd.

Rm. 803, World Trade Square, Tower II, 123 Hoi Bun Rd., Kwun Tong, Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064

Taipei Office

11F, No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-7190505 FAX: 886-2-7197502

Note: All data and specifications are subject to change without notice.

- 14 -

Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab.

2727 N. First Street, San Jose, CA 95134, U.S.A. TEL: 408-9436666 FAX: 408-5441798