Datasheet W27C520W-90, W27C520W-70, W27C520S-90, W27C520S-70 Datasheet (Winbond Electronics)

Preliminary W27C520

OE

64K × 8 ELECTRICALLY ERASABLE EPROM

GENERAL DESCRIPTION

The W27C520 is a high speed, low power Electrically Erasable and Programmable Read Only Memory organized as 65,536 × 8 bits. It includes latches for the lower 8 address lines to multiplex with the 8 data lines. To cooperate with the MCU, this device could save the external TTL component, also cost and space. It requires only one supply in the range of 3.0V to 3.6V or 4.5V to 5.5V in normal read mode. The W27C520 provides an electrical chip erase function. It will be a great convenient when you need to change/update the contents in the device.

FEATURES

• High speed access time: 70/90 nS (max.)

• Read operating current: 8/20 mA (max.)

• Erase/Programming operating current

30 mA (max.)

• Standby current: 20/100 µA (max.)

• Unregulated battery power supply range,

3.0V to 3.6V and 4.5V to 5.5V

• +13V erase and programming voltage

• High Reliability CMOS Technology

− 2K V ESD Protection

− 200 mA Latchup Immunity

• Fully static operation

• All inputs and outputs directly LVTTL/CMOS

compatible

• Three-state outputs

• Available packages: 20-pin TSSOP and 20-pin

SOP

PIN CONFIGURATIONS

1

A10

2

A12

3

A14

4

ALE

5

V

OE/VPP

A15 A13 A11

A9

OE/VPP

A15

A13

A11

A9

AD0

AD2 AD4 AD6

GND

DD

6 7 8 9 10

1 2 3 4 5 6 7 8 9 10

TSSOP

Top View

SOP

Top View

BLOCK DIAGRAM

20

A8 AD1

19

AD3

18

AD5

17

AD7

16

GND

15 14

AD6

13

AD4

12

AD2 AD0

11

VDD

20

ALE

19

A14

18

A12

17

A10

16

A8

15

AD1

14 13

AD3 AD5

12

AD7

11

PIN DESCRIPTION

SYMBOL DESCRIPTION

AD0−AD7

A8−A15

ALE Address Latch Enable

VDD Power Supply

GND Ground

OE / V

AD7 - AD0

A15 - A8

/VPP

ALE

V

GND

CONTROL

PP

L A T C H E S

DECODER

DD

OUTPUT BUFFER

MEMORY

ARRAY

Address/Data Inputs/Outputs Address Inputs

Output Enable, Program/Erase Supply Voltage

Publication Release Date: October 2000

- 1 - Revision A1

Preliminary W27C520

OE

FUNCTIONAL DESCRIPTION

Read Mode

Unlike conventional UVEPROMs, which has CE and OE two control functions, the W27C520 has one OE/VPP and one ALE (address_latch_enable) control functions. The ALE makes lower

address A[7:0] to be latched in the chip when it goes from high to low, so that the same bus can be used to output data during read mode. i.e. lower address A[7:0] and data bus DQ[7:0] are multiplexed.

/VPP controls the output buffer to gate data to the output pins. When addresses are stable, the

address access time (TACC) is equal to the delay from ALE to output (TCE), and data are available at the outputs TOE after the falling edge of OE/VPP, if TACC and TCE timings are met.

Erase Mode

The erase operation is the only way to change data from "0" to "1." Unlike conventional UVEPROMs, which use ultraviolet light to erase the contents of the entire chip (a procedure that requires up to half an hour), the W27C520 uses electrical erasure. Generally, the chip can be erased within 100 mS by using an EPROM writer with a special erase algorithm.

There are two ways to enter Erase mode. One is to raise OE/VPP to VPE (13V), VDD = VDE (6.5V), A9 = VHH (13V), A10 = high A8&A11 = low, and all other address pins include AD[7:0] keep at fixed low or high. Pulsing ALE high starts the erase operation. The other way is somewhat like flash, by programming two consecutive commands into the device and then enter Erase mode. The two commands are loading Data = AA(hex) to Addr. = 5555(hex) and Data = 10(hex) to Addr. = 2AAA(hex). Be careful to note that the ALE pulse widths of these two commands are different: One is 50 µS, while the other is 100 mS. Please refer to the Smart Erase Algorithm 1 & 2.

Erase Verify Mode

The device will enter the Erase Verify Mode automatically after Erase Mode. Only power down the device can force the device enter Normal Read Mode again.

Program Mode

Programming is the only way to change cell data from "1" to "0." The program mode is entered when

/VPP is raised to VPP (13V), VDD = VDP (6.5V), the address pins equal the desired addresses, and

the input pins equal the desired inputs. Pulsing ALE high starts the programming operation.

Program Verify Mode

The device will enter the Program Verify Mode automatically after Program Mode. Only power down the device can force the device enter Normal Read Mode again.

Erase/Program Inhibit

Erase or program inhibit mode allows parallel erasing or programming of multiple chips with different data. When ALE low, erasing or programming of non-target chips is inhibited, so that except for the

ALE and OE/VPP pins, the W27C520 may have common inputs.

Standby Mode

The standby mode significantly reduces VDD current. This mode is entered when ALE and OE/VPP keep high. In standby mode, all outputs are in a high impedance state.

- 2 -

OE

Preliminary W27C520

System Considerations

An EPROM's power switching characteristics require careful device decoupling. System designers are interested in three supply current issues: standby current levels (ISB), active current levels (IDD), and transient current peaks produced by the falling and rising edges of ALE Transient current magnitudes depend on the device output's capacitive and inductive loading. Proper decoupling capacitor selection will suppress transient voltage peaks. Each device should have a

0.1 µF ceramic capacitor connected between its VDD and GND. This high frequency, low inherentinductance capacitor should be placed as close as possible to the device. Additionally, for every eight devices, a 4.7 µF electrolytic capacitor should be placed at the array's power supply connection between VDD and GND. The bulk capacitor will overcome voltage slumps caused by PC board trace inductances.

TABLE OF OPERATING MODES

(VPP = 13V, VPE = 13V, VHH = 12V, VDP = 6.5V, VDE = 6.5V, VDD = 3.3V or 5.0V, VDI = 5.0V, X = VIH or VIL)

MODE PIN

Address Latch Enable VIH VIH AIN VDD A[7:0] Read VIL VIL AIN VDD DOUT Output Disable VIL/

Standby VIH VIH X VDD A[7:0] Program VIH VPP AIN VDP DIN Erase 1 VIH VPE A8&A11 = VIL, A9 = VPE,

Erase 2 VIH VPE First command:

Second command:

Product Identifiermanufacturer

Product Identifier-device VIL VIL A8 = VIH, A9 = VHH, Others = X VDI 1F(Hex)

ALE

VIH

VIL VIL A8 = VIL, A9 = VHH, Others = X VDI DA(Hex)

/VPP

VIH X VDD High Z

OTHER ADDRESS VDD AD[7:0]

VDE X

A10 = VIH, Others = X

VDE AA(hex)

Addr. = 5555 (hex)

VDE 10(hex)

Addr. = 2AAA (hex)

Publication Release Date: October 2000

- 3 - Revision A1

Preliminary W27C520

OE

DC CHARACTERISTICS

Absolute Maximum Ratings

PARAMETER RATING UNIT

Ambient Temperature with Power Applied -55 to +125 Storage Temperature -65 to +150 Voltage on all Pins with Respect to Ground Except

/VPP, A9 and VDD Pins

Voltage on OE/VPP Pin with Respect to Ground Voltage on A9 Pin with Respect to Ground -2.0 to +7.0 V Voltage VDD Pin with Respect to Ground -2.0 to +14.0 V

Notes:

1. Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device.

2. Minimum voltage is -0.6V DC which may undershoot to -2.0V for pulses of less than 20 nS. Maximum output pin voltage is VDD +0.75V DC which may overshoot to +7.0V for pulses of less than 20 nS.

-2.0 to +7.0 V

DC Erase Characteristics

(TA = 25° C ±5° C, VDD = 6.5V ±0.25V)

°C °C

PARAMETER SYM.

Input Load Current ILI VIN = VIL or VIH -10 - 10 VDD Erase Current ICP

VPP Erase Current IPP

Input Low Voltage VIL - -0.3 - 0.8 V Input High Voltage VIH - 2.4 - VDD+0.3 Output Low Voltage

(Verify) Output High Voltage

(Verify) A9 SID Voltage

A9 Erase Voltage VPE - 12.75 13 13.25 V VPP Erase Voltage VPE - 12.75 13 13.25 V VDD Supply Voltage

(Erase & Erase Verify)

Note: VDD must be applied simultaneously or before VPP and removed simultaneously or after VPP.

VOL IOL = 2.1 mA - - 0.45 V

VOH

VHH

VDE - 6.25 6.5 6.75 V

CONDITIONS LIMITS UNIT

ALE = VIH, OE/VPP = VPE A8 & A11 = VIL, A9 = VPE, A10 = VIH, Others = X

IOH = -0.4 mA 2.4 - - -

VDD = 5V ±10%

MIN. TYP. MAX.

- - 30 mA

11.5 12 12.5 V

µA

V

- 4 -

Preliminary W27C520

Input

CAPACITANCE

(VDD = 3.0V to 3.6V or 4.5V to 5.5V, TA = 25° C, f = 1 MHz)

PARAMETER SYMBOL MAX. UNIT

Input Capacitance CIN VIN = 0V 6 pF Output Capacitance COUT VOUT = 0V 12 pF

AC CHARACTERISTICS

AC Test Conditions

PARAMETER CONDITIONS

Input Pulse Levels 0V/3V Input Rise and Fall Times 10 nS Input and Output Timing Reference Level 1.5V/1.5V Output Load CL = 100 pF, IOH/IOL = -0.4 mA/2.1 mA

AC Test Load and Waveforms

D

OUT

3V

0V

+1.3V

(IN914)

3.3K ohm

100 pF (Including Jig and Scope)

Output

Test Points Test Points

1.5V

Publication Release Date: October 2000

- 5 - Revision A1

READ OPERATION DC CHARACTERISTICS

0.3V,

OE

(VDD = 3.0V to 3.6V or 4.5V to 5.5V, TA = 0 to 70° C)

Preliminary W27C520

PARAMETER SYM.

CONDITIONS LIMITS UNIT

MIN. TYP. MAX.

Input Load Current ILI VIN = 0V to VDD -5 - 5 Output Leakage Current ILO VOUT = 0V to VDD -5 - 5

VDD = 3.0V to

3.6V VDD = 4.5V to

5.5V

VDD = 3.0V to

3.6V VDD = 4.5V to

5.5V

(CMOS input)

ISB

Input Low Voltage VIL - -0.6

ALE = VDD ±

/VPP = VDD ±0.3V All others inputs = GND/ VDD ±0.3V

ALE = VIL, IOUT = 0 mA f = 5 MHz

- - 20 Standby VDD Current

- 100

- - 8 VDD Operating Current IDD

- - 20

- 0.8 V

Input High Voltage VIH - 2.0 - VDD

Output Low Voltage VOL IOL = 2.1 mA - - 0.4 V Output High Voltage VOH IOH = -0.4 mA 2.4 - - V

READ OPERATION AC CHARACTERISTICS

µA µA µA

mA

V

+0.3

(VDD = 3.0V to 3.6V or 4.5V to 5.5V, TA = 0 to 70° C)

PARAMETER SYM. W27C520-70 W27C520-90 UNIT

MIN. MAX. MIN. MAX.

Address Latch Enable Access Time TCE - 70 - 90 nS Address Latch Enable Width TALE 45 - 45 - nS Address Access Time TACC - 70 - 90 nS Address Setup Time TAS 15 - 15 - nS Address Hold Time TAH 15 - 15 - nS Output Enable Access Time TOE - 35 - 35 nS

OE /VPP High to High-Z Output

TDF - 25 - 25 nS

Output Hold from Address Change TOH 0 - 0 - nS

Note: VDD must be applied simultaneously or before VPP and removed simultaneously or after VPP.

- 6 -

Preliminary W27C520

DC PROGRAMMING CHARACTERISTICS

(VDD = 6.5V ±0.25V, TA = 25° C ±5° C)

PARAMETER SYM.

Input Load Current ILI VIN = VIL or VIH -10 - 10 VDD Program Current ICP ALE = VIH,

VPP Program Current IPP ALE = VIH,

Input Low Voltage VIL - -0.3 - 0.8 V Input High Voltage VIH - 2.4 - VDD +0.5 Output Low Voltage (Verify) VOL IOL = 2.1 mA - - 0.45 V Output High Voltage (Verify) VOH IOH = -0.4 mA 2.4 - - V A9 Silicon I.D. Voltage VHH VPP Program Voltage VPP - 12.75 13.0 VDD Supply Voltage (Program) VDP - 6.25 6.5 6.75 V

AC PROGRAMMING/ERASE CHARACTERISTICS

(VDD = 6.5V ±0.25V, TA = 25° C ±5° C)

PARAMETER SYM. LIMITS UNIT

OE /VPP Pulse Rise Time Address Latch Enable Width TALE 500 - - nS ALE Program Pulse Width TPPW 47.5 50 52.5

ALE Erase Pulse Width TEPW 95 100 105 mS ALE Erase Pulse Width 1 TEPW1 47.5 50 52.5 ALE Erase Pulse Width 2 TEPW2 95 100 105 mS Latched Address Setup Time TLAS 100 - - nS Latched Address Hold Time TLAH 100 - - nS Address Setup Time TAS 2.0 - Address Hold Time TAH 0 - -

OE /VPP Setup Time

OE /VPP Hold Time Data Setup Time TDS 2.0 - -

Data Hold Time TDH 2.0 - Data Valid from OE/VPP Low during Erase Verify

Data Valid from OE /VPP Low during Program Verify

OE /VPP High to Output High Z

OE /VPP High Voltage Delay After ALE Low

OE /VPP Recovery Time

Note: VDD must be applied simultaneously or before VPP and removed simultaneously or after VPP.

CONDITIONS LIMITS UNIT

MIN. TYP. MAX.

- - 30 mA

OE /VPP = VPP

- - 30 mA

/VPP = VPP

OE

VDD = 5V ±10%

TPRT 50 - - nS

TOES 2.0 - TOEH 2.0 - -

TEOE - - 150 nS TPOE - - 150 nS TDFP 0 - 130 nS

TVS 2.0 - TVR 2.0 - -

11.5 12.0

MIN. TYP. MAX.

12.5 V

13.25 V

µA

V

µS

µS µS µS

µS µS

Publication Release Date: October 2000

- 7 - Revision A1

TIMING WAVEFORMS

AC Read Waveform

V

ALE

IH

V

IL

V

IH

V

IL

V

IH

V

IL

High Z

A8-A15

OE/Vpp

AD0-AD7

T

ALE

AS

T

Address

Preliminary W27C520

Address Valid

CE

T

TOE

AH

T

Data

ACC

T

DF

T

OH

T

High Z

Programming Waveform

V

A[15:8]

OE/Vpp

ALE

AD[7:0]

V

13V

V

V V

IH

IL

T

RPT

IH

IL

IH

IL

IH

IL

T

VS

ALE

T

LAS

Add

PROGRAM PROGRAM (VERIFY)

T

AS

T

Address Stable

T

OES

T

OEH

T

VR

T

PPW

T

LAH

DS

DH

Data in

ALE

Add

T

POE

T

DFP

Data out

AH

- 8 -

Timing Waveforms, continued

Erase Waveform 1

Preliminary W27C520

V

IH

A[15:8]

V

IL

V

AD[7:0]

IH

V

IL

13.0V

V

ALE

IH

V

IL

V

IH

V

IL

OE/Vpp

Erase Waveform 2

Read Company SID

Others=V

A8=VIL

A[15:8]

OE/Vpp

V V

13.0V V

V

IH

IL

IH IL

DD

V =5.0V A9=12.0

V

IL

Read Company SID

V = 3.3 or 5.0V

DD

Read Device SID

Chip Erase Erase (Verify)

A9 = 12.0V A9 = 13.0V

IH

1F

T

AST

PRT

T

OES

A[15:8] = 55

T

OES

Others = VILor V A8, A11 = V

A10 = V

Chip Erase

A8 = V

Read Device SID

or V

A8=V

Others = V

IL

DA

IH

T

PRT

IL

or V

A8 = V

Command 1 Command 2

V =6.5V

DD

T

RPT

VS

T

DD

V = 6.5V

IL

IH

T

EPW

OEH

T

IH

T

OEH

V =6.5V

DD

A[15:8] = 2A

DD

V = 6.5V

Address Valid

Add

T

VR

D

OUT

T

EOE

Erase Verify

V =6.5V

DD

Address Valid

T

ALE

AD[7:0]

V

IH

V

IL

V

IH

V

IL

DA

T

OES

ALE

T

LAS

T

55 AA

1F D

LAH

EPW1

T

EPW2

T

DS

DH

AA

10

Add

EOE

OUT

Note: First command Address = 5555(hex) with Data = AA(hex) Second command Address = 2AAA(hex) with Data = 10(hex)

Publication Release Date: October 2000

- 9 - Revision A1

SMART PROGRAMMING ALGORITHM 1

Start

Address = First Location

V = 6.5V

DD

OE/Vpp = 13V

Preliminary W27C520

Increment Address

Increment

Address

Last

Address ?

Power

Down

No

Yes

No

Pass

Program One 50 S Pulse

Address = First Location

Program One 50 S Pulse

V = 3.3 or 5.0V

DD

OE/Vpp = V

µ

Last

Address ?

Yes

X = 0

Verify

Byte

µ

IL

Fail

No

Increment X

X = 25 ?

Yes

Compare

All Bytes to

Original

Data

Pass

Device Passed

- 10 -

Fail

Device

Failed

SMART PROGRAMMING ALGORITHM 2

Start

Address = First Location

V = 6.5V

DD

X = 0

Preliminary W27C520

Increment Address

Fail

Program One 50 S Pulse

OE/Vpp = 13V

µ

Increment X

X = 25?

No

Verify One Byte OE/Vpp = V

IL

Pass

No

Last Address ?

Yes

Power Down

V =3.3or5.0V

DD

Compare

All Bytes to

Original

Data

Yes

Verify One Byte

OE/Vpp = V

Fail

IL

Pass

Device Passed

Device Failed

Publication Release Date: October 2000

- 11 - Revision A1

SMART ERASE ALGORITHM 1

OE/Vpp = 13V

Start

X = 0

V = 6.5V

DD

Preliminary W27C520

Increment

Address

A9 = 13V; A8&A11 = V A10 = V

Chip Erase 100 mS Pulse

Address = First Location

Increment X

V = 6.5VDD

OE/Vpp = V

No

Address?

IH

IL

Erase

Verify

Pass

Last

Yes

Power Down

IL

No

Fail

X = 20?

Yes

V = 3.3 or 5.0V

DD

OE/Vpp = V

Compare

All Bytes to

FFs (HEX)

Pass Device

IL

Pass

- 12 -

Fail

Fail Device

SMART ERASE ALGORITHM 2

OE/Vpp = 13V

Start

X = 0

V = 6.5V

DD

Preliminary W27C520

Increment

Address

Program One 50 S Pulse

with Address = 5555(Hex) Data = AA(Hex)

Program One 100 mS Pulse

with Address = 2AAA(Hex) Data = 10(Hex)

OE/Vpp = V

No

V = 3.3 or 5.0V

DD

OE/Vpp = V

µ

Increment X

V = 6.5V

DD

Erase

Verify

Pass

Last

Address?

Yes

Power

Down

IL

Fail

No

X = 20?

Yes

Compare All Bytes to FFs (HEX)

Pass

Device

Fail

Device

Publication Release Date: October 2000

- 13 - Revision A1

ORDERING INFORMATION

Preliminary W27C520

PART NO. ACCESS

TIME

(nS)

W27C520W-70* 70 8/20 20/100 173mil TSSOP W27C520W-90* 90 8/20 20/100 173mil TSSOP W27C520S-70* 70 8/20 20/100 300mil SOP W27C520S-90* 90 8/20 20/100 300mil SOP

Notes:

1. The Part No is preliminary and might be changed after project is consoled.

2. Winbond reserves the right to make changes to its products without prior notice.

3. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure.

OPERATING

CURRENT

MAX. (mA)

STANDBY CURRENT

MAX. (µA)

PACKAGE

- 14 -

PACKAGE DIMENSIONS

θ

20-pin TSSOP

Preliminary W27C520

20-pin SOP

c

L

b

Dimension in Inches

Symbol

Min. Nom. Max.

A

0.002

1

A

E

1

E

L D

0.246

E

0.169 0.176

1

e

D

A

1

A

c

L

E

0.007

b

0.003 0.007

c e

0

θ

0.65 BSC

Dimension in mm

Min. Nom. Max.

0.043

0.05

0.006

0.50

6.40

0.256

6.25

4.30

0.18

0.012

0.09

0.256 BSC

8 0 8

1.10

0.15

0.700.0280.020

6.600.2600.252

6.50

4.48

0.30

0.18

b

Dimension in Inches

Symbol

Min. Nom. Max.

0.092 2.34

A

0.003

1

A

E

1

L D

0.393

E

0.291 0.299

1

e

D

A

1

A

E

0.013

b

0.009 0.013

c

e

0

θ

0.50 BSC

Dimension in mm

Min. Nom. Max.

0.105

0.076

0.012

0.381

12.6

0.420

9.98

7.39

0.330

0.020

0.229

1.27 BSC

8 0 8

2.67

0.305

0.8890.0350.015

13.00.5130.497

10.7

7.60

0.508

0.330

Publication Release Date: October 2000

- 15 - Revision A1

VERSION HISTORY

Winbond Electronics North America Corp.

Preliminary W27C520

VERSION

DATE PAGE DESCRIPTION

A1 Oct. 2000 - Initial Issued

Headquarters

No. 4, Creation Rd. III,

No. 4, Creation Rd. III, Science-Based Industrial Park,

Science-Based Industrial Park, Hsinchu, Taiwan

Hsinchu, Taiwan TEL: 886-3-5770066

TEL: 886-3-5770066 FAX: 886-3-5796096

FAX: 886-3-5796096 http://www.winbond.com.tw/

http://www.winbond.com.tw/ Voice & Fax-on-demand: 886-2-27197006

Voice & Fax-on-demand: 886-2-27197006

Taipei Office

11F, No. 115, Sec. 3, Min-Sheng East Rd.,

11F, No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan

Taipei, Taiwan TEL: 886-2-27190505

TEL: 886-2-27190505 FAX: 886-2-27197502

FAX: 886-2-27197502

Note: All data and specifications are subject to change withou t notice.

Winbond Electronics (H.K.) Ltd.

Unit 9-15, 22F, Millennium City,

Unit 9-15, 22F, Millennium City, No. 378 Kwun Tong Rd;

No. 378 Kwun Tong Rd; Kowloon, Hong Kong

Kowloon, Hong Kong TEL: 852-27513100

TEL: 852-27513100 FAX: 852-27552064

FAX: 852-27552064

- 16 -

Winbond Memory Lab.

Winbond Memory Lab. Winbond Microelectronics Corp.

Winbond Microelectronics Corp. Winbond Systems Lab.

Winbond Systems Lab.

2727 N. First Street, San Jose,

2727 N. First Street, San Jose, CA 95134, U.S.A.

CA 95134, U.S.A. TEL: 408-9436666

TEL: 408-9436666 FAX: 408-5441798

FAX: 408-5441798