Datasheet W27C512-70, W27C512-12, W27C512-45, W27C512P-90, W27C512P-45 Datasheet (Winbond Electronics)

W27C512

0

3

CE

OE

64K × 8 ELECTRICALLY ERASABLE EPROM

GENERAL DESCRIPTION

The W27C512 is a high speed, low power Electrically Erasable and Programmable Read Only Memory organized as 65536 × 8 bits that operates on a single 5 volt power supply. The W27C512 provides an electrical chip erase function.

FEATURES

• High speed access time:

45/70/90/120 nS (max.)

• Read operating current: 30 mA (max.)

• Erase/Programming operating current

30 mA (max.)

• Standby current: 1 mA (max.)

• Single 5V power supply

• +14V erase/+12V programming voltage

• Fully static operation

• All inputs and outputs directly TTL/CMOS

compatible

• Three-state outputs

• Available packages: 28-pin 600 mil DIP, 330 mil

32-pin PLCC

PIN CONFIGURATIONS

1

A6 A5

A4 A3 A2 A1 A0 NC Q0

A15 A12

A7 A6 A5 A4 A3 A2 A1

A0 Q0 Q1 Q2

GND

A7N

4 3 2 1 5 6

7 8 9 10 11 12

1

13

4

Q1Q

2 3 4 5 6 7 8 9 10 11 12 13 14

A 1 2

151

2

28-pin

A 1 5

32-pin PLCC

6

G N D

DIP

C

1 7

N C

A

V

1

C

4

C

323

1

18192

Q

4

28 27 26 25 24 23 22 21 20 19 18 17 16 15

A 1 3

3

0

Q 5

29 28 27 26 25 24 23 22 21

V

CC

A14 A13 A8 A9 A11

OE/Vpp A10

CE Q7

Q6 Q5 Q4 Q3

A8 A9 A11 NC

OE/Vpp A10

CE Q7 Q6

BLOCK DIAGRAM

Q0

. .

Q7

OE/V

CE

PP

A0

.

A15

V

CC

GND

CONTROL

DECODER

OUTPUT BUFFER

CORE

ARRAY

PIN DESCRIPTION

SYMBOL DESCRIPTION

A0−A15

Q0−Q7

/VPP

VCC Power Supply

GND Ground

NC No Connection

Address Inputs Data Inputs/Outputs Chip Enable Output Enable, Program/Erase

Supply Voltage

Publication Release Date: November 1999

- 1 - Revision A4

W27C512

CE

FUNCTIONAL DESCRIPTION

Read Mode

Like conventional UVEPROMs, the W27C512 has two control functions, both of which produce data at the outputs. CE is for power control and chip select. OE/VPP controls the output buffer to gate data

to the output pins. When addresses are stable, the address access time (T from CE to output (TCE), and data are available at the outputs TOE after the falling edge of OE/VPP,

ACC

if T

and TCE timings are met.

Erase Mode

The erase operation is the only way to change data from "0" to "1." Unlike conventional UVEPROMs, which use ultraviolet light to erase the contents of the entire chip (a procedure that requires up to half an hour), the W27C512 uses electrical erasure. Generally, the chip can be erased within 100 mS by using an EPROM writer with a special erase algorithm.

Erase mode is entered when OE/VPP is raised to VPE (14V), VCC = VCE (5V), A9 = VPE (14V), A0 low, and all other address pins low and data input pins high. Pulsing CE low starts the erase

operation.

Erase Verify Mode

After an erase operation, all of the bytes in the chip must be verified to check whether they have been successfully erased to "1" or not. The erase verify mode ensures a substantial erase margin if VCC =

VCE (3.75V), CE low, and OE/VPP low.

ACC

) is equal to the delay

Program Mode

Programming is performed exactly as it is in conventional UVEPROMs, and programming is the only way to change cell data from "1" to "0." The program mode is entered when OE/VPP is raised to VPP

(12V), VCC = VCP (5V), the address pins equal the desired addresses, and the input pins equal the desired inputs. Pulsing CE low starts the programming operation.

Program Verify Mode

All of the bytes in the chip must be verified to check whether they have been successfully programmed with the desired data or not. Hence, after each byte is programmed, a program verify operation should be performed. The program verify mode automatically ensures a substantial

program margin. This mode will be entered after the program operation if OE/VPP low and CE low.

Erase/Program Inhibit

Erase or program inhibit mode allows parallel erasing or programming of multiple chips with different data. When CE high, erasing or programming of non-target chips is inhibited, so that except for the

and OE/VPP pins, the W27C512 may have common inputs.

- 2 -

W27C512

CE OE

Standby Mode

The standby mode significantly reduces VCC current. This mode is entered when CE high. In standby mode, all outputs are in a high impedance state, independent of OE/VPP.

Two-line Output Control

Since EPROMs are often used in large memory arrays, the W27C512 provides two control inputs for multiple memory connections. Two-line control provides for lowest possible memory power dissipation and ensures that data bus contention will not occur.

System Considerations

An EPROM's power switching characteristics require careful device decoupling. System designers are interested in three supply current issues: standby current levels (ISB), active current levels (ICC), and

transient current peaks produced by the falling and rising edges of CE. Transient current magnitudes depend on the device output's capacitive and inductive loading. Two-line control and proper decoupling capacitor selection will suppress transient voltage peaks. Each device should have a 0.1 µ F ceramic capacitor connected between its VCC and GND. This high frequency, low inherentinductance capacitor should be placed as close as possible to the device. Additionally, for every eight devices, a 4.7 µF electrolytic capacitor should be placed at the array's power supply connection between VCC and GND. The bulk capacitor will overcome voltage slumps caused by PC board trace inductances.

TABLE OF OPERATING MODES

(VPP = 12V, VPE = 14V, VHH = 12V, VCP = 5V, VCE = 5V, X = VIH or VIL)

MODE PINS

Read VIL VIL X X VCC D Output Disable VIL VIH X X VCC High Z Standby (TTL) VIH X X X VCC High Z Standby (CMOS) Program VIL VPP X X VCP DIN Program Verify VIL VIL X X VCC D Program Inhibit VIH VPP X X VCP High Z Erase VIL VPE VIL VPE VCE DIH Erase Verify VIL VIL X X 3.75 D Erase Inhibit VIH VPE X X VCE High Z Product Identifier-manufacturer VIL VIL VIL VHH VCC DA (Hex) Product Identifier-device VIL VIL VIH VHH VCC 08 (Hex)

VCC ±0.3V

/VPP

X X X VCC High Z

A0 A9 VCC OUTPUTS

OUT

Publication Release Date: November 1999

- 3 - Revision A4

DC CHARACTERISTICS

CE

OE

Absolute Maximum Ratings

PARAMETER RATING UNIT

W27C512

Operation Temperature 0 to +70 Storage Temperature -65 to +125

Voltage on all Pins with Respect to Ground Except OE/V A9 and VCC Pins

Voltage on OE/VPP Pin with Respect to Ground Voltage on A9 Pin with Respect to Ground -0.5 to +14.5 V Voltage VCC Pin with Respect to Ground -0.5 to +7 V

Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device.

PP,

-0.5 to VCC +0.5 V

-0.5 to +14.5 V

°

C

°

C

DC Erase Characteristics

(TA = 25° C ±5° C, VCC = 5.0V ±5%)

PARAMETER SYM.

Input Load Current ILI VIN = VIL or VIH -10 - 10 VCC Erase Current ICP VPP Erase Current IPP

Input Low Voltage VIL - -0.3 - 0.8 V Input High Voltage VIH - 2.4 - 5.5 V Output Low Voltage (Verify) VOL IOL = 2.1 mA - - 0.45 V Output High Voltage (Verify) VOH IOH = -0.4 mA 2.4 - - A9 Erase Voltage VID - 13.75 14 14.25 V VPP Erase Voltage VPE - 13.75 14 14.25 V VCC Supply Voltage (Erase) VCE - 4.75 5.0 5.25 V VCC Supply Voltage

(Erase Verify)

Note: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP.

VCE - 3.5 3.75 4.0 V

CONDITIONS LIMITS UNIT

MIN. TYP. MAX.

µ

IL,

= V

OE/VPP = VPE

IL,

= V

/VPP = VPE

- - 30 mA

A

- 4 -

W27C512

100 pF for 90/120 nS (Including Jig and Scope)

CAPACITANCE

(VCC = 5V, TA = 25° C, f = 1 MHz)

PARAMETER SYMBOL CONDITIONS MAX. UNIT

Input Capacitance CIN VIN = 0V 6 pF Output Capacitance C

OUT

V

AC CHARACTERISTICS

AC Test Conditions

PARAMETER CONDITIONS

45/70 nS 90/120 nS

Input Pulse Levels 0 to 3.0V 0.45V to 2.4V Input Rise and Fall Times 5 nS 10 nS Input and Output Timing Reference Level 1.5V/1.5V 0.8V/2.0V Output Load CL = 30 pF,

OUT

= 0V 12 pF

IOH/IOL = -0.4 mA/2.1 mA

CL = 100 pF, IOH/IOL = -0.4 mA/2.1 mA

AC Test Load and Waveforms

D

OUT

For 90/120 nS

For 45/70 nS

2.4V

0.45V

3.0V

0V

Input

+1.3V

(IN914)

3.3K ohm

30 pF for 45/70 nS (Including Jig and Scope)

Output

Test Points Test Points

2.0V

0.8V

Output

Test Point Test Point

1.5V

- 5 - Revision A4

Publication Release Date: November 1999

W27C512

CE

READ OPERATION DC CHARACTERISTICS

(VCC = 5.0V ±5%, TA = 0 to 70° C)

PARAMETER SYM. CONDITIONS LIMITS UNIT

MIN. TYP. MAX. Input Load Current ILI VIN = 0V to VCC -5 - 5 Output Leakage Current ILO V Standby VCC Current

ISB

OUT

= 0V to VCC -10 - 10

= VIH

- - 1.0 mA

µ µ

(TTL input) Standby VCC Current

SB1

I

= VCC ±0.3V

- 5 100

µ

(CMOS input) VCC Operating Current ICC

IL

= V

OUT

I

= 0 mA, f = 5 MHz

- - 30 mA

Input Low Voltage VIL - -0.3 - 0.8 V Input High Voltage VIH - 2.2 - V

CC

+0.5 V Output Low Voltage VOL IOL = 2.1 mA - - 0.45 V Output High Voltage VOH IOH = -0.4 mA 2.4 - - V

A A

A

READ OPERATION AC CHARACTERISTICS

(VCC = 5.0V ±5%, TA = 0 to 70° C)

PARAMETER SYM. W27C512-45 W27C512-70 W27C512-90 W27C512-12 UNIT

Read Cycle Time T Chip Enable Access Time T Address Access Time T Output Enable Access Time T

OE /VPP High to High-Z Output

Output Hold from Address Change T

Note: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP.

T

MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.

RC

45 - 70 - 90 - 120 - nS

CE ACC OE DF

OH

- 45 - 70 - 90 - 120 nS

- 20 - 30 - 40 - 55 nS

- 20 - 30 - 30 - 30 nS

0 - 0 - 0 - 0 - nS

DC PROGRAMMING CHARACTERISTICS

(VCC = 5.0V ±5%, TA = 25° C ±5° C)

PARAMETER SYM.

Input Load Current VCC Program Current I

VPP Program Current

MIN. TYP. MAX.

ILI VIN

CP

PP

I

CONDITIONS LIMITS UNIT

= VIL or VIH

CE

= VIL,

-10 - 10

- - 30 mA

OE/VPP = VPP CE = VIL,

- - 30 mA

OE/VPP = VPP

µA

- 6 -

DC Programming Characteristics, continued

W27C512

PARAMETER SYM.

Input Low Voltage Input High Voltage Output Low Voltage (Verify) Output High Voltage (Verify) A9 Silicon I.D. Voltage VPP Program Voltage VCC Supply Voltage (Program)

MIN. TYP. MAX.

VIL

VIH

VOL

VOH

VID

VPP

VCP

CONDITIONS LIMITS UNIT

- -0.3 - 0.8 V

- 2.4 - 5.5 V

IOL = 2.1 mA - - 0.45 V

IOH = -0.4 mA 2.4 - - V

- 11.5 12.0 12.5 V

- 11.75 12.0 12.25 V

- 4.75 5.0 5.25 V

AC PROGRAMMING/ERASE CHARACTERISTICS

(VCC = 5.0V ±5%, TA = 25° C ±5° C)

PARAMETER SYM. LIMITS UNIT

OE/VPP Pulse Rise Time

Data Setup Time T

CE

Program Pulse Width

CE Erase Pulse Width

Data Hold Time T

OE/VPP Setup Time OE/VPP Hold Time

Data Valid from CE Data Valid from Address Change T

CE High to Output High Z

Address Setup Time T Address Hold Time T

Address Hold Time after CE High (Erase)

OE/VPP Valid after CE High OE/VPP Recovery Time

Address Access Time During Erase Verify (VCC = 3.75V) T Output Enable Access Time during Erase Verify

(VCC = 3.75V)

Note: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP.

MIN. TYP. MAX.

PRT

T

PWP

T

PWE

T

OES

T

OEH

T

DV1

T

DV2 DFP

T

AHC

T

ACV OEV

T

DS

DH

AS AH

VS VR

50 - - nS

2.0 - 95 100 105

µ

S

µ

S

95 100 105 mS

2.0 - -

2.0 - 25 - 1 25 - 1

µS µ

S

µ

S

µS µ

S

0 - 130 nS

2.0 - -

0 - -

2.0 - -

µ

S

µ

S

µ

S

µ

S

µ

S

- - 250 nS

- - 150 nS

Publication Release Date: November 1999

- 7 - Revision A4

TIMING WAVEFORMS

AC Read Waveform

W27C512

Address

VIH VIL

VIH

CE

IL

V VIH

OE/Vpp

IL

V

Outputs

Erase Waveform

IH

Vcc

CE

V V

5V

14.0V

VIH VIL

V

IH

V

IL

OE

T

Address

Data

OE/Vpp

High Z

Read Company SID

A0 = V

TACC

T

CE T

A9 = 12.0V

Others = VIL

I

DA

Others = V

TACC

TOE

Read Device SID

A0 = V

Address

Valid

TCE

DF

T

TACC

TOE

TOH

Valid Output

High Z

Blank Check Read Verify

TACC

D

OUT

T

V

OE

IH

TOEV

=250 nS

D

= 150 nS

Erase Verify

OUT

Always = V

Address Valid Address Valid Address Valid

T

ACV

=250 nS

D

OUT

3.75V

IL

Chip Erase A9 = 14.0V

Others = VIL

IH

IL

T

AS

08

Data All One

T

DS

T

OES

TPRT

VS

TPWE

TAHC

T

OEH

T

Address Valid

T

ACV

DH

T

VCS

IH

V

VR

T

- 8 -

Timing Waveforms, continued

Programming Waveform

W27C512

Address

Data

OE/Vpp

CE

V

IH

V

IH

V

12.0V

V

IH

V

IL

V

IH

V IL

Program Program

Address Stable

IL

T

AS

Data In Stable

T

DS

T

OES

T

PRT

T

PWP

Address Stable

T

AH

T

AS

Data In Stable

T

DS

DH

Address Stable

T

DH

T

OEH

AH

V

IL

T

VR

Verify

Address Valid

T

DV1

V

IL

CE should not be toggled during program verify period

Data

Out

T

OH

T

DV2

T

DFP

Address Valid

T

ACC

T

CE

Read Verify

Data Out

T

OH

OE

Publication Release Date: November 1999

- 9 - Revision A4

SMART PROGRAMMING ALGORITHM 1

Start

Address = First Location

Vcc = 5.0V

OE/Vpp = 12V

W27C512

Increment

Address

Increment

Address

Last

Address?

Yes

No

Pass

Program One 100 S Pulse

Address = First Location

Program One 100 S Pulse

Vcc = 5.0V OE/Vpp = V

µ

Last

Address?

Yes

X = 0

Verify

Byte

µ

IL

Fail

No

Increment X

X = 25 ?

Yes

Compare

All Bytes to

Original

Data

Pass

Device

Passed

- 10 -

Fail

Device

Failed

SMART PROGRAMMING ALGORITHM 2

Start

Address = First Location

Vcc = 5.0V

X = 0

W27C512

Increment

Address

Fail

Program One 100 S Pulse

OE/V = 12V

µ

PP

Increment X

X = 25?

No

Verify One Byte

OE/V = V

IL

PP

Pass

No

Last Address ?

Yes

Compare

All Bytes to

Original

Data

Pass

Device Passed

Yes

Verify One Byte

OE/V = V

PP

Fail

IL

Pass

Fail

Device

Failed

Publication Release Date: November 1999

- 11 - Revision A4

SMART ERASE ALGORITHM

W27C512

Start

X = 0

Vcc = 5V

OE/Vpp = 14V

Increment Address

A9 = 14V; A0 = V

Chip Erase 100 mS Pulse

Address = First Location

Increment X

Vcc = 3.75V

OE/Vpp = V

Erase Verify

No

Last Address?

Vcc = 5V

OE/Vpp = V

IL

Fail

Pass

Yes

IL

No

X = 20 ?

Yes

Compare All Bytes to FFs (HEX)

Pass

Pass Device

- 12 -

Fail

Fail Device

ORDERING INFORMATION

W27C512

PART NO. ACCESS

TIME

(nS)

W27C512-45 45 30 100 600 mil DIP W27C512-70 70 30 100 600 mil DIP W27C512-90 90 30 100 600 mil DIP W27C512-12 120 30 100 600 mil DIP W27C512P-45 45 30 100 32-pin PLCC W27C512P-70 70 30 100 32-pin PLCC W27C512P-90 90 30 100 32-pin PLCC W27C512P-12 120 30 100 32-pin PLCC

Notes:

1. Winbond reserves the right to make changes to its products without prior notice.

2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure.

OPERATING

CURRENT

MAX. (mA)

STANDBY

CURRENT

MAX. (µA)

PACKAGE

Publication Release Date: November 1999

- 13 - Revision A4

PACKAGE DIMENSIONS

3. Dimensions D & E1 include mold mismatch and

28-pin P-DIP

W27C512

28

E

1

S

2

A

L

32-pin PLCC

5

13

14

L

θ

Seating Plane

Dimension in Inches

Symbol

A A A B B c

D

15

D E E e L

S

14

E

1

A

Base Plane Seating Plane

B

e

1

B

1

H

E

1

324

30

29

D

D H

21

20

2A

A

e

b

1b

EG

1

A

y

a

e

A

GD

c

Notes:

1. Dimensions D Max. & S include mold flash or tie bar burrs.

c

2. Dimension E1 does not include interlead flash. are determined at the mold parting line.

4. Dimension B1 does not include dambar protrusion/intrusion.

5. Controlling dimension: Inches.

6. General appearance spec. should be based on final visual inspection spec.

Dimension in Inches

Symbol

Min. Nom. Max. Max.Nom.Min.

A

0.020

A

1

A

2

b

1

0.016

b

0.008

c

0.547

D

0.447

E

e

0.490

G

D

0.390

G

E

0.585

H

D

0.485

H

E

0.075

L

y

0

θ

Notes:

1. Dimension D & E do not include interlead flash.

2. Dimension b does not include dambar protrusion/intrusion.

3. Controlling dimension: Inches.

4. General appearance spec. should be based on final visual inspection spec.

0.010

1

0.150

2

0.016

1

0.008

1

0.120

a

A

e

0.028

0.018

0.010

0.550

0.450

0.050

0.510

0.410

0.590

0.490

0.090

°

Nom.

Min.

0.155

0.018

0.060 1.52

0.010

1.460 1.470

0.6000.590

0.540 0.5500.545

0.130

0 15

0.630

0.650

0.140

0.1150.105 0.110

0.0320.026

0.022

0.014

0.553

0.453

0.530

0.430

0.595

0.495

0.095

0.004

10

Dimension in mm

Max. Max.

Min.

0.210

0.25

0.160

3.81

0.022

0.41

0.0640.058

0.20

0.014

0.610

14.99

13.72 13.9713.84

0.110

2.29 2.54 2.790.090 0.100

3.05

0.140

0.670

16.00 16.51

0.090

Dimension in mm

0.50

2.802.67 2.93

0.66 0.81

0.71

0.41

0.46

0.20

0.25

13.89

13.97

11.35

11.43

1.12 1.420.044 0.056

1.27

12.95

12.45

9.91

10.41

14.86

14.99

12.32

12.45

1.91

2.29

°

0

14.05

11.51

13.46

10.92

15.11

12.57

15.24

3.56

0.56

0.35

Nom.

3.94

0.46

0.25

37.08

3.30

2.41

0.10

10

5.33

4.06

0.56

1.631.47

0.36

37.34

15.49

3.56 150

17.02

2.29

°

- 14 -

VERSION HISTORY

6

W27C512

VERSION

DATE PAGE DESCRIPTION

A1 Mar. 1998 Initial Issued A2 Sep. 1998

4 , 6

Correct Imput High Voltage (VIH) from 2.0 (min) to 2.2 (max) Correct VCC from 5.0 ±10% to 5.0 ±5%

A3 Aug. 1999 1, 5, 6, 13 Add 45 nS bining

2, 3 Modify function description (V

IL

→

V

Low; V

IH

A4 Nov. 1999 6 Typo correction

→

High

IL

and VIH):

Headquarters

No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5796096 http://www.winbond.com.tw/ Voice & Fax-on-demand: 886-2-27197006

Taipei Office

11F, No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-27190505 FAX: 886-2-27197502

Note: All data and specifications are subject to change without notice.

Winbond Electronics (H.K.) Ltd.

Rm. 803, World Trade Square, Tower II, 123 Hoi Bun Rd., Kwun Tong, Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064

Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab.

2727 N. First Street, San Jose, CA 95134, U.S.A. TEL: 408-9436666 FAX: 408-5441798

Publication Release Date: November 1999

- 15 - Revision A4