Datasheet W27C4096T-15, W27C4096T-12, W27C4096P-12, W27C4096P-15, W27C4096-15 Datasheet (Winbond Electronics)

Preliminary W27C4096

CE

OE

256K × 16 ELECTRICALLY ERASABLE EPROM

GENERAL DESCRIPTION

The W27C4096 is a high speed, low power Electrically Erasable and Programmable Read Only
Memory organized as 262144 × 16 bits that operates on a single 5 volt power supply. The W27C4096
provides an electrical chip erase function.

FEATURES

• High speed access time:

120/150 nS (max.)

• Read operating current: 30 mA (max.)

• Erase/Programming operating current

30 mA (max.)

• Standby current: 100 µA (max.)

• Single 5V power supply

• +14V erase/+12V programming voltage

• Fully static operation

• All inputs and outputs directly TTL/CMOS

compatible

• Three-state outputs

• Available packages: 40-pin 600 mil DIP, TSOP

and 44-pin PLCC

PIN CONFIGURATIONS

V

1

PP

2

CE

3

Q15

4

Q14

5

Q13

6

Q12

7

Q11

8

Q10

9

40-pin

Q9

10

DIP

Q8

11

GND

12

Q7

13

Q6

14

Q5

15

Q4

16

Q3

17

Q2

18

Q1

19

Q0

20

OE

/

V

Q

Q

Q

V

C

p

1

1
4

Q2Q

N

C

E

p

5

C

C

456

44123 4041

44-pin
PLCC

232221201918

NCA

Q0/

1

O

0

E

40-pin
TSOP

1
3

7

Q12

8

Q11

9

Q10

10

Q9

11

Q8

12

GND

13

NC

14

Q7

15

Q6

16

Q5
Q4

17

Q
3

1

A9

2

A10

3

A11

4

A12

5

A13

6

A14
A15

7

A16

8
9

A17

10

V

CC

11

V

PP

12

CE

13

Q15

14

Q14

15

Q13

16

Q12

17

Q11

18

Q10

19

Q9

20

Q8

BLOCK DIAGRAM

V

40

DD

39

A17

38

A16

37

A15

36

A14

35

A13

34

A12

33

A11

32

A10

31

A9

30

GND

29

A8

28

A7

27

A6

26

A5

25

A4

24

A3

23

A2

22

A1

21

A0

A

A

A

A

1

1

1

1

4

5

6

7

4243

39

A13

38

A12

37

A11

36

A10

35

A9

34

GND

33

NC

32

A8

31

A7

30

A6

29

A5

2827262524

A2A

A

A

3

1

4

40

GND
A8

39

A7

38

A6

37
36

A5
A4

35

A3

34

A2

33

A1

32

A0

31
30

OE
Q0

29
28

Q1

27

Q2

26

Q3

25

Q4

24

Q5

23

Q6

22

Q7

21

Q8

PIN DESCRIPTION

SYMBOL DESCRIPTION

A0−A17

Q0−Q15

CE

CONTROL

OUTPUT
BUFFER

OE

A0

.

DECODER

.

CORE

ARRAY

A17

V

CC

GND

V

PP

Address Inputs
Data Inputs/Outputs
Chip Enable

Output Enable
VPP Program/Erase Supply Voltage
VCC Power Supply

GND Ground

NC No Connection

Q0

.
.

Q15

Publication Release Date: March 1999

- 1 - Revision A1

Preliminary W27C4096

OE

OE

FUNCTIONAL DESCRIPTION

Read Mode

Like conventional UVEPROMs, the W27C4096 has two control functions, both of which produce data
at the outputs. CE is for power control and chip select. OE controls the output buffer to gate data to

the output pins. When addresses are stable, the address access time (TACC) is equal to the delay
from CE to output (TCE), and data are available at the outputs TOE after the falling edge of OE, if

TACC and TCE timings are met.

Erase Mode

The erase operation is the only way to change data from "0" to "1." Unlike conventional UVEPROMs,
which use ultraviolet light to erase the contents of the entire chip (a procedure that requires up to half
an hour), the W27C4096 uses electrical erasure. Generally, the chip can be erased within 100 mS by
using an EPROM writer with a special erase algorithm.

Erase mode is entered when VPP is raised to VPE (14V), VCC = VCE (5V), CE low, OE high, A9 =
VPE (14V), A0 low, and all other address pins low and data input pins high.

Erase Verify Mode

After an erase operation, all of the words in the chip must be verified to check whether they have
been successfully erased to "1" or not. The erase verify mode automatically ensures a substantial

erase margin. This mode will be entered after the erase operation if VPP = VPE (14V), CE high, and

low.

Program Mode

Programming is performed exactly as it is in conventional UVEPROMs, and programming is the only
way to change cell data from "1" to "0." The program mode is entered when VPP is raised to VPP

(12V), VCC = VCP (5V), CE low, OE high, the address pins equal the desired address, and the input
pins equal the desired inputs.

Program Verify Mode

All of the words in the chip must be verified to check whether they have been successfully
programmed with the desired data or not. Hence, after each word is programmed, a program verify
operation should be performed. The program verify mode automatically ensures a substantial

program margin. This mode will be entered after the program operation if VPP = VPP (12V), CE high,

low and VCC = VCP (5V).

Erase/Program Inhibit

Erase or program inhibit mode allows parallel erasing or programming of multiple chips with different
data. When CE high , VPP = VPP/VPE (12V/14V), and VCC = 5V, erasing or programming of non­target chips is inhibited, so that except for the CE and VPP, and VCC, the W27C4096 may have

common inputs.

- 2 -

Preliminary W27C4096

CE

OE

Standby Mode

The standby mode significantly reduces VCC current. This mode is entered when CE high , VPP = 5V,
and VCC = 5V. In standby mode, all outputs are in a high impedance state, independent of OE.

Two-line Output Control

Since EPROMs are often used in large memory arrays, the W27C4096 provides two control inputs for
multiple memory connections. Two-line control provides for lowest possible memory power
dissipation and ensures that data bus contention will not occur.

System Considerations

EPROM power switching characteristics require careful device decoupling. System designers are
interested in three supply current issues: standby current levels (ISB), active current levels (ICC), and

transient current peaks produced by the falling and rising edges of CE. Transient current magnitudes
depend on the device output's capacitive and inductive loading. Two-line control and proper
decoupling capacitor selection will suppress transient voltage peaks. Each device should have a 0.1 µ
F ceramic capacitor connected between its VCC and GND. This high frequency, low inherent­inductance capacitor should be placed as close as possible to the device. Additionally, for every eight
devices, a 4.7 µF electrolytic capacitor should be placed at the array's power supply connection
between VCC and GND. The bulk capacitor will overcome voltage slumps caused by PC board trace
inductances.

TABLE OF OPERATING MODES

(VPP = 12V, VPE = 14V, VHH = 12V, VCP = 5V, X = VIH or VIL)

MODE PINS

A0 A9 VCC VPP OUTPUTS

Read VIL VIL X X VCC VCC DOUT
Output Disable VIL VIH X X VCC VCC High Z
Standby (TTL) VIH X X X VCC VCC High Z
Standby (CMOS)
Program VIL VIH X X VCP VPP DIN
Program Verify VIH VIL X X VCP VPP DOUT
Program Inhibit VIH X X X VCP VPP High Z
Erase VIL VIH VIL VPE VCE VPE DIH
Erase Verify VIH VIL X X VCE VPE DOUT
Erase Inhibit VIH X X X VCE VPE High Z
Product Identifier-manufacturer VIL VIL VIL VHH VCC VCC 00DA (Hex)
Product Identifier-device VIL VIL VIH VHH VCC VCC 000D (Hex)

VCC ±0.3V

X X X VCC VCC High Z

Publication Release Date: March 1999

- 3 - Revision A1

DC CHARACTERISTICS

CE

CE

Absolute Maximum Ratings

PARAMETER RATING UNIT

Preliminary W27C4096

Ambient Temperature with Power Applied -55 to +125
Storage Temperature -65 to +125
Voltage on all pins with Respect to Ground Except VPP, A9

and VCC pins
Voltage on VPP Pin with Respect to Ground -0.5 to +14.5 V
Voltage on A9 Pin with Respect to Ground -0.5 to +14.5 V
Voltage on VCC Pin with Respect to Ground -0.5 to +7 V

Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the

device.

-0.5 to VCC +0.5 V

°C
°C

DC Erase Characteristics

(TA = 25° C ±5° C, VCC = 5.0V ± 5%, VHH = 14V)

PARAMETER SYM. CONDITIONS LIMITS UNIT

MIN. TYP. MAX.

Input Load Current ILI VIN = VIL or VIH -10 - 10
VCC Erase Current ICP
VPP Erase Current IPP
Input Low Voltage VIL - -0.3 - 0.8 V

= VIL
= VIL

- - 30 mA

- - 30 mA

µA

Input High Voltage VIH - 2.4 - 5.5 V
Output Low Voltage (Verify) VOL IOL = 2.1 mA - - 0.45 V
Output High Voltage (Verify) VOH IOH = -0.4 mA 2.4 - - ­A9 Erase Voltage VID - 13.75 14 14.25 V
VPP Erase Voltage VPE - 13.75 14 14.25 V
VCC Supply Voltage (Erase) VCE - 4.5 5.0 5.5 V

Note: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP.

CAPACITANCE

(VCC = 5V, TA = 25° C, f = 1 MHz)

PARAMETER SYMBOL CONDITIONS MAX. UNIT

Input Capacitance CIN VIN = 0V 6 pF
Output Capacitance COUT VOUT = 0V 12 pF

- 4 -

Preliminary W27C4096

100 pF (Including Jig and Scope)

AC CHARACTERISTICS

AC Test Conditions

PARAMETER CONDITIONS

Input Pulse Levels 0.45V to 2.4V
Input Rise and Fall Times 10 nS
Input and Output Timing Reference Level 0.8V/2.0V
Output Load CL = 100 pF, IOH/IOL = -0.4 mA/2.1 mA

AC Test Load and Waveform

+1.3V

(IN914)

D

OUT

Input

2.4V

0.45V

3.3K ohm

Output

Test Points Test Points

2.0V

0.8V

2.0V

0.8V

Publication Release Date: March 1999

- 5 - Revision A1

Preliminary W27C4096

CE

CE

CE

OE

READ OPERATION DC CHARACTERISTICS

(VCC = 5.0V ±5%, TA = 0 to 50° C)

PARAMETER SYM. CONDITIONS LIMITS UNIT

MIN. TYP. MAX.

Input Load Current ILI VIN = 0V to VCC -5 - 5
Output Leakage Current ILO VOUT = 0V to VCC -10 - 10
VCC Standby Current ISB

ISB1

VCC Operating Current ICC

VPP Operating Current IPP VPP = VCC - - 10
Input Low Voltage VIL - -0.3 - 0.8 V
Input High Voltage VIH - 2.2 - VCC +0.5 V
Output Low Voltage VOL IOL = 2.1 mA - - 0.4 V
Output High Voltage VOH IOH = -0.4 mA 2.4 - - V
VPP Operating Voltage VPP - VCC -0.7 - VCC V

= VIH
= VCC ±0.2V
= VIL

IOUT = 0 mA, f = 5 MHz

- - 1.0 mA

- 5 100

- - 30 mA

READ OPERATION AC CHARACTERISTICS

(VCC = 5.0V ±5%, TA = 0 to 50° C)

PARAMETER SYM. W27C4096-12 W27C4096-15 UNIT

µA
µA

µA

µA

MIN. MAX. MIN. MAX.

Read Cycle Time TRC 120 - 150 - nS
Chip Enable Access Time TCE - 120 - 150 nS
Address Access Time TACC - 120 - 150 nS
Output Enable Access Time TOE - 50 - 70 nS

High to High-Z Output

Output Hold from Address Change TOH 0 - 0 - nS

Note: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP.

TDF - 30 - 30 nS

- 6 -

Preliminary W27C4096

CE

CE

CE

CE

OE

OE

OE

DC PROGRAMMING CHARACTERISTICS

(VCC = 5.0V ±5%, TA = 25° C ±5° C)

PARAMETER SYM. CONDITIONS LIMITS UNIT

MIN. TYP. MAX.

Input Load Current ILI VIN = VIL or VIH -10 - 10
VCC Program Current ICP
VPP Program Current IPP
Input Low Voltage VIL - -0.3 - 0.8 V
Input High Voltage VIH - 2.4 - 5.5 V
Output Low Voltage (Verify) VOL IOL = 2.1 mA - - 0.45 V
Output High Voltage (Verify) VOH IOH = -0.4 mA 2.4 - - V
A9 Silicon I.D. Voltage VID - 11.5 12.0 12.5 V
VPP Program Voltage VPP - 11.75 12.0 12.25 V
VCC Supply Voltage (Program) VCP - 4.5 5.0 5.5 V

= VIL
= VIL

- - 30 mA

- - 30 mA

µA

AC PROGRAMMING/ERASE CHARACTERISTICS

(VCC = 5.0V ±5%, TA = 25° C ±5° C)

PARAMETER SYM. LIMITS UNIT

MIN. TYP. MAX.

VPP Setup Time TVPS 2.0 - ­Address Setup Time TAS 2.0 - ­Data Setup Time TDS 2.0 - -

Program Pulse Width
Erase Pulse Width

Data Hold Time TDH 2.0 - -

Setup Time

Data Valid from

High to Output High Z

Address Hold Time TAH 0 - ­Address Hold Time after CE High (Erase)

Note: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP.

TPWP 95 100 105
TPWE 95 100 105 mS

TOES 2.0 - ­TOEV - - 150 nS
TDFP 0 - 130 nS

TAHC 2.0 - -

µS
µS
µS
µS

µS
µS

µS
µS

Publication Release Date: March 1999

- 7 - Revision A1

TIMING WAVEFORMS

Address Valid

Stable

IL

AC Read Waveform

V

CE

OE

Outputs

IH

V

IL

V

IH

IL

IH

V

IL

High Z

Address

Preliminary W27C4096

CE

T

T

DF

T

T

ACC

OE

Valid Output

T

OH

High Z

Erase Waveform

V

Data

V

CE

OE

PP

14.0V

5.0V

V
V

V

IH

V

IL

IH

IL

IH

V

IL

Address

Read

Manufacturer

SID

A9 = 12.0V

A0= V

Others = V

A0 = V

T

ACC

00DA

T

CE

T

OE

IH

IL

T

OE

Read

Device

SID

IL

Others = V

T

ACC

000D

IL

T

T

Chip Erase
A9 = 14.0V

Others = V

AS T

Data All One

T

DS

VPS

T

ARC

PWE

Erase Verify

Address

T

AHC

T

OES

Address
Stable

T

DFP

D

OUT D

T

AH

T

OEV

D

OUT

Blank Check
Read Verify

Address
Stable

T

ACC

T

OE

OUT

5V

- 8 -

Timing Waveforms, continued

Programming Waveform

Preliminary W27C4096

Address

Data

V

CE

OE

PP

12.0V

5.0V

Read

Verify

Address Valid

T

ACC

T

OE

D

OUT

5V

OES

Program

Verify

D

T

OEV

OUT

Address Stable

T

DFP

D

OUT

T

AH

Program

V

IH

T

T

VPS

Address Stable

AS

Data In Stable

T

DS

T

PWP

T

DH

T

V

IL

V

IH

V

IL

V

IH

V

IL

Publication Release Date: March 1999

- 9 - Revision A1

SMART PROGRAMMING ALGORITHM

Start

Address = First Location

Vcc = 5V
Vpp = 12V

X = 0

Preliminary W27C4096

Increment
Address

Program One 100 S Pulse

Increment X

X = 25?

Fail

No

Verify

One Word

Last
Address?

Vcc = 5V

Vpp = 5V

Compare

All Words to

Original Data

µ

Yes

No

Pass

Yes

Fail

Verify

One Word

Pass

Fail

Pass
Device

Pass

Fail
Device

- 10 -

SMART ERASE ALGORITHM

Preliminary W27C4096

Start

X = 0

Vcc = 5V
Vpp = 14V

Increment

Address

A9 = 14V; A0 = V

Chip Erase 100 mS Pulse

Address = First Location

Increment X

Erase

Verify

No

Last
Address?

Vcc = 5V
Vpp = 5V

Compare

All Words to

FFFF (HEX)

IL

Pass

Yes

No

Fail

X = 20?

Yes

Fail

Pass
Device

Pass

Fail
Device

Publication Release Date: March 1999

- 11 - Revision A1

ORDERING INFORMATION

Preliminary W27C4096

PART NO. ACCESS

TIME (nS)

W27C4096-12 120 30 100 600 mil DIP
W27C4096T-12 120 30 100 40-pin TSOP
W27C4096P-12 120 30 100 44-pin PLCC
W27C4096-15 150 30 100 600 mil DIP
W27C4096T-15 150 30 100 40-pin TSOP
W27C4096P-15 150 30 100 44-pin PLCC

Notes:

1. Winbond reserves the right to make changes to its products without prior notice.

2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in
applications where personal injury might occur as a consequence of product failure.

POWER SUPPLY

CURRENT MAX.

(mA)

STANDBY VCC

CURRENT MAX.

(µA)

PACKAGE

- 12 -

PACKAGE DIMENSIONS

40-pin PDIP

40

1

E

1

S

2

A

A

L

D

B

1e

1B

Preliminary W27C4096

Dimension in inches Dimension in mm

Symbol

Min. Nom. Max. Max.

A

0.010

1

A

0.150

2

A

0.016

B

1

B

0.008

c
D

21

20

Base Plane

A

1

Seating Plane

E

e

A

a

E

0.540

1

E

1

e

0.120

L

a

0.630 16.00

A

e
S

Notes:

1. Dimensions D Max & S include mold flash or
tie bar burrs.

2. Dimension E1 does not include interlead flash.

c

3. Dimensions D & E1 include mold mismatch and
are determined at the mold parting line.

4. Dimension B1 does not include dambar
protrusion/intrusion.

5. Controlling dimension: Inches.

6. General appearance spec. should be based on

final visual inspection spec.

0.210

0.155

0.160

0.018

0.022

0.050 1.27

0.0540.048

0.010

0.014

2.055 2.070 52.20 52.58

0.610

0.6000.590

0.545

0.550

0.110

0.140

0.130

0 15

0.670

0.650

0.090

.

0.25

3.81

0.41

0.20

14.99

13.72

2.29 2.54 2.790.090 0.100

3.05

Nom.Min.

15.24

16.51

5.33

3.94

4.06

0.46

0.56

1.371.22

0.25

0.36

15.49

13.9713.84

3.30

3.56
150

17.02

2.29

40-pin TSOP

1

e

M

0.10(0.004)

b

θ

L

D

H
D

c

E

Symbol

A
A

A

b

1

2

Min. Nom. Max.

0.006

0.002

c

0.72 0.724 0.728

D

0.390 0.394 0.398

E

D

0.780 0.787 0.795

H

e
L

A

2

A

1

A

L1

Y

L
Y

θ

Controlling dimension: Millimeters

0.020

1

0.000

0.020

0.024

0.031

0 3 5

Min. Nom. Max.

0.047

18.3

0.028

0.004

Dimension in mmDimension in Inches

0.05

0.95

0.17 0.22 0.270.007 0.009 0.011

0.10 0.15 0.200.004 0.006 0.008

9.90

19.8

0.50

0.00

1.20

0.15

1.00

1.050.0410.0390.037

18.4

18.5

10

10.10

20.0

20.2

0.50

0.60

0.70

0.8

0.10

0

3

5

Publication Release Date: March 1999

- 13 - Revision A1

Package Dimensions, continued

44-pin PLCC

D

H

6 1

7

17

L

θ

Seating Plane

D

e

DG

44 40

b
b

1

Preliminary W27C4096

Dimension in inches Dimension in mm

Symbol

39

E

E H

29

2818

2

A

A

A1

y

E

G

c

Notes:

1. Dimension D & E do not include interlead flash.

Min. Nom.

A

0.020

1

A

0.145

2

A

0.026

b

1

0.016

b

0.008

c

0.648

D
E

e

0.590

D

G

0.590

E

G

0.680

HD

0.680

H

E

0.090

L

y

2. Dimension b1 does not include dambar
protrusion/intrusion.

3. Controlling dimension: Inches

4. General appearance spec. should be based
on final visual inspection spec.

0.050

0.150

0.028

0.018

0.010

0.653

0.610

0.690

0.690

0.100

BSC

Max.

0.185

0.155

0.032

0.022

0.014

0.658

0.6580.6530.648

0.630

0.6300.610

0.700

0.700

0.110

0.004

0.51

3.68

0.66

0.41

0.20

16.46

14.99

17.27

17.27

2.29

1.27

Nom.Min.

3.81

0.71

0.46

0.25

16.59

15.49

15.4914.99

17.53

2.54

Max.

4.70

3.94

0.81

0.56

0.36

16.71

16.7116.5916.46

BSC

16.00

16.00

17.78

17.7817.53

2.79

0.10

- 14 -

Preliminary W27C4096

VERSION HISTORY

VERSION DATE PAGE DESCRIPTION

A1 Mar. 1999 Initial Issued

Headquarters

No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: [phone]
FAX: [phone]
http://www.winbond.com.tw/
Voice & Fax-on-demand: 886-2-7197006

Winbond Electronics (H.K.) Ltd.

Rm. 803, World Trade Square, Tower II,
123 Hoi Bun Rd., Kwun Tong,
Kowloon, Hong Kong
TEL: [phone]
FAX: [phone]

Taipei Office

11F, No. 115, Sec. 3, Min-Sheng East Rd.,
Taipei, Taiwan
TEL: [phone]
FAX: [phone]

Note: All data and specifications are subject to change without notice.

Winbond Electronics North America Corp.
Winbond Memory Lab.
Winbond Microelectronics Corp.
Winbond Systems Lab.

2727 N. First Street, San Jose,
CA 95134, U.S.A.
TEL: [phone]
FAX: [phone]

Publication Release Date: March 1999

- 15 - Revision A1