Datasheet W27C020PM-90, W27C020PM-70, W27C020PM-12, W27C020M-90, W27C020M-70 Datasheet (Winbond Electronics)

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Page 1

Preliminary W27C020M

PGM

256K × 8 ELECTRICALLY ERASABLE EPROM

GENERAL DESCRIPTION

The W27C020M is a high speed, low power Electrically Erasable and Programmable Read Only Memory organized as 262144 × 8 bits that operates on a single 5 volt power supply. The W27C020M provides an electrical chip erase function.The W27C020M is designed to be used in 3.3V I/O bus interface enviornment.

FEATURES

• High speed access time:

70/90/120 nS (max.)

• Read operating current: 30 mA (max.)

• Erase/Programming operating current:

30 mA (max.)

• Standby current: 1 mA (max.)

• Single 5V power supply

PIN CONFIGURATIONS

Vpp

A16

A15

A12

32-pin DIP

13 14

Q1 Q2

GND

4 3 2 1

A7 A6

6 7

A5 A4

8 A3 A2 A1 A0 Q0

32-pin PLCC

151

Q1Q2Q4Q

G N D

1 7

Q 3

32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17

18192

Vcc PGM

A17 A14 A13 A8 A9 A11

OE A10 CE Q7 Q6 Q5

Q4 Q3

A 1 7

3 0

A14

A13

A11

A10

23 22

Q 6

• +14V erase/+12V programming voltage

• Fully static operation

• Output level : 3.3V compatible output

• All inputs and outputs directly TTL/CMOS

compatible

• Three-state outputs

• Available packages: 32-pin 600 mil DIP and

PLCC

BLOCK DIAGRAM

PGM

CE OE

A17

GND

CONTROL

DECODER

OUTPUT

BUFFER

CORE

ARRAY

PIN DESCRIPTION

SYMBOL DESCRIPTION

A0−A17

Q0−Q7

VPP Program/Erase Supply Voltage VCC Power Supply

GND Ground

Address Inputs Data Inputs/Outputs Chip Enable Output Enable Program Enable

Publication Release Date: March 1999

- 1 - Revision A1

Page 2

Preliminary W27C020M

PGM

FUNCTIONAL DESCRIPTION

Read Mode

Like conventional UVEPROMs, the W27C020M has two control functions, both of which produce data at the outputs.

is for power control and chip select. OE controls the output buffer to gate data to the output pins. When addresses are stable, the address access time (TACC) is equal to the delay from CE to output (TCE), and data are available at the outputs TOE after the falling edge of OE, if TACC and TCE timings

are met.

Erase Mode

The erase operation is the only way to change data from "0" to "1." Unlike conventional UVEPROMs, which use ultraviolet light to erase the contents of the entire chip (a procedure that requires up to half an hour), the W27C020M uses electrical erasure. Generally, the chip can be erased within 100 mS by using an EPROM writer with a special erase algorithm.

Erase mode is entered when VPP is raised to VPE (14V), VCC = VCE (5V), CE low, OE high, A9 = VID (14V), A0 low, and all other address pins low and data input pins high. Pulsing

erase operation.

low starts the

Erase Verify Mode

After an erase operation, all of the bytes in the chip must be verified to check whether they have been successfully erased to "1" or not. The erase verify mode automatically ensures a substantial erase

margin. This mode will be entered after the erase operation if VPP = VPE (14V), CE low, and OE low,

high .

Program Mode

Programming is performed exactly as it is in conventional UVEPROMs, and programming is the only way to change cell data from "1" to "0." The program mode is entered when VPP is raised to VPP

(12V), VCC = VCP (5V), CE low, OE high , the address pins equal the desired addresses, and the input pins equal the desired inputs. Pulsing

low starts the programming operation.

Program Verify Mode

All of the bytes in the chip must be verified to check whether they have been successfully programmed with the desired data or not. Hence, after each byte is programmed, a program verify operation should be performed. The program verify mode automatically ensures a substantial

program margin. This mode will be entered after the program operation if VPP = VPP (12V), CE low ,

low , and

high.

Erase/Program Inhibit

Erase or program inhibit mode allows parallel erasing or programming of multiple chips with different data. When CE high , erasing or programming of non-target chips is inhibited, so that except for the

, the W27C020M may have common inputs.

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Page 3

Preliminary W27C020M

PGM

Standby Mode

The standby mode significantly reduces VCC current. This mode is entered when CE high . In standby mode, all outputs are in a high impedance state, independent of OE and

Two-line Output Control

Since EPROMs are often used in large memory arrays, the W27C020M provides two control inputs for multiple memory connections. Two-line control provides for lowest possible memory power dissipation and ensures that data bus contention will not occur.

System Considerations

EPROM power switching characteristics require careful device decoupling. System designers are concerned with three supply current issues: standby current levels (ISB), active current levels (ICC),

and transient current peaks produced by the falling and rising edges of CE. Transient current magnitudes depend on the device output's capacitive and inductive loading. Two-line control and proper decoupling capacitor selection will suppress transient voltage peaks. Each device should have a 0.1 µF ceramic capacitor connected between its VCC and GND. This high frequency, low inherentinductance capacitor should be placed as close as possible to the device. Additionally, for every eight devices, a 4.7 µF electrolytic capacitor should be placed at the array's power supply connection between VCC and GND. The bulk capacitor will overcome voltage slumps caused by PC board trace inductances.

TABLE OF OPERATING MODES

VPP = 12V, VPE = 14V, VHH = 12V, VCP = 5V, VCE = 5V, VID = 14V, X = VIH or VIL

MODE PINS

PGM

Read VIL VIL X X X VCC VCC DOUT Output Disable VIL VIH X X X VCC VCC High Z Standby (TTL) VIH X X X X VCC VCC High Z Standby (CMOS) Program VIL VIH VIL X X VCP VPP DIN Program Verify VIL VIL VIH X X VCC VPP DOUT Program Inhibit VIH X X X X VCP VPP High Z Erase VIL VIH VIL VIL VID VCE VPE FF (Hex) Erase Verify VIL VIL VIH X X VCC VPE DOUT Erase Inhibit VIH X X X X VCE VPE High Z Product Identifier-

manufacturer Product Identifier-device VIL VIL X VIH VHH VCC VCC 85 (Hex)

VCC ±0.3V

VIL VIL X VIL VHH VCC VCC DA (Hex)

X X X X VCC VCC High Z

A0 A9 VCC VPP OUTPUTS

Publication Release Date: March 1999

- 3 - Revision A1

Page 4

DC CHARACTERISTICS

PGM

Absolute Maximum Ratings

PARAMETER RATING UNIT

Preliminary W27C020M

Operation Temperature 0 to +70 Storage Temperature -65 to +125 Voltage on all Pins with Respect to Ground Except VCC, VPP

and A9 Pins Voltage on VCC Pin with Respect to Ground -0.5 to +7 V Voltage on VPP Pin with Respect to Ground -0.5 to +14.5 V Voltage on A9 Pin with Respect to Ground -0.5 to +14.5 V

Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability

of the device.

-0.5 to VCC +0.5 V

DC Erase Characteristics

(TA = 25° C ±5° C, VCC = 5.0V ±5%, VHH = 14V)

PARAMETER SYM. CONDITIONS LIMITS UNIT

MIN. TYP. MAX.

Input Load Current ILI VIN = VIL or VIH -10 - 10 VCC Erase Current ICP

= VIL, OE = VIH,

= VIL, A9 = VHH

- - 30 mA

°C °C

µA

VPP Erase Current IPP

Input Low Voltage VIL - -0.3 - 0.8 V Input High Voltage VIH - 2.4 - 5.5 V Output Low Voltage (Verify) VOL IOL = 2.1 mA - - 0.45 V Output High Voltage (Verify) VOH IOH = -0.4 mA 2.4 - - V

VOH2 IOH = -0.1 mA, VCC =

A9 Erase Voltage VID - 13.75 14.0 14.25 V VPP Erase Voltage VPE - 13.75 14.0 14.25 V VCC Supply Voltage (Erase) VCE - 4.75 5.0 5.25 V

Note: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP.

= VIL, OE = VIH,

= VIL, A9 = VHH

- 4 -

- - 30 mA

- - 3.8 V

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Preliminary W27C020M

CAPACITANCE

(VCC = 5V, TA = 25° C, f = 1 MHz)

PARAMETER SYMBOL CONDITIONS MAX. UNIT

Input Capacitance CIN VIN = 0V 6 pF Output Capacitance COUT VOUT = 0V 12 pF

AC CHARACTERISTICS

AC Test Conditions

PARAMETER CONDITIONS

70 nS 90/120 nS

Input Pulse Levels 0 to 3.0V 0.45V to 2.4V Input Rise and Fall Times 5 nS 10 nS Input and Output Timing Reference

Level Output Load CL = 30 pF,

1.5V/1.5V 0.8V/2.0V

CL = 100 pF,

IOH/IOL = -0.4 mA/2.1 mA

AC Test Load and Waveforms

OUT

Input/Outpu

For 90/120 nS

2.4V

0.45V

3.0V

+1.3V

(IN914)

3.3K ohm

100 pF for 90/120 nS (Including Jig and Scope)

30 pF for 70 nS (Including Jig and Scope)

Test Points Test Points

2.0V

0.8V

Test Point Test Point

1.5V

1.5VFor 70 nS

Publication Release Date: March 1999

- 5 - Revision A1

Page 6

Preliminary W27C020M

READ OPERATION DC CHARACTERISTICS

(Vcc = 5.0V ±5%)

PARAMETER SYM. CONDITIONS LIMITS UNIT

MIN. TYP. MAX.

Input Load Current ILI VIN = 0V to VCC -5 - 5 Output Leakage Current ILO VOUT = 0V to VCC -10 - 10 Standby VCC Current

(TTL input) Standby VCC Current

(CMOS input) VCC Operating Current ICC

VPP Operating Current IPP VPP = VCC - - 10 Input Low Voltage VIL - -0.3 - 0.8 V Input High Voltage VIH - 2.2 - VCC +0.5 V Output Low Voltage VOL IOL = 2.1 mA - - 0.45 V Output High Voltage VOH IOH = -0.4 mA 2.4 - - V

VPP Operating Voltage VPP - VCC -0.7 - VCC V

ISB

ISB1

VOH2 IOH = -0.1 mA - - 3.8 V

= VIH

= VCC ±0.3V

= VIL IOUT = 0 mA f = 5 MHz

- - 1.0 mA

- 5 100

- - 30 mA

µA µA

µA

READ OPERATION AC CHARACTERISTICS

(VCC = 5.0V ±5%, for 70, 90 and 120 nS; TA = 0 to 70° C)

PARAMETER SYM. W27C020M-70 W27C020M-90 W27C020M-12 UNIT

MIN. MAX. MIN. MAX. MIN. MAX.

Read Cycle Time TRC 70 - 90 - 120 - nS Chip Enable Access Time TCE - 70 - 90 - 120 nS Address Access Time TACC - 70 - 90 - 120 nS Output Enable Access

Time

High to High-Z Output

Output Hold from Address Change

Note: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP.

TOE - 30 - 40 - 55 nS

TDF - 25 - 25 - 30 nS TOH 0 - 0 - 0 - nS

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Page 7

Preliminary W27C020M

PGM

DC PROGRAMMING CHARACTERISTICS

(VCC = 5.0V ±5%, TA = 25° C ±5° C)

PARAMETER SYM. CONDITIONS LIMITS UNIT

MIN. TYP. MAX.

Input Load Current ILI VIN = VIL or VIH - VCC Program Current ICP

VPP Program Current IPP

Input Low Voltage VIL - -0.3 - 0.8 V Input High Voltage VIH - 2.4 - 5.5 V Output Low Voltage (Verify) VOL IOL = 2.1 mA - - 0.45 V Output High Voltage (Verify) VOH IOH = -0.4 mA 2.4 - - V

VOH2 IOH = -0.1mA - - 3.5 V A9 Silicon I. D. Voltage VID - 11.5 12.0 12.5 V VPP Program Voltage VPP - 11.75 12.0 12.25 V VCC Supply Voltage (Program) VCP - 4.75 5.0 5.25 V

= VIL, OE = VIH,

= VIL

= VIL, OE = VIH,

= VIL

- - 30 mA

±10 µA

AC PROGRAMMING/ERASE CHARACTERISTICS

(VCC = 5.0V ±5%, TA = 25° C ±5° C)

PARAMETER SYM. LIMITS UNIT

MIN. TYP. MAX.

VPP Setup Time TVPS 2.0 - Address Setup Time TAS 2.0 - Data Setup Time TDS 2.0 - -

Program Pulse Width Erase Pulse Width

Data Hold Time TDH 2.0 - -

Setup Time

Data Valid from

High to Output High Z

Address Hold Time after Address Hold Time (Erase) TAHE 2.0 - -

Setup Time

Note: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP.

High

TPWP 95 100 105 TPWE 95 100 105 mS

TOES 2.0 - TOEV - - 150 nS TDFP 0 - 130 nS TAH 0 - -

TCES 2.0 - -

µS µS µS µS

µS µS

µS µS µS

Publication Release Date: March 1999

- 7 - Revision A1

Page 8

TIMING WAVEFORMS

AC Read Waveform

Address Address Valid

Outputs

High Z

Preliminary W27C020M

ACC

Valid Output

High Z

Erase Waveform

Data

PGM

14.0V

5.0V

Address

Read

Manufacturer

SID

A9 = 12.0V

Others = V

A0 = V

DA 85

Others=V

Read

Device

SID

A0=V

Chip Erase

A9 = 14.0V

Others = V

AHC

Data All One

Erase Verify

Address Stable

DFP

Address

Stable

OUT D

OUT

Blank Check Read Verify

Address Stable

ACC

OUT

VPS

OES

CES

PWE

OEV

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Page 9

Timing Waveforms, continued

Programming Waveform

Preliminary W27C020M

Address

Data

PGM

12.0V

5.0V

Program

VPS

Address Stable

Data In Stable

CES

PWP

Program

Verify

Address Stable

DFP

OUT

OES

OEV

OUT

Read

Verify

Address Valid

ACC

OUT

Publication Release Date: March 1999

- 9 - Revision A1

Page 10

SMART PROGRAMMING ALGORITHM

Start

Address = First Location

Vcc = 5V Vpp = 12V

X = 0

Preliminary W27C020M

Increment Address

Program One 100 S Pulse

Increment X

X = 25?

Fail

Verify

One Byte

Last Address?

Vcc = 5V

Vpp = 5V

Compare All Bytes to

Original Data

Yes

Pass

Yes

Fail

Verify

One Byte

Pass

Fail

Pass Device

Pass

Fail Device

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Page 11

SMART ERASE ALGORITHM

Preliminary W27C020M

Start

X = 0

Vcc = 5V

Vpp = 14V

Increment

Address

A9 = 14V; A0 = V

Chip Erase 100 mS Pulse

Address = First Location

Increment X

Erase Verify

Last Address?

Vcc = 5V

Vpp = 5V

Fail

Pass

Yes

X = 20?

Yes

Compare All Bytes to

FFs (HEX)

Pass

Pass Device

Fail

Fail Device

Publication Release Date: March 1999

- 11 - Revision A1

Page 12

ORDERING INFORMATION

Preliminary W27C020M

PART NO. ACCESS

TIME

(nS)

W27C020M-70 70 30 100 600 mil DIP W27C020M-90 90 30 100 600 mil DIP W27C020M-12 120 30 100 600 mil DIP W27C020PM-70 70 30 100 32-pin PLCC W27C020PM-90 90 30 100 32-pin PLCC W27C020PM-12 120 30 100 32-pin PLCC

Notes:

1. Winbond reserves the right to make changes to its products without prior notice.

2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure.

POWER SUPPLY

CURRENT MAX.

(mA)

STANDBY VCC

CURRENT MAX.

(µA)

PACKAGE

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Page 13

PACKAGE DIMENSIONS

1. Dimensions D Max. & S include mold flash or tie bar burrs.

6. General appearance spec. should be based on final visual

4. Dimension B1 does not include dambar protrusion/intrusion.

32-pin P-DIP

Preliminary W27C020M

32-Lead PLCC

Seating Plane

0.140

0.1150.105 0.110

0.0320.026

0.022

0.014

0.553

0.453

0.530

0.430

0.595

0.495

0.095

0.004

0.210

0.160

0.022

0.0540.048

0.014

0.555

0.110

0.140

0.670

0.085

Dimension in mm

5.33

0.25

3.81

3.94

4.06

0.41

0.46

0.56

1.371.22

0.20

0.36

0.25

42.16

41.91

15.49

15.2414.99

14.1013.9713.84

2.29 2.54 2.790.090 0.100

3.05

3.30

3.56

17.02

16.51

2.16

0.50

2.802.67 2.93

0.66 0.81

0.71

0.41

0.46

0.20

0.25

13.89

13.97

11.35

11.43

1.12 1.420.044 0.056

1.27

12.95

12.45

9.91

10.41

14.86

14.99

12.32

12.45

1.91 2.29

150

3.56

0.56

0.35

14.05

11.51

13.46

10.92

15.11

12.57

2.41

0.10

Dimension in Inches

Symbol

Min. Nom. Max. Max.Nom.Min.

0.010

0.155

0.150

0.016

0.018

0.050 1.27

B 1

0.008

324

Base Plane

Seating Plane

Notes:

2. Dimension E1 does not include interlead flash.

3. Dimensions D & E1 include mold mismatch and are determined at the mold parting line.

5. Controlling dimension: Inches. inspection spec.

Symbol

H D

b b

G D

A A

b b c D

D E

L y

Notes:

1. Dimensions D & E do not include interlead flash.

2. Dimension b1 does not include dambar protrusion/intrusion.

3. Controlling dimension: Inches.

4. General appearance spec. should be based on final visual inspection sepc.

0.010

1.650 1.660

0.6000.590 0.610

0.5500.545

E1 e

0.120

0.130

0 15

0.630 16.00

0.650

Dimension in Inches Dimension in mm

Min. Nom. Max. Max.Nom.Min.

0.020

0.028

0.016

0.018

0.008

0.010

0.547

0.550

0.447

0.450

0.050

0.490

0.510

0.390

0.410

0.585

0.590

0.485

0.490

0.075

0.090

Publication Release Date: March 1999

- 13 - Revision A1

Page 14

Preliminary W27C020M

VERSION HISTORY

VERSION DATE PAGE DESCRIPTION

A1 Mar. 1999 - Initial Issued

Headquarters

No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5796096 http://www.winbond.com.tw/ Voice & Fax-on-demand: 886-2-7197006

Winbond Electronics (H.K.) Ltd.

Rm. 803, World Trade Square, Tower II, 123 Hoi Bun Rd., Kwun Tong, Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064

Taipei Office

11F, No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-7190505 FAX: 886-2-7197502

Note: All data and specifications are subject to change without notice.

- 14 -

Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab.

2727 N. First Street, San Jose, CA 95134, U.S.A. TEL: 408-9436666 FAX: 408-5441798