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W26L010AJ-10

Datasheet W26L010AJ-10, W26L010AT-12, W26L010AJ-12, W26L010AT-10 Datasheet (Winbond Electronics)

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W26L010A
CS
WE
OE
LB
UB
64K × 16 HIGH-SPEED CMOS STATIC RAM
GENERAL DESCRIPTION
The W26L010A is a high-speed, low-power CMOS static RAM organized as 65,536 × 16 bits that operates on a single 3.3-volt power supply. This device is manufactured using Winbond's high performance CMOS technology.
I/O16, the upper byte. This device is well suited for use in high-density, high-speed system applications.
FEATURES
• High speed access time: 10/12 nS (max.)
• Low power consumption:
− Active: 530 mW (max.)
• Single +3.3V power supply
• Fully static operation
− No clock or refreshing
• All inputs and outputs directly TTL compatible
• Three-state outputs
• Data byte control
− LB (I/O1−I/O8), UB (I/O9−I/O16)
• Available packages: 44-pin 400 mil SOJ and
44-pin TSOP(II)
PIN CONFIGURATION
1
A0
2
A1
3
A2
4
A3
5
A4
6
CS
7
I/O1
8
I/O2
9
I/O3 I/O4
10 11
V
DD
V
SS
I/O5 I/O6 I/O7 I/O8
WE
A5 A6 A7 A8 NC NC
44-PIN
12 13 14 15 16 17 18 19 20 21 22
BLOCK DIAGRAM
VDD
V
SS
A0
.
DECODER
44
A15
43
A14 A13
42 41
OE
40
UB
39
LB
38
I/O16
37
I/O15 I/O14
36 35
I/O13
34
VSS V
33
DD
32
I/O12
31
I/O11
30
I/O10
29
I/O9
28
NC
27
A12
26
A11
25
A10
24
A9
23
PIN DESCRIPTION
I/O1−I/O16
.
A15
UB CS
CONTROL
OE WE LB
SYMBOL DESCRIPTION
A0−A15
Address Inputs Data Inputs/Outputs Chip Select Inputs Write Enable Input
Output Enable Input Lower Byte Select I/O1−I/O8 Upper Byte Select I/O9−I/O16
VDD Power Supply
VSS Ground
NC No Connection
CORE
ARRAY
DATA I/O
I/O1
. .
I/O16
Publication Release Date: July 1998
- 1 - Revision A3
TRUTH TABLE
CSOEWE
LB
UB
W26L010A
MODE
H X X X X Not Selected High Z High Z ISB, ISB1
L H H X X Output Disable High Z High Z IDD L L H L L 2 Bytes Read DOUT DOUT IDD L L H L H Lower Byte Read DOUT High Z IDD L L H H L Upper Byte Read High Z DOUT IDD L X L L L 2 Bytes Write DIN DIN IDD L X L L H Lower Byte Write DIN High Z IDD L X L H L Upper Byte Write High Z DIN IDD L X X H H Output Disable High Z High Z IDD
I/O1−I/O8 I/O9−I/O16
CURRENT
DC CHARACTERISTICS
Absolute Maximum Ratings
PARAMETER RATING UNIT
Supply Voltage to VSS Potential -0.5 to +4.6 V Input/Output to VSS Potential -0.5 to VDD +0.5 V
VDD
Allowable Power Dissipation 1.5 W Storage Temperature -65 to +150 Operating Temperature 0 to +70
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the
device.
- 2 -
°C °C
W26L010A
CS
CS
CS
Operating Characteristics
(VDD = 3.3V ±5%, VSS = 0V, TA = 0 to 70° C)
PARAMETER SYM. TEST CONDITIONS MIN. TYP. MAX. UNIT
Input Low Voltage VIL - -0.5 - +0.8 V Input High Voltage VIH - +2.0 - VDD
+0.3
Input Leakage Current
Output Leakage Current
Output Low Voltage VOL IOL = +8.0 mA - - 0.4 V Output High Voltage VOH IOH = -4.0 mA 2.4 - - V Operating Power IDD
Supply Current I/O = open, Duty = 100% 12 - - 140 Standby Power ISB
Supply Current ISB1
Note: Typical characteristics are evaluated at VDD = 3.3V, TA = 25° C.
ILI VIN = VSS to VDD -10 - +10
ILO VI/O = VSS to VDD
Output Pins in High Z, See Truth Table
= VIL (max.), Cycle =
min.
= VIH (min.), Cycle = min. = VDD -0.2V, I/O = open
All other pins = VDD -0.2V/GND
10 - - 160 mA
-10 - +10
- - 30 mA
- - 10 mA
V
µA
µA
CAPACITANCE
(VDD = 3.3V, TA = 25° C, f = 1 MHz)
PARAMETER SYM. CONDITIONS MAX. UNIT
Input Capacitance CIN VIN = 0V 6 pF Input/Output Capacitance CI/O VOUT = 0V 8 pF
Note: These parameters are sampled but not 100% tested.
AC CHARACTERISTICS AC Test Conditions
PARAMETER CONDITIONS
Input Pulse Levels 0V to 3V Input Rise and Fall Times 2 nS Input and Output Timing Reference Level 1.5V Output Load CL = 30 pF, IOH/IOL = -4 mA/8 mA
Publication Release Date: July 1998
- 3 - Revision A3
AC Test Loads and Waveform
UB, LB
UB, LB
UB, LB
W26L010A
T
OLZ,
R1 320 ohm
5 pF
Including Jig and Scope
T
T
CHZ,
BHZ,
R2 350 ohm
WHZ,
)
T
OW
T
T
OHZ,
3.3V
OUTPUT
(VDD = 3.3V ±5%, VSS = 0V, TA = 0 to 70° C)
R1 320 ohm
30 pF Including
Jig and Scope
R2 350 ohm
3.0V
3.3V
OUTPUT
2 nS
T
T
BLZ,
CLZ,
(
For
90% 90%
0V
10%
2 nS
10%
(1) Read Cycle
PARAMETER SYM.
Read Cycle Time TRC 10 - 12 - nS
W26L010A-10 W26L010A-12
MIN. MAX. MIN. MAX.
UNIT
Address Access Time TAA Chip Select Access Time TACS Output Enable to Output Valid TOE
Access Time
TBA
Output Hold from Address Change TOH 3 Chip Select to Output in Low Z TCLZ* 3 Chip Deselect to Output in High Z TCHZ* Output Enable to Output in Low Z TOLZ* 0 Output Disable to Output in High Z TOHZ*
*
Select to Output in Low Z Deselect to Output in High Z
∗ These parameters are sampled but not 100% tested.
TBLZ TBHZ*
- 4 -
−
−
−
−
−
−
0
−
10 10
5 5
−
−
5
−
5
−
5
−
−
−
−
3 3
−
0
−
0
−
12 nS 12 nS
6 nS 6 nS
−
−
nS nS
6 nS
−
nS
6 nS
−
nS
6 nS
AC Characteristics, continued
UB, LB
CS, WE
(2) Write Cycle
W26L010A
PARAMETER SYM.
Write Cycle Time TWC 10 Chip Select to End of Write TCW 9 Address Valid to End of Write TAW 9 Address Setup Time TAS 0
Select to End of Write Write Pulse Width TWP 9 Write Recovery Time
Data Valid to End of Write TDW 6 Data Hold from End of Write TDH 0 Write to Output in High Z TWHZ* End of Write to Output Active TOW* 3
∗ These parameters are sampled but not 100% tested.
TBW 9
TWR 0
W26L010A-10 W26L010A-12
MIN. MAX. MIN. MAX.
−
−
−
−
−
−
−
−
−
−
6
−
12 10 10
0
10 10
0 7
0
−
3
−
−
−
−
−
−
−
−
−
7 nS
−
UNIT
nS nS nS nS nS
nS nS
nS nS
nS
Publication Release Date: July 1998
- 5 - Revision A3
Timing Waveforms Read Cycle 1
(Address Controlled, CS = OE = UB = LB = VIL, WE = VIH)
T
RC
Address
T
AA
T
OH
D
OUT
Read Cycle 2
(Chip Select Controlled, OE = VIL, WE = VIH)
T
RC
W26L010A
T
OH
Address
CS
OE
UB / LB
D
OUT
HIGH-Z
Notes:
1. WE is high for read cycle.
2. Device is continuously selected.
CS =
CS =OE
= LB = Low
OE
= LB = Low
3. Address valid prior to or coincident with
transition low.
CS
T
CLZ
T
OLZ
TBLZ
T
ACS
T
CHZ
T
OE
T
BA
T
BHZ
T
OHZ
HIGH-Z
- 6 -
Timing Waveforms, continued
D
IN
Read Cycle 3
(Output Enable Controlled, CS = UB = LB = VIL, WE = VIH)
T
RC
Address
T
AA
OE
T
AOE
T
OLZ
D
OUT
Write Cycle 1
T
W26L010A
T
OH
OHZ
(OE Clock)
Address
OE
CS
UB/LB
WE
D
OUT
T
WC
T
WR
T
CW
T
BW
T
AW
T
WP
T
AS
T
T
DW
DH
Publication Release Date: July 1998
- 7 - Revision A3
Timing Waveforms, continued
Write Cycle 2
(OE = VIL Fixed)
Address
CS
UB/LB
WE
D
OUT
D
IN
W26L010A
T
WC
T T
CW
T
BW
T
AW
T
T
AS
WP
T
WHZ (1, 4)
T
DW
WR
T
DH
T
OH
T
OW
(2) (3)
Notes:
1. During this period, I/O pins are in the output state, so input signals of opposite phase to the outputs should not be applied.
2. The data output from DOUT are the same as the data written to DIN during the write cycle.
3. DOUT provides the read data for the next address.
4. Transition is measured ±500 mV from steady state with CL = 5 pF. This parameter is guaranteed but not 100% tested.
ORDERING INFORMATION
PART NO. ACCESS
TIME
(nS)
W26L010AJ-10 10 160 10 44-pin 400 mil SOJ W26L010AJ-12 12 140 10 44-pin 400 mil SOJ W26L010AT-10 10 160 10 44-pin TSOP W26L010AT-12 12 140 10 44-pin TSOP
Notes:
1. Winbond reserves the right to make changes to its products without prior notice.
2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure.
OPERATING
CURRENT
MAX. (mA)
STANDBY CURRENT MAX. (mA)
PACKAGE
- 8 -
PACKAGE DIMENSIONS
44-pin Small Outline J Band
W26L010A
44
1
s
Seating Plane
D
b b
1
23
EEH
22
A
2
e
A
1
44-pin Standard Type Two TSOP
D
D
H
e
M
Dimension in inches
Symbol
Min. Nom.
A A
A
1
b
b
0.1380.128
0.025
1
0.110 0.115
0.105
2
0.026
0.028 0.032 0.66 0.711 0.813
0.015
c
1.125 1.130
1.120 28.45
D
0.395
E e
0.044 0.050
0.435 0.440
0.082
0
0.031
0.031
0.37
Max.
Min. Nom. Max.
0.047
0.0410.0390.037
18.31
10.06
11.56
0.004
o
e
1
HE
A
y
L
θ
e
1
c
Y
A A
2
A
1
E
1
L
L
b
0.10 (0.004)
θ
c
L S
y
θ
Dimension in inches
Symbol
Min. Nom.
A
0.002
1
A
2
A
0.010 0.014 0.018
b
0.005 0.006 0.007
c
0.721 0.725 0.729
D
0.396 0.400 0.404
E
0.455 0.463 0.471
D
H
e
0.016 0.020 0.024
L
1
L Y
o
θ 0 50 5
Dimension in mm
Max.
0.635
2.41
0.381
0.178
10.03
1.12
11.05
2.06
0
1.20
1.051.00
0.35 0.45
0.15 0.17
18.41 18.51
10.16 10.26
11.76 11.96
0.80
0.60
0.50
0.80
0.10
3.5853.251
2.54 2.67
28.58
10.16
1.27
9.40
11.18 11.30
o
0.148
0.020
0.0130.007
0.4050.400
0.056
0.445
0.045 1.14
0.004
10
Dimension in mm
0.05
0.95
0.25
0.12
0.40
o
Max.Nom.Min.
3.759
0.508
0.330
28.70
10.29
1.42
0.10
10
Publication Release Date: July 1998
- 9 - Revision A3
W26L010A
VERSION HISTORY
VERSION DATE PAGE DESCRIPTION
A1 May 1995 Initial Issued A2 Feb. 1998 1, 3, 4, 5, 8 Change the relative specification from 15/20 nS to 10/12 nS
1, 8, 9 Add TSOP package
6, 7 Modify timing waveforms
A3 Jul. 1998 3, 4
Revise Vcc from 3.3V ±10% to 3.3V ±5%
Headquarters
No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5796096 http://www.winbond.com.tw/ Voice & Fax-on-demand: 886-2-27197006
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-27190505 FAX: 886-2-27197502
Note: All data and specifications are subject to change without notice.
Winbond Electronics (H.K.) Ltd.
Rm. 803, World Trade Square, Tower II, 123 Hoi Bun Rd., Kwun Tong, Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064
- 10 -
Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab.
2727 N. First Street, San Jose, CA 95134, U.S.A. TEL: 408-9436666 FAX: 408-5441798
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