Page 1
Preliminary W25S243A
LBO
ZZ
64K × 64 BURST PIPELINED HIGH-SPEED
CMOS STATIC RAM
GENERAL DESCRIPTION
The W25S243A is a high-speed, low-power, synchronous-burst pipelined, CMOS static RAM
organized as 65,536 × 64 bits that operates on a single 3.3-volt power supply. A built-in two-bit burst
address counter supports both Pentium burst mode and linear burst mode. The mode to be
executed is controlled by the
the FT pin. A snooze mode can reduces power dissipation.
This device supports 3-1-1-1-2-1-1-1 in a two-bank, back-to-back burst read cycle.
FEATURES
pin. Pipelining or non-pipelining of the data outputs is controlled by
• Synchronous operation
• High-speed access time: 12 nS
• Single +3.3V power supply
• Individual byte write capability
• 3.3V LVTTL compatible I/O
• Clock-controlled and registered input
• Asynchronous output enable
BLOCK DIAGRAM
A(15:0)
CLK
CE(3:1)
GW
BWE
BW(8:1)
OE
ADSC
ADSP
ADV
LBO
FT
INPUT
REGISTER
CONTROL
LOGIC
REGISTER
• Pipelined/non-pipelined data output capability
• Supports snooze mode (low-power state)
• Internal burst counter supports Intel burst
(Interleaved) mode & linear burst mode
• Supports 2T/1T mode
• Packaged in 128-pin QFP and TQFP
64K X 64
CORE
ARRAY
DATA I/O
REGISTER
I/O(64:1)
Publication Release Date: November 1998
- 1 - Revision A1
Page 2
PIN CONFIGURATION
S
V
D
D
Q
C
NCN
E
2
Preliminary W25S243A
/
/
/
C
E
C
3
/
/
B
W
5
/
/
O
E
/
C
B
/
B
W
G
L
W
E
W
K
4
/
/
/
B
V
V
S
D
S
D
B
B
C
W
W
W
E
8
6
7
/
B
W
3
/
/
B
V
B
V
W
W
S
D
2
1
D
V
/
A
A
S
A
D
D
S
D
S
S
Q
V
C
P
VSSQ
I/O33
I/O34
I/O35
I/O36
I/O37
I/O38
I/O39
I/O40
I/O41
I/O42
I/O43
VDDQ
VSSQ
I/O44
I/O45
I/O46
I/O47
I/O48
I/O49
I/O50
I/O51
I/O52
I/O53
VDDQ
VSSQ
I/O54
I/O55
I/O56
I/O57
I/O58
I/O59
I/O60
I/O61
I/O62
I/O63
I/O64
VDDQ
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
7
8
6
5
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
3
9
4
4
424
4
0
3
1
2
2
3
2
44454
1
2
2
1
0
4
6
7
1
1
9
8
48495
1
7
0
1
1
6
5
153
1
1
1
1
1
1
1
1
2
3
4
5
5
5
455
2
1
1
1
1
1
0
1
1
0
0
575
0
9
8
7
5
606
9
8
1
5
6
1
1
1
1
0
0
0
0
3
6
4
5
6
6
2
1
364
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
VDDQ
I/O32
I/O31
I/O30
I/O29
I/O28
I/O27
I/O26
I/O25
I/O24
I/O23
I/O22
VSSQ
VDDQ
I/O21
I/O20
I/O19
I/O18
I/O17
I/O16
I/O15
I/O14
I/O13
I/O12
VSSQ
VDDQ
I/O11
I/O10
I/O9
I/O8
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
VSSQ
A
R
A
V
/
A
/
S
F
1
L
S
T
5
B
Q
O
V
A
V
1
4
A
1
D
S
1
3
D
S
2
A
A
A
1
1
9
8
0
1
A5A4A
A
A
S
7
6
V
3VD
A2A
V
S
S
D
Z
V
A
Z
1
D
0
D
Q
- 2 -
Page 3
PIN DESCRIPTION
CE1
GW
BWE
BW1
BWE
OE
ADV
ADSC
ADSP
FT
LBO
SYMBOL TYPE DESCRIPTION
Preliminary W25S243A
A0−A15
I/O1−I/O64
CLK Input, Clock Processor host bus clock
, CE2, CE3
−BW8
ZZ Input, Asynchronous Snooze pin for low-power state, internal pull low
Input, Synchronous Host address
I/O, Synchronous Data Inputs/Outputs
Input, Synchronous Chip enables
Input, Synchronous Global write
Input, Synchronous Byte write enable from cache controller
Input, Synchronous
Input, Asynchronous Output enable input
Input, Synchronous Internal burst address counter advance
Input, Synchronous Address status from Chip Set
Input, Synchronous Address status from CPU
Input, Static Connected to VSSQ: Device operates in flow-
Host bus byte enables used with
through (non-pipelined) mode.
Connected to VDDQ or unconnected: Device
operates in pipelined mode.
Input, Static Lower address burst order
Connected to VSSQ: Device is in linear mode.
Connected to VDDQ or unconnected: Device is in
non-linear mode.
VDDQ I/O power supply
VSSQ I/O ground
VDD Power supply
VSS Ground
RSV Reserved pin, don't use these pins
NC No connection
Publication Release Date: November 1998
- 3 - Revision A1
Page 4
Preliminary W25S243A
LBO
ADSP
ADSC
ADV
LBO
LBO
BWE
GW
FUNCTIONAL DESCRIPTION
The W25S243A is a synchronous-burst pipelined SRAM designed for use in high-end personal
computers. It supports two burst address sequences for Intel systems (Interleaved mode) and linear
mode, which can be controlled by the
and the burst counter is incremented whenever
switched to non-pipelined mode if necessary.
BURST ADDRESS SEQUENCE
pin. The burst cycles are initiated by
is sampled low. The device can also be
or
INTEL SYSTEM (
= VDDQ) LINEAR MODE (
= VSSQ)
A[1:0] A[1:0] A[1:0] A[1:0] A[1:0] A[1:0] A[1:0] A[1:0]
External Start Address 00 01 10 11 00 01 10 11
Second Address 01 00 11 10 01 10 11 00
Third Address 10 11 00 01 10 11 00 01
Fourth Address 11 10 01 00 11 00 01 10
The device supports several types of write mode operations.
byte writes. The BE[7:0] signals can be directly connected to the SRAM BW[8:1]. The
and BW[8:1] support individual
signal is
used to override the byte enable signals and allows the cache controller to write all bytes to the
SRAM, no matter what the byte write enable signals are. The various write modes are indicated in the
Write Table below. Note that in pipelined mode, the byte write enable signals are not latched by the
SRAM with addresses but with data. In pipelined mode, the cache controller must ensure the SRAM
latches both data and valid byte enable signals from the processor.
TRUTH TABLE
CYCLE
Unselected No 1 X X X 0 X X Hi-Z X
Unselected No 0 X 1 0 X X X Hi-Z X
Unselected No 0 0 X 0 X X X Hi-Z X
Unselected No 0 X 1 1 0 X X Hi-Z X
Unselected No 0 0 X 1 0 X X Hi-Z X
Begin Read External 0 1 0 0 X X X Hi-Z X
Begin Read External 0 1 0 1 0 X X Hi-Z Read
Continue Read Next X X X 1 1 0 1 Hi-Z Read
Continue Read Next X X X 1 1 0 0 D-Out Read
Continue Read Next 1 X X X 1 0 1 Hi-Z Read
Continue Read Next 1 X X X 1 0 0 D-Out Read
Suspend Read Current X X X 1 1 1 1 Hi-Z Read
Suspend Read Current X X X 1 1 1 0 D-Out Read
Suspend Read Current 1 X X X 1 1 1 Hi-Z Read
Suspend Read Current 1 X X X 1 1 0 D-Out Read
ADDRESS
USED
CE1
CE2
CE3 ADSP ADSC ADV
OE
DATA WRITE*
- 4 -
Page 5
Preliminary W25S243A
Truth Table, continued
CYCLE
Begin Write Current X X X 1 1 1 X Hi-Z Write
Begin Write Current 1 X X X 1 1 X Hi-Z Write
Begin Write External 0 1 0 1 0 X X Hi-Z Write
Continue Write Next X X X 1 1 0 X Hi-Z Write
Continue Write Next 1 X X X 1 0 X Hi-Z Write
Suspend Write Current X X X 1 1 1 X Hi-Z Write
Suspend Write Current 1 X X X 1 1 X Hi-Z Write
Notes:
1. For a detailed definition of read/write, see the Write Table below.
2. An "X" means don't care, "1" means logic high, and "0" means logic low.
3. The OE pin enables the data output but is not synchronous with the clock. All signals of the SRAM are sampled synchronous to
the bus clock except for the OE pin.
4. On a write cycle that follows a read cycle, OE must be inactive prior to the start of write cycle to allow write data to setup
the SRAM. OE must also disable the output buffer prior to the finish of a write cycle to ensure the SRAM data hold timings are
met.
ADDRESS
USED
CE1
CE2
CE3 ADSP ADSC ADV
OE
DATA WRITE*
WRITE TABLE
READ/WRITE FUNCTION
Read 1 1 X X X X X X X X
Read 1 0 1 1 1 1 1 1 1 1
Write byte 1 I/O1−I/O8
Write byte 2 I/O9−I/O16
Write byte 2, byte 1 1 0 1 1 1 1 1 1 0 0
Write byte 3 I/O17−I/O24
Write byte 3, byte 1 1 0 1 1 1 1 1 0 1 0
Write byte 3, byte 2 1 0 1 1 1 1 1 0 0 1
Write byte 3, byte 2, byte 1 1 0 1 1 1 1 1 0 0 0
Write byte 4, I/O25−I/O32
Write byte 4, byte 1 1 0 1 1 1 1 0 1 1 0
Write byte 4, byte 2 1 0 1 1 1 1 0 1 0 1
Write byte 4, byte 2, byte 1 1 0 1 1 1 1 0 1 0 0
Write byte 4, byte 3 1 0 1 1 1 1 0 0 1 1
Write byte 4, byte 3, byte 1 1 0 1 1 1 1 0 0 1 0
Write byte 4, byte 3, byte 2 1 0 1 1 1 1 0 0 0 1
Write byte 4, byte 3, byte 2, byte 1 1 0 1 1 1 1 0 0 0 0
Write byte 5, I/O33−I/O40
Write byte 5, byte 1 1 0 1 1 1 0 1 1 1 0
GW
BWE
BW8 BW7 BW6 BW5 BW4 BW3 BW2 BW1
1 0 1 1 1 1 1 1 1 0
1 0 1 1 1 1 1 1 0 1
1 0 1 1 1 1 1 0 1 1
1 0 1 1 1 1 0 1 1 1
1 0 1 1 1 0 1 1 1 1
Publication Release Date: November 1998
- 5 - Revision A1
Page 6
Write Table, continued
Preliminary W25S243A
READ/WRITE FUNCTION
Write byte 5, byte 2 1 0 1 1 1 0 1 1 0 1
Write byte 5, byte 2, byte 1 1 0 1 1 1 0 1 1 0 0
Write byte 5, byte 3 1 0 1 1 1 0 1 0 1 1
Write byte 5, byte 3, byte 1 1 0 1 1 1 0 1 0 1 0
Write byte 5, byte 3, byte 2 1 0 1 1 1 0 1 0 0 1
Write byte 5, byte 3, byte 2, byte 1 1 0 1 1 1 0 1 0 0 0
Write byte 5, byte 4 1 0 1 1 1 0 0 1 1 1
Write byte 5, byte 4, byte 1 1 0 1 1 1 0 0 1 1 0
Write byte 5, byte 4, byte 2 1 0 1 1 1 0 0 1 0 1
Write byte 5, byte 4, byte 2, byte 1 1 0 1 1 1 0 0 1 0 0
Write byte 5, byte 4, byte 3 1 0 1 1 1 0 0 0 1 1
Write byte 5, byte 4, byte 3, byte 1 1 0 1 1 1 0 0 0 1 0
Write byte 5, byte 4, byte 3, byte 2 1 0 1 1 1 0 0 0 0 1
Write byte 5, byte 4, byte 3, byte 2,
byte 1
Write byte 6 1 0 1 1 0 1 1 1 1 1
Write byte 6, byte 1 1 0 1 1 0 1 1 1 1 0
Write byte 6, byte 2 1 0 1 1 0 1 1 1 0 1
Write byte 6, byte 2, byte 1 1 0 1 1 0 1 1 1 0 0
..... and so on ..... ... ... ... ... ... ... ... ... ... ...
Write byte 8, byte 7, byte 6, byte 5,
byte 4, byte 2, byte 1
Write byte 8, byte 7, byte 6, byte 5,
byte 4, byte 3
Write byte 8, byte 7, byte 6, byte 5,
byte 4, byte 3, byte 1
Write byte 8, byte 7, byte 6, byte 5,
byte 4, byte 3, byte 2
Write all bytes 1 0 0 0 0 0 0 0 0 0
Write all bytes 0 x x x x x x x x x
GW
1 0 1 1 1 0 0 0 0 0
1 0 0 0 0 0 0 1 0 0
1 0 0 0 0 0 0 0 1 1
1 0 0 0 0 0 0 0 1 0
1 0 0 0 0 0 0 0 0 1
BWE
BW8 BW7 BW6 BW5 BW4 BW3 BW2 BW1
The ZZ state is a low-power state in which the device consumes less power than in the unselected
mode. Enabling the ZZ pin for a fixed period of time will force the SRAM into the ZZ state. Pulling the
ZZ pin low for a set period of time will wake up the SRAM again. While the SRAM is in ZZ mode, data
retention is guaranteed, but the chip will not monitor any input signal except for the ZZ pin. In the
unselected mode, on the other hand, all the input signals are monitored.
- 6 -
Page 7
Preliminary W25S243A
DC CHARACTERISTICS
Absolute Maximum Ratings
PARAMETER RATING UNIT
Core Supply Voltage to Vss -0.5 to 4.6 V
I/O Supply Voltage to Vss -0.5 to 4.6 V
Input/Output to VSSQ Potential VSSQ -0.5 to VDDQ +0.5 V
Allowable Power Dissipation 1.0 W
Storage Temperature -65 to 150
Operating Temperature 0 to +70
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the
device.
Operating Characteristics
(VDD/VDDQ = 3.15V to 3.6V, VSS/VSSQ = 0V, TA = 0 to 70° C)
PARAMETER SYM. TEST CONDITIONS MIN. TYP. MAX. UNIT
Input Low Voltage VIL - -0.5 - +0.8 V
Input High Voltage VIH - +2.0 - VDD
+0.3
Input Leakage Current ILI VIN = VSSQ to VDDQ -10 - +10
Output Leakage
Current
Output Low Voltage VOL IOL = +8.0 mA - - 0.4 V
Output High Voltage VOH IOH = -4.0 mA 2.4 - - V
Operating Current IDD
Standby Current ISB Unselected mode defined in
ZZ Mode Current IZZ
Note: Typical characteristics are measured at VDD = 3.3V, TA = 25° C.
ILO VI/O = VSSQ to VDDQ, and data
I/O pins in high-Z state defined
in truth table
TCYC ≥ min. , I/O = 0 mA
truth table, VIN, VIO = VIH (min.)
/VIL (max.) TCYC ≥ min.
ZZ mode, TCYC ≥ min.
-10 - + 10
- - 350 mA
- - 80 mA
- - 5 mA
°C
°C
V
µA
µA
CAPACITANCE
(VDD = 3.3V, TA = 25° C, f = 1 MHz)
PARAMETER SYM. CONDITIONS MAX. UNIT
Input Capacitance CIN VIN = 0V 6 pF
Input/Output Capacitance CI/O VOUT = 0V 8 pF
Note: These parameters are sampled but not 100% tested.
Publication Release Date: November 1998
- 7 - Revision A1
Page 8
Preliminary W25S243A
AC CHARACTERISTICS
AC Test Conditions
PARAMETER CONDITIONS
Input Pulse Levels 0V to 3V
Input Rise and Fall Times 2 nS
Input and Output Timing Reference Level 1.5V
Output Load CL = 30 pF, IOH/IOL = -4 mA/8 mA
AC Test Loads and Waveform
R1 320 ohm
Including
Jig and
Scope
T
OHZ,TOLZ,
5 pF
measurement)
VL = 1.5V
OUTPUT
RL = 50 ohm
Zo = 50 ohm
3.0V
0V
30 pF
Including
Jig and
Scope
2 nS
90%
10%
(For T
10%
3.3V
OUTPUT
KHZ,
90%
2 nS
T
KLZ,
AC Timing Characteristics
(VDD/VDDQ = 3.15V to 3.6V, VSS/VSSQ = 0V, TA = 0 to 70° C, all timings measured in pipelined mode)
PARAMETER SYMBOL W25S243A-12 UNIT NOTES
MIN. MAX.
Add. Setup Time TAS 2.5 - nS
Add. Hold Time TAH 0.5 - nS
Write Data Setup Time TDS 2.5 - nS
Write Data Hold Time TDH 0.5 - nS
ADV Setup Time
ADV Hold Time
TADVS 2.5 - nS
TADVH 0.5 - nS
R2
350 ohm
- 8 -
Page 9
Preliminary W25S243A
AC Timing Characteristics, continued
PARAMETER SYMBOL W25S243A-12 UNIT NOTES
MIN. MAX.
ADSP Setup Time
ADSP Hold Time
ADSC Setup Time
ADSC Hold Time
CE1, CE2, CE3 Setup Time
CE1, CE2, CE3 Hold Time
GW , BWE X Setup Time
GW , BWE X Hold Time
Clock Cycle Time TCYC 15 - nS
Clock High Pulse Width TKO 6 - nS
Clock Low Pulse Width TKL 6 - nS
Clock to Output Valid TKQ - 12 nS
Clock to Output High-Z TKHZ 2 15 nS 1
Clock to Output Low-Z TKLZ 0 - nS 1
Clock to Output Invalid TKX 2 - nS 1
Output Enable to Output
Valid
Output Enable to Output
High-Z
Output Enable to Output
Low-Z
Output Enable to Output
Invalid
ZZ Standby Time TZZS - 100 nS 2
ZZ Recover Time TZZR 100 - nS 3
TADSS 2.5 - nS
TADSH 0.5 - nS
TADCS 2.5 - nS
TADCH 0.5 - nS
TCES 2.5 - nS
TCEH 0.5 - nS
TWS 2.5 - nS
TWH 0.5 - nS
TOE - 7 nS
TOHZ - 7 nS 1
TOLZ 0 - nS 1
TOX 0 - nS
Notes:
1. These parameters are sampled but not 100% tested
2. In the ZZ mode, the SRAM will enter a low-power state. In this mode, data retention is guaranteed and the clock is active.
3. ADSC and ADSP should not be accessed for at least 100 nS after chip leaves ZZ mode.
4. Configuration signals LBO and FT are static and should not be changed during operation.
Publication Release Date: November 1998
- 9 - Revision A1
Page 10
TIMING WAVEFORMS
Read Cycle Timing
Preliminary W25S243A
CLK
ADSP
ADSC
ADV
A[15:0]
GW
BWE
BW[4:1]
CE1
CE2
CE3
Single Read Burst Read
T
ADCS
TKH
TADCH
T
ADSS T
ADSH
TADVS TADVH
T
AS T
AH
RD1
TCES
TCES T
TCES
T
WSTWH
T
WSTWH
T
CEH
CEH
TCEH
T
OE
RD2
CE2 and CE3 only sampled with ADSP or ADSC
T
OHZ
TCYC
T
KL
Unselected
ADSP is blocked by CE1 inactive
ADSC initiated read
Suspend Burst
RD3
CE1 masks ADSP
Unselected with CE2
OE
Data-Out
Data-In
TOLZ
High-Z
T
KLZ
High-Z
T
KQ
T
OX
1a
DON'T CARE
UNDEFINED
T
KX
2b
2a
2c
2d
TKX
3a
T
KHZ
- 10 -
Page 11
Timing Waveforms, continued
Write Cycle Timing
Preliminary W25S243A
CLK
ADSP
ADSC
ADV
A[15:0]
GW
BWE
BW[4:1]
CE1
CE2
Single Write Burst Write Unselected
T
ADSS
T
T
ADSH
ADCS
T
ADCH
T
CYC
T
KH
T
KL
ADSP is blocked by CE1 inactive
Write
ADSC initiated write
TADVS TADVH
T
AS T
WR1
ADV must be inactive for ADSP write
AH
WR2
T
WSTWH
GWE allows processor address (and BE=BW)
WR3
to be pipelined during a writeback
TWS TWH
T
T
WH
WS
T
CES
T
CESTCEH
WR1
T
CEH
WR2
CE1 masks ADSP
CE2 and CE3 only sampled with ADSP or ADSC
WR3
Unselected with CE2
CE3
OE
Data-Out
Data-In
T
CES T
High-Z
High-Z
CEH
TDST
DH
1a
DON'T CARE
UNDEFINED
BW[4:1] are applied only to first cycle of WR2
2a 2b 2c
2d 3a
Publication Release Date: November 1998
- 11 - Revision A1
Page 12
Timing Waveforms, continued
Read/Write Cycle Timing
Preliminary W25S243A
CLK
ADSP
ADSC
ADV
A[15:0]
GW
BWE
BW[4:1]
CE1
CE2
CE3
Single Read
T
ADSS TADSH
T
T
ADVSTADVH
T
AS T
AH
RD1
T
T
T
CESTCEH
T
CESTCEH
T
CES T
CEH
T
OE
ADCS T
ADCH
TWH
WS
WSTWH
Single Write
T
CYC
T
KH
T
KL
Burst Read Unselected
ADSP is blocked by CE1 inactive
ADSC initiated read
Suspend Burst
WR1
TWST
RD2
WH
WR1
CE1 masks ADSP
CE2 and CE3 only sampled with ADSP or ADSC
T
OHZ
Unselected with CE3
OE
Data-Out
Data-In
TOLZ
High-Z
T
High-Z
KLZ
T
KQ
DON'T CARE
UNDEFINED
T
OH
1a
T
KHZ
TDSTDH
2a
2b
T
KX
2d2c
T
KHZ
1a
- 12 -
Page 13
Timing Waveforms, continued
ZZ and RD Timing
Preliminary W25S243A
CLK
ADSP
ADSC
ADV
A[15:0]
GW
BWE
BW[4:1]
CE1
CE2
CE3
OE
Data-Out
Data-In
Single Read Snooze -with Data Retention
TADSS TADSH
TADVS TADVH
TAS
TAH
RD1
TWS TWH
TWST
TWS T
RD RD
T
TCEH
CES
TCES TCEH
TCES
TCEH
TOE
TOLZ
High-Z
TKLZ
TKQ
High-Z
TCYC
TKH
TKL
WH
WH
TOHZ
TOH
1a
T
KX
TKHZ
Read
RD2
RD
ZZ
DON'T CARE
UNDEFINED
T
ZZS
TZZR
Publication Release Date: November 1998
- 13 - Revision A1
Page 14
ORDERING INFORMATION
Preliminary W25S243A
PART NO. ACCESS
TIME (nS)
W25S243AF-12 12 350 80 128-pin QFP
W25S243AD-12 12 350 80 128-pin TQFP
Notes
1. Winbond reserves the right to make changes to its products without prior notice.
2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications
where personal injury might occur as a consequence of product failure.
OPERATING
CURRENT
MAX. (mA)
STANDBY
CURRENT
MAX. (mA)
PACKAGE
- 14 -
Page 15
PACKAGE DIMENSIONS
128-pin QFP
128
Preliminary W25S243A
H
D
D
103
1
38
39
Seating Plane
e
See Detail F
b
Symbol
A
A
1
2
A
b
c
D
E
e
D
H
E
H
L
1
L
y
θ
102
64
A
A
y
Dimension in inches
Nom.
Min.
0.004
0.101
0.006
0.004
0.547
0.783 0.787 0.791
0.669
0.905
0.023
0.055
Max. Max.
0.134
0.113
0.107
0.010
0.008
0.006 0.15
0.010
0.555
0.551
0.020
0.685
0.677
0.921
0.913
0.039
0.031
0.071
0.063
0.004
E
H
E
65
A
2
1
Dimension in mm
Nom.
Min.
0.10
2.57
2.72
0.15
0.20
0.10
14.00
13.90
20.00
19.90
0.50
17.20
17.00
23.20 23.40
23.00
0.80
0.60
1.60
1.40
0120
c
L
3.40
2.87
0.25
0.25
14.10
20.10
17.40
1.00
1.80
0.10
12
θ
L
1
Detail F
Publication Release Date: November 1998
- 15 - Revision A1
Page 16
Package Dimensions, continued
128-pin TQFP
Preliminary W25S243A
H
D
D
103128
1
38
39
Seating Plane
e
See Detail F
b
Symbol
A
A
1
A
2
b
c
D
E
e
HD
H
E
L
1
L
y
θ
102
65
64
2
A
A
y
Dimension in inches
Nom.
Min.
0.002
0.053
0.006
0.004
0.547
0.783
0.626
0.862
0.018
Max. Max.
0.063
0.057
0.055
0.011
0.008
0.006 0.15
0.010
0.555
0.551
0.791
0.787
0.020
0.634
0.630
0.870
0.866
0.030
0.024
0.039
0.004
E
HE
A
1
Min.
0.05
1.35
0.15
0.10
13.90
19.90
15.90
21.90
0.45
Dimension in mm
Nom.
1.40
0.20
14.00
14.10
20.00
20.10
0.50
16.10
16.00
22.00 22.10
0.60
1.00
0120
c
1.60
1.45
0.27
0.25
0.75
0.10
12
θ
L
L
1
Detail F
- 16 -
Page 17
Preliminary W25S243A
VERSION HISTORY
VERSION DATE PAGE DESCRIPTION
A1 Nov. 1998 Initial Issued
Headquarters
No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 886-3-5770066
FAX: 886-3-5796096
http://www.winbond.com.tw/
Voice & Fax-on-demand: 886-2-27197006
Winbond Electronics (H.K.) Ltd.
Rm. 803, World Trade Square, Tower II,
123 Hoi Bun Rd., Kwun Tong,
Kowloon, Hong Kong
TEL: 852-27513100
FAX: 852-27552064
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd.,
Taipei, Taiwan
TEL: 886-2-27190505
FAX: 886-2-27197502
Note: All data and specifications are subject to change without notice.
Winbond Electronics North America Corp.
Winbond Memory Lab.
Winbond Microelectronics Corp.
Winbond Systems Lab.
2727 N. First Street, San Jose,
CA 95134, U.S.A.
TEL: 408-9436666
FAX: 408-5441798
Publication Release Date: November 1998
- 17 - Revision A1
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