Datasheet W25Q40EWUXIE Specification

1.8V 4M-BIT
SERIAL FLASH MEMORY WITH
DUAL/QUAD SPI & QPI

W25Q40EW

Publication Release Date: August 18, 2018

- 1 - Preliminar y-Revision J

W25Q40EW

Table of Contents

1. GENERAL DESCRIPTIONS ............................................................................................................. 5

2. FEATURES ....................................................................................................................................... 5

3. PACKAGE TYPES: ........................................................................................................................... 6

3.1 Pin Configuration SOIC 150-mil AND VSOP 150-mil ........................................................... 6

3.2 PAD Configuration WSON 6x5-MM / USON 2x3-mm / USON 4x3-mm .............................. 6

3.3 Pin Description SOIC / VSOP 150-mil, WSON 6x5-MM, USON 2x3-mm / 4x3-mm............ 6

3.4 Ball Configuration WLCSP ................................................................................................... 7

3.5 Ball Description WLCSP ....................................................................................................... 7

4. PIN DESCRIPTIONS ........................................................................................................................ 8

4.1 Chip Select (/CS) .................................................................................................................. 8

4.2 Serial Data Input, Output and IOs (DI, DO and IO0, IO1, IO2, IO3) ..................................... 8

4.3 Write Protect (/WP) .............................................................................................................. 8

4.4 HOLD (/HOLD) ..................................................................................................................... 8

4.5 Serial Clock (CLK) ................................................................................................................ 8

5. BLOCK DIAGRAM ............................................................................................................................ 9

6. FUNCTIONAL DESCRIPTION ....................................................................................................... 10

6.1 SPI / QPI Operations .......................................................................................................... 10

6.2 SPI OPERATIONS ............................................................................................................. 10

6.2.1 Standard SPI Instructions ..................................................................................................... 10

6.2.2 Dual SPI Instructions ............................................................................................................ 10

6.2.3 Quad SPI Instructions ........................................................................................................... 11

6.3 QPI Instructions .................................................................................................................. 11

6.3.1 Hold Function ....................................................................................................................... 11

6.4 WRITE PROTECTION ....................................................................................................... 12

6.4.1 Write Protect Features ......................................................................................................... 12

7. STATUS REGISTERS AND INSTRUCTIONS ............................................................................... 13

7.1 STATUS REGISTERs ........................................................................................................ 13

7.1.1 BUSY BUSY Status (BUSY) – Status Only ....................................................................... 13

7.1.2 Write Enable Latch Status (WEL) – Status Only ............................................................... 13

7.1.3 Block Protect Bits (BP2, BP1, BP0) – Volatile/Non-Volatile Writable ................................ 13

7.1.4 Top/Bottom Block Protect (TB) – Volatile/Non-Volatile Writable ....................................... 13

7.1.5 Sector/Block Protect (SEC) – Volatile/Non-Volatile Writable ............................................ 13

7.1.6 Complement Protect (CMP) Volatile/Non-Volatile Writable .................................................. 14

7.1.7 Status Register Protect (SRP, SRL) Volatile/Non-Volatile Writable ..................................... 14

7.1.8 Erase/Program Suspend Status (SUS) –Status Only ........................................................ 15

7.1.9 Security Register Lock Bits (LB[3:0]) – Volatile/Non-Volatile OTP Writable ...................... 15

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W25Q40EW

7.1.10 Quad Enable (QE) – Volatile/Non-Volatile Writable ........................................................ 15

7.1.11 Reserved Bits – Non Functional ...................................................................................... 16

7.1.12 Status Register Memory Protection (CMP = 0) ................................................................... 17

7.1.13 Status Register Memory Protection (CMP = 1) ................................................................... 18

7.1.14 INSTRUCTIONS ................................................................................................................. 19

7.1.15 Manufacturer and Device Identification .............................................................................. 19

7.1.16 Instruction Set Table 1 (Standard SPI Instructions)

7.1.17 Instruction Set Table 2 (Dual/Quad SPI Instructions) ......................................................... 21

7.1.18 Instruction Set Table 3 (QPI Instructions)

(1)

(1)

......................................................... 20

....................................................................... 22

7.2 Instruction Descriptions ...................................................................................................... 24

7.2.1 Write Enable (06h) ............................................................................................................... 24

7.2.2 Write Enable for Volatile Status Register (50h) .................................................................... 24

7.2.3 Write Disable (04h) ............................................................................................................... 25

7.2.4 Read Status Register-1(05h) and Read Status Register-2(35h) .......................................... 26

7.2.5 Write Status Register-1 (01h), Status Register-2 (31h) ........................................................ 27

7.2.6 Read Data (03h) ................................................................................................................... 29

7.2.7 Fast Read (0Bh) ................................................................................................................... 30

7.2.8 Fast Read Dual Output (3Bh) ............................................................................................... 32

7.2.9 Fast Read Quad Output (6Bh) .............................................................................................. 33

7.2.10 Fast Read Dual I/O (BBh) ................................................................................................... 34

7.2.11 Fast Read Quad I/O (EBh) ................................................................................................. 35

7.2.12 Set Burst with Wrap (77h) .................................................................................................. 37

7.2.13 Page Program (02h) ........................................................................................................... 38

7.2.14 Quad Input Page Program (32h) ........................................................................................ 40

7.2.15 Sector Erase (20h) ............................................................................................................. 41

7.2.16 32KB Block Erase (52h) ..................................................................................................... 42

7.2.17 64KB Block Erase (D8h) ..................................................................................................... 43

7.2.18 Chip Erase (C7h / 60h) ....................................................................................................... 44

7.2.19 Erase / Program Suspend (75h) ......................................................................................... 45

7.2.20 Erase / Program Resume (7Ah) ......................................................................................... 47

7.2.21 Power-down (B9h) .............................................................................................................. 48

7.2.22 Release Power-down / Device ID (ABh) ............................................................................. 49

7.2.23 Read Manufacturer / Device ID (90h) ................................................................................. 51

7.2.24 Read Manufacturer / Device ID Dual I/O (92h) ................................................................... 52

7.2.25 Read Manufacturer / Device ID Quad I/O (94h) ................................................................. 53

7.2.26 Read Unique ID Number (4Bh)........................................................................................... 54

7.2.27 Read JEDEC ID (9Fh) ........................................................................................................ 55

7.2.28 Read SFDP Register (5Ah) ................................................................................................ 56

7.2.29 Erase Security Registers (44h) ........................................................................................... 57

7.2.30 Program Security Registers (42h) ...................................................................................... 58

7.2.31 Read Security Registers (48h) ........................................................................................... 59

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W25Q40EW

7.2.32 Set Read Parameters (C0h) ............................................................................................... 60

7.2.33 Burst Read with Wrap (0Ch) ............................................................................................... 61

7.2.34 Enter QPI Mode (38h) ......................................................................................................... 62

7.2.35 Exit QPI Mode (FFh) ........................................................................................................... 63

7.2.36 Enable Reset (66h) and Reset Device (99h) ...................................................................... 64

8. ELECTRICAL CHARACTERISTICS ............................................................................................... 65

8.1 Absolute Maximum Ratings

8.2 Operating Ranges............................................................................................................... 65

8.3 Power-up Timing and Write Inhibit Threshold .................................................................... 66

8.4 DC Electrical Characteristics: Industrial: ............................................................................ 67

8.5 AC Measurement Conditions .............................................................................................. 68

8.6 AC Electrical Characteristics: ............................................................................................. 69

AC Electrical Characteristics (cont’d) ........................................................................................... 70

8.7 Serial Output Timing ........................................................................................................... 71

8.8 Serial Input Timing .............................................................................................................. 71

8.9 /HOLD Timing ..................................................................................................................... 71

8.10 /WP Timing ......................................................................................................................... 71

9. PACKAGE SPECIFICATION .......................................................................................................... 72

9.1 8-Pin SOIC 150-mil (Package Code SN) ............................................................................ 72

9.2 8-Pin VSOP 150-mil (Package Code SV) ........................................................................... 73

9.3 8-Pad WSON 6x5-mm (Package Code ZP) ....................................................................... 74

9.4 8-Pad USON 2x3-mm (Package Code UXIE) .................................................................... 75

9.5 8-Pad USON 4x3-mm (Package Code UU) ....................................................................... 76

9.6 8-Ball WLCSP (Package Code BY) .................................................................................... 77

9.7 Ordering Information ........................................................................................................... 78

9.8 Valid Part Numbers and Top Side Marking ........................................................................ 79

10. REVISION J1ISTORY ..................................................................................................................... 80

(1)

.......................................................................................... 65

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W25Q40EW

1. GENERAL DESCRIPTIONS

The W25Q40EW (4M-bit) Serial Flash memory provides a storage solution for systems with limited space,
pins and power. The 25Q series offers flexibility and performance well beyond ordinary Serial Flash
devices. They are ideal for code shadowing to RAM, executing code directly from Dual/Quad SPI (XIP)
and storing voice, text and data. The device operates on a single 1.65V to 1.95V power supply with current
consumption as low as 1mA active and 1µA for power-down. All devices are offered in space-saving
packages.

The W25Q40EW array is organized into 2,048 programmable pages of 256-bytes each. Up to 256 bytes
can be programmed at a time. Pages can be erased in groups of 16 (4KB sector erase), groups of 128
(32KB block erase), groups of 256 (64KB block erase) or the entire chip (chip erase). The W25Q40EW
has 128 erasable sectors and 8 erasable blocks respectively. The small 4KB sectors allow for greater
flexibility in applications that require data and parameter storage. (See figure 2.)

The W25Q40EW supports the standard Serial Peripheral Interface (SPI), and a high performance
Dual/Quad output as well as Dual/Quad I/O SPI: Serial Clock, Chip Select, Serial Data I/O0 (DI), I/O1
(DO), I/O2 (/WP), and I/O3 (/HOLD). SPI clock frequencies of up to 104MHz are supported allowing
equivalent clock rates of 208MHz (104MHz x 2) for Dual I/O and 416MHz (104MHz x 4) for Quad I/O when
using the Fast Read Dual/Quad I/O instructions. These transfer rates can outperform standard
Asynchronous 8 and 16-bit Parallel Flash memories.

A Hold pin, Write Protect pin and programmable write protection, with top, bottom or complement array
control, provide further control flexibility. Additionally, the device supports JEDEC standard manufacturer
and device identification with a 64-bit Unique Serial Number.

2. FEATURES

 Family of SpiFlash Memories

– 4M-bit/512K-byte (524,288)
– 256-byte per programmable page
– Standard SPI: CLK, /CS, DI, DO, /WP, /Hold
– Dual SPI: CLK, /CS, IO0, IO1, /WP, /Hold
– Quad SPI: CLK, /CS, IO0, IO1, IO2, IO
– QPI: CLK, /CS, IO0, IO1, IO2, IO3

 Highest Performance Serial Flash

– 104MHz Dual/Quad SPI clocks
– 208/416MHz equivalent Dual/Quad SPI
– 50MB/S continuous data transfer rate
– Up to 6X that of ordinary Serial Flash
– Min 100K Program-Erase cycles per sector
– More than 20-year data retention

 Low Power, Wide Temperature Range

– Single 1.65V to 1.95V supply
– 1mA active current & <1µA Power-down current
– -40°C to +85°C operating range

 Flexible Architecture with 4KB sectors

– Uniform Sector Erase (4K-bytes)
– Uniform Block Erase (32K and 64K-bytes)
– Program one to 256 bytes

3

– Erase/Program Suspend & Resume

 Advanced Security Features

– Software and Hardware Write-Protect
– Top/Bottom, 4KB complement array protection
– Lock-Down and Special OTP array protection
– 64-Bit Unique Serial Number for each device
– Discoverable Parameters (SFDP) Register
– 3X256-Byte Security Registers with OTP locks
– Volatile & Non-volatile Status Register Bits

 Space Efficient Packaging:

– 8-pin SOIC / VSOP 150-mil
– 8-pad WSON 6X5-mm
– USON8 2X3mm / 4x3-mm
– 8-ball WLCSP
– Contact Winbond for KGD and other o

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W25Q40EW

1

2

3

4

8

7

6

5

/CS

DO (IO1)

/WP (IO2)

GND

VCC

/HOLD (IO3)

DI (IO0)

CLK

Top View

1
2
3
4

/CS

DO (IO1)

/WP (IO2)

GND

VCC
/HOLD (IO3)

DI (IO0)

CLK

Top View

8
7
6
5

PIN NO.

PIN NAME

I/O

FUNCTION

1

/CS

I

Chip Select Input

2

DO (IO1)

I/O

Data Output (Data Input Output 1)*1

3

/WP (IO2)

I/O

Write Protect Input ( Data Input Output 2)*2

4

GND

Ground 5 DI (IO0)

I/O

Data Input (Data Input Output 0)*1

6

CLK

I

Serial Clock Input

7

/HOLD (IO3)

I/O

Hold Input (Data Input Output 3)*2

8

VCC

Power Supply

3. PACKAGE TYPES:

W25Q40EW is offered in an 8-pin plastic 150-mil width SOIC (package code SN), an 8-pin VSOP 150-mil
(package code SV), , an 8-pad WSON 6X5-mm (package code ZP) ,an 8-pad USON 2x3-mm (package
code UX),amd 8-pad WLCSP as shown in figure 1a-1c respectively. Package diagrams and dimensions
are illustrated at the end of this datasheet.

3.1 Pin Configuration SOIC 150-mil AND VSOP 150-mil

Figure 1a. W25Q40EW Pin Assignments, 8-pin SOIC 150 -mil & VSOP 150-mil (Package Code SN, SV)

3.2 PAD Configuration WSON 6x5-MM / USON 2x3-mm / USON 4x3-mm

Figure 1b. W2540EW Pad Assignments USON 2x3-MM / 4x3-mm (Package Code UX / UU)

3.3 Pin Description SOIC / VSOP 150-mil, WSON 6x5-MM, USON 2x3-mm / 4x3-mm

*1 IO0 and IO1 are used for Standard and Dual SPI instructions
*2 IO0 – IO3 are used for Quad SPI instructions

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3.4 Ball Configuration WLCSP

BALL NO.

PIN NAME

I/O

FUNCTION

A1

VCC

Power Supply

A2

/CS

I

Chip Select Input

B1

/HOLD

(IO3)

I/O

Hold or Reset Input (Data Input Output 3)

(2)

B2

DO (IO1)

I/O

Data Output (Data Input Output 1)

(1)

C1

CLK

I

Serial Clock Input

C2

/WP (IO2)

I/O

Write Protect Input (Data Input Output 2)

(2)

D1

DI (IO0)

I/O

Data Input (Data Input Output 0)

(1)

D2

GND

Ground

Figure 1c. W25Q40EW Ball Assignments, 8-ball WLCSP (Package Code BY)

W25Q40EW

3.5 Ball Description WLCSP

Notes:

1. IO0 and IO1 are used for Standard and Dual SPI instructions

2. IO0 – IO3 are used for Quad SPI instructions, /WP & /HOLD functions are only available for Standard/Dual SPI.

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W25Q40EW

4. PIN DESCRIPTIONS

4.1 Chip Select (/CS)

The SPI Chip Select (/CS) pin enables and disables device operation. When /CS is high the device is
deselected and the Serial Data Output (DO, or IO0, IO1, IO2, IO3) pins are at high impedance. When
deselected, the devices power consumption will be at standby levels unless an internal erase, program or
write status register cycle is in progress. When /CS is brought low the device will be selected, power
consumption will increase to active levels and instructions can be written to and data read from the device.
After power-up, /CS must transition from high to low before a new instruction will be accepted. The /CS
input must track the VCC supply level at power-up (see “Write Protection” and figure 37). If needed a pull­up resister on /CS can be used to accomplish this.

4.2 Serial Data Input, Output and IOs (DI, DO and IO0, IO1, IO2, IO3)

The W25Q40EW supports standard SPI, Dual SPI and Quad SPI operation. Standard SPI instructions
use the unidirectional DI (input) pin to serially write instructions, addresses or data to the device on the
rising edge of the Serial Clock (CLK) input pin. Standard SPI also uses the unidirectional DO (output) to
read data or status from the device on the falling edge of CLK.

Dual and Quad SPI instructions use the bidirectional IO pins to serially write instructions, addresses or
data to the device on the rising edge of CLK and read data or status from the device on the falling edge of
CLK. Quad SPI instructions require the non-volatile Quad Enable bit (QE) in Status Register-2 to be set.
When QE=1, the /WP pin becomes IO2 and /HOLD pin becomes IO3.

4.3 Write Protect (/WP)

The Write Protect (/WP) pin can be used to prevent the Status Register from being written. Used in
conjunction with the Status Register’s Block Protect (CMP, SEC, TB, BP2, BP1 and BP0) bits and Status
Register Protect (SRP) bits, a portion as small as a 4KB sector or the entire memory array can be
hardware protected. The /WP pin is active low. When the QE bit of Status Register-2 is set for Quad I/O,
the /WP pin function is not available since this pin is used for IO2. See figure 1a-b for the pin configuration
of Quad I/O operation.

4.4 HOLD (/HOLD)

The /HOLD pin allows the device to be paused while it is actively selected. When /HOLD is brought low,
while /CS is low, the DO pin will be at high impedance and signals on the DI and CLK pins will be ignored
(don’t care). When /HOLD is brought high, device operation can resume. The /HOLD function can be
useful when multiple devices are sharing the same SPI signals. The /HOLD pin is active low. When the
QE bit of Status Register-2 is set for Quad I/O, the /HOLD pin function is not available since this pin is
used for IO3. See figure 1a-c for the pin configuration of Quad I/O operation.

4.5 Serial Clock (CLK)

The SPI Serial Clock Input (CLK) pin provides the timing for serial input and output operations. ("See SPI
Operations")

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5. BLOCK DIAGRAM

Block 0 (64KB)

03FF00h 03FFFFh

Block 3 (64KB)

030000h 0300FFh

04FF00h 04FFFFh

Block 4 (64KB)

040000h 0400FFh

Column Decode

And 256 Byte Page Buffer

Beginning

Page Address

Ending

Page Address

Page Address

Latch / Counter

High Voltage

Generators

xx0F00h xx0FFFh

• Sector 0 (4KB) •

xx0000h xx00FFh

xx1F00h xx1FFFh

• Sector 1 (4KB) •

xx1000h xx10FFh

xx2F00h xx2FFFh

• Sector 2 (4KB) •

xx2000h xx20FFh

•

•

•

xxDFFFh

Sector 13 (4KB)

xxD000h xxD0FFh

xxEFFFh

Sector 14 (4KB)

xxE000h xxE0FFh

xxFFFFh

Sector 15 (4KB)

xxF000h xxF0FFh

Block Segmentation

Data

Write Protect Logic and Row Decode

DO (IO1)

DI (IO0)

/CS

CLK

/HOLD (IO3)

/WP (IO2)

00FF00h 00FFFFh

• •

000000h 0000FFh

• •

• •

07FF00h 07FFFFh

• Block 7 (64KB) •

070000h 0700FFh

Column Decode

And 256-Byte Page Buffer

Beginning

Page Address

Ending

Page Address

W25Q40EW

Page Address

High Voltage

Generators

•

•

•

xxDF00h

• •

xxEF00h

• •

xxFF00h

• •

Data

Write Protect Logic and Row Decode

DI (IO )

/CS

CLK

/HOLD (IO

/WP (IO

•

•

•

•

•

•

003000h 0030FFh
002000h 0020FFh
001000h 0010FFh

Security Register 3-1

000000h 0000FFh

Write Control

Logic

Status

Register

SPI

Command &

Control Logic

SFDP Register

Byte AddressByte Address

Latch / Counter

W25Q40EW

Figure 2. W25Q40EW Serial Flash Memory Block Diagram

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Publication Release Date: August 18, 2018

6. FUNCTIONAL DESCRIPTION

Power Up

Standard SPI

Dual SPI

Quad SPI

QPI

Enable QPI

(

38 h )

Disable QPI

(

FFh ) SPI Reset

(

66

h

+

99 h )

QPI Reset

(

66

h

+

99 h )

Device Initialization

&

Status Register Refresh

(

Non - Volatile Cells

)

6.1 SPI / QPI Operations

W25Q40EW

Figure 3. W25Q40EW Serial Flash Memory Operation Diagram

6.2 SPI OPERATIONS

6.2.1 Standard SPI Instructions

The W25Q40EW is accessed through an SPI compatible bus consisting of four signals: Serial Clock
(CLK), Chip Select (/CS), Serial Data Input (DI) and Serial Data Output (DO). Standard SPI instructions
use the DI input pin to serially write instructions, addresses or data to the device on the rising edge of
CLK. The DO output pin is used to read data or status from the device on the falling edge CLK.

SPI bus operation Mode 0 (0,0) and 3 (1,1) are supported. The primary difference between Mode 0 and
Mode 3 concerns the normal state of the CLK signal when the SPI bus master is in standby and data is
not being transferred to the Serial Flash. For Mode 0, the CLK signal is normally low on the falling and
rising edges of /CS. For Mode 3, the CLK signal is normally high on the falling and rising edges of /CS.

6.2.2 Dual SPI Instructions

The W25Q40EW supports Dual SPI operation when using the “Fast Read Dual Output (3Bh)” and “Fast
Read Dual I/O (BBh)” instructions. These instructions allow data to be transferred to or from the device at

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W25Q40EW

two to three times the rate of ordinary Serial Flash devices. The Dual SPI Read instructions are ideal for
quickly downloading code to RAM upon power-up (code-shadowing) or for executing non-speed-critical
code directly from the SPI bus (XIP). When using Dual SPI instructions, the DI and DO pins become
bidirectional I/O pins: IO0 and IO1.

6.2.3 Quad SPI Instructions

The W25Q40EW supports Quad SPI operation when using the “Fast Read Quad Output (6Bh)”, and “Fast
Read Quad I/O (EBh)” instructions. These instructions allow data to be transferred to or from the device
six to eight times the rate of ordinary Serial Flash. The Quad Read instructions offer a significant
improvement in continuous and random access transfer rates allowing fast code-shadowing to RAM or
execution directly from the SPI bus (XIP). When using Quad SPI instructions the DI and DO pins become
bidirectional IO0 and IO1, and the /WP and /HOLD pins become IO2 and IO3 respectively. Quad SPI
instructions require the non-volatile Quad Enable bit (QE) in Status Register-2 to be set.

6.3 QPI Instructions

The W25Q40EW supports Quad Peripheral Interface (QPI) operations only when the device is switched

from Standard/Dual/Quad SPI mode to QPI mode using the “Enter QPI (38h)” instruction. The typical SPI

protocol requires that the byte-long instruction code being shifted into the device only via DI pin in eight
serial clocks. The QPI mode utilizes all four IO pins to input the instruction code, thus only two serial
clocks are required. This can significantly reduce the SPI instruction overhead and improve system
performance in an XIP environment. Standard/Dual/Quad SPI mode and QPI mode are exclusive. Only

one mode can be active at any given time. “Enter QPI (38h)” and “Exit QPI (FFh)” instructions are used to

switch between these two modes. Upon power-up or after a software reset using “Reset (99h)” instruction,
the default state of the device is Standard/Dual/Quad SPI mode. To enable QPI mode, the non-volatile
Quad Enable bit (QE) in Status Register-2 is required to be set. When using QPI instructions, the DI and
DO pins become bidirectional IO0 and IO1, and the /WP and /HOLD pins become IO2 and IO3
respectively. See Figure 3 for the device operation modes.

6.3.1 Hold Function

For Standard SPI and Dual SPI operations, the /HOLD signal allows the W25Q40EW operation to be
paused while it is actively selected (when /CS is low). The /HOLD function may be useful in cases where
the SPI data and clock signals are shared with other devices. For example, consider if the page buffer
was only partially written when a priority interrupt requires use of the SPI bus. In this case the /HOLD
function can save the state of the instruction and the data in the buffer so programming can resume where
it left off once the bus is available again. The /HOLD function is only available for standard SPI and Dual
SPI operation, not during Quad SPI or QPI. The Quad Enable Bit QE in Status Register-2 is used to
determine if the pin is used as /HOLD pin or data I/O pin. When QE=0 (factory default), the pin is /HOLD,
when QE=1, the pin will become an I/O pin, /HOLD function is no longer available.

To initiate a /HOLD condition, the device must be selected with /CS low. A /HOLD condition will activate on
the falling edge of the /HOLD signal if the CLK signal is already low. If the CLK is not already low the
/HOLD condition will activate after the next falling edge of CLK. The /HOLD condition will terminate on the
rising edge of the /HOLD signal if the CLK signal is already low. If the CLK is not already low the /HOLD

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W25Q40EW

condition will terminate after the next falling edge of CLK. During a /HOLD condition, the Serial Data
Output (DO) is high impedance, and Serial Data Input (DI) and Serial Clock (CLK) are ignored. The Chip
Select (/CS) signal should be kept active low for the full duration of the /HOLD operation to avoid resetting
the internal logic state of the device.

6.4 WRITE PROTECTION

Applications that use non-volatile memory must take into consideration the possibility of noise and other
adverse system conditions that may compromise data integrity. To address this concern, the W25Q40EW
provides several means to protect the data from inadvertent writes.

6.4.1 Write Protect Features

 Device resets when VCC is below threshold
 Time delay write disable after Power-up
 Write enable/disable instructions and automatic write disable after erase or program
 Software and Hardware (/WP pin) write protection using Status Register
 Write Protection using Power-down instruction
 Lock Down write protection until next power-up

 One Time Program (OTP) write protection*

* Note: This feature is available upon special order. Please contact Winbond for details.

Upon power-up or at power-down, the W25Q40EW will maintain a reset condition while VCC is below the
threshold value of VWI, (See Power-up Timing and Voltage Levels and Figure 37). While reset, all
operations are disabled and no instructions are recognized. During power-up and after the VCC voltage
exceeds VWI, all program and erase related instructions are further disabled for a time delay of tPUW. This
includes the Write Enable, Page Program, Sector Erase, Block Erase, Chip Erase and the Write Status
Register instructions. Note that the chip select pin (/CS) must track the VCC supply level at power-up until
the VCC-min level and tVSL time delay is reached. If needed a pull-up resister on /CS can be used to
accomplish this.

After power-up the device is automatically placed in a write-disabled state with the Status Register Write
Enable Latch (WEL) set to a 0. A Write Enable instruction must be issued before a Page Program, Sector
Erase, Block Erase, Chip Erase or Write Status Register instruction will be accepted. After completing a
program, erase or write instruction the Write Enable Latch (WEL) is automatically cleared to a write­disabled state of 0.

Software controlled write protection is facilitated using the Write Status Register instruction and setting the
Status Register Protect (SRP, SRL) and Block Protect (CMP, SEC,TB, BP2, BP1 and BP0) bits. These
settings allow a portion as small as 4KB sector or the entire memory array to be configured as read only.
Used in conjunction with the Write Protect (/WP) pin, changes to the Status Register can be enabled or
disabled under hardware control. See Status Register section for further information. Additionally, the
Power-down instruction offers an extra level of write protection as all instructions are ignored except for
the Release Power-down instruction.

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W25Q40EW

7. STATUS REGISTERS AND INSTRUCTIONS

The Read Status Register-1 and Status Register-2 instructions can be used to provide status on the
availability of the Flash memory array, if the device is write enabled or disabled, the state of write
protection, Quad SPI setting, Security Register lock status and Erase/Program Suspend status. The Write
Status Register instruction can be used to configure the device write protection features, Quad SPI setting
and Security Register OTP lock. Write access to the Status Register is controlled by the state of the non­volatile Status Register Protect bits (SRP, SRL), the Write Enable instruction, and during Standard/Dual
SPI operations, the /WP pin.

7.1 STATUS REGISTERs

7.1.1 BUSY BUSY Status (BUSY) – Status Only

BUSY is a read only bit in the status register (S0) that is set to a 1 state when the device is executing a
Page Program, Quad Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register or
Erase/Program Security Register instruction. During this time the device will ignore further instructions
except for the Read Status Register and Erase/Program Suspend instruction (see tW, tPP, tSE, tBE, and
tCE in AC Characteristics). When the program, erase or write status/security register instruction has
completed, the BUSY bit will be cleared to a 0 state indicating the device is ready for further instructions.

7.1.2 Write Enable Latch Status (WEL) – Status Only

Write Enable Latch (WEL) is a read only bit in the status register (S1) that is set to 1 after executing a
Write Enable Instruction. The WEL status bit is cleared to 0 when the device is write disabled. A write
disable state occurs upon power-up or after any of the following instructions: Write Disable, Page
Program, Quad Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register, Erase
Security Register and Program Security Register.

7.1.3 Block Protect Bits (BP2, BP1, BP0) – Volatile/Non-Volatile Writable

The Block Protect Bits (BP2, BP1, BP0) are non-volatile read/write bits in the status register (S4, S3, and
S2) that provide Write Protection control and status. Block Protect bits can be set using the Write Status
Register Instruction (see tW in AC characteristics). All, none or a portion of the memory array can be
protected from Program and Erase instructions (see Status Register Memory Protection table). The
factory default setting for the Block Protection Bits is 0, none of the array protected.

7.1.4 Top/Bottom Block Protect (TB) – Volatile/Non-Volatile Writable

The non-volatile Top/Bottom bit (TB) controls if the Block Protect Bits (BP2, BP1, BP0) protect from the
Top (TB=0) or the Bottom (TB=1) of the array as shown in the Status Register Memory Protection table.
The factory default setting is TB=0. The TB bit can be set with the Write Status Register Instruction
depending on the state of the SRP and WEL bits.

7.1.5 Sector/Block Protect (SEC) – Volatile/Non-Volatile Writable

The non-volatile Sector/Block Protect bit (SEC) controls if the Block Protect Bits (BP2, BP1, BP0) protect
either 4KB Sectors (SEC=1) or 64KB Blocks (SEC=0) in the Top (TB=0) or the Bottom (TB=1) of the array
as shown in the Status Register Memory Protection table. The default setting is SEC=0.

Publication Release Date: August 18, 2018

- 13 - Preliminary-Revision J

W25Q40EW

SRP

/WP

Status

Protection

Description

0

X

Software

Protection

/WP pin has no control. The Status register can be
written to after a Write Enable instruction, WEL=1.

[Factory Default]

1

0

Hardware

Protected

When /WP pin is low the Status Register can not be

written to.

1

Hardware

Unprotected

When /WP pin is high the Status register can be

written to after a Write Enable instruction, WEL=1.

SRL

Status Register Lock

Description

0

Non-Lock

Status Register is unlocked

1

Lock-Down

(1)

(temporary/Volatile)

Status Register is locked by standard status
register write command and can not be written to

again until the next power-down, power-up cycle.

One Time Program

(2)

(Permanently/Non-Volatile)

Status Register is permanently locked by special

command flow

*

and can not be written to

7.1.6 Complement Protect (CMP) Volatile/Non-Volatile Writable

The Complement Protect bit (CMP) is a non-volatile read/write bit in the status register (S14). It is used in
conjunction with SEC, TB, BP2, BP1 and BP0 bits to provide more flexibility for the array protection. Once
CMP is set to 1, previous array protection set by SEC, TB, BP2, BP1 and BP0 will be reversed. For
instance, when CMP=0, a top 4KB sector can be protected while the rest of the array is not; when CMP=1,
the top 4KB sector will become unprotected while the rest of the array become read-only. Please refer to
the Status Register Memory Protection table for details. The default setting is CMP=0.

7.1.7 Status Register Protect (SRP, SRL) Volatile/Non-Volatile Writable

The Status Register Protect bits (SRP) are non-volatile read/write bits in the status register (S7). The SRP
bits control the method of write protection: software protection,

1. When SRL =1 , a power-down, power-up cycle will change SRL =0 state.

2. Special One Time Protection feature is available upon special flow; please contact Winbond for details

- 14 -

W25Q40EW

SRP SEC TB BP 2 BP1 BP0 WEL BUSY

TOP/BOTTOM PROTECT

WRITE ENABLE LATCH

S7 S6 S5 S4 S3 S2 S1 S0

STATUS REGISTER PROTECT

(Volatile/Non-Volatile Writable)

SECTOR PROTECT

BLOCK PROTECT BITS

ERASE/WRITE IN PROGRESS

(Volatile/Non-Volatile Writable)

(Status-Only)

(Status-Only)

(Volatile/Non-Volatile Writable)

(Volatile/Non-Volatile Writable)

7.1.8 Erase/Program Suspend Status (SUS) –Status Only

The Suspend Status bit is a read only bit in the status register (S15) that is set to 1 after executing a
Erase/Program Suspend (75h) instruction. The SUS status bit is cleared to 0 by Erase/Program Resume
(7Ah) instruction as well as a power-down, power-up cycle.

7.1.9 Security Register Lock Bits (LB[3:0]) – Volatile/Non-Volatile OTP Writable

The Security Register Lock Bits (LB3, LB2, LB1, LB0) are non-volatile One Time Program (OTP) bits in
Status Register (S13, S12, S11, S10) that provide the write protect control and status to the Security
Registers. The default state of LB[3:0] is 0, Security Registers are unlocked. LB3-0 can be set to 1
individually using the Write Status Register instruction. LB3-0 are One Time Programmable (OTP), once
it’s set to 1, the corresponding 256-Byte Security Register will become read-only permanently.

7.1.10 Quad Enable (QE) – Volatile/Non-Volatile Writable

The Quad Enable (QE) bit is a non-volatile read/write bit in the status register (S9) that allows Quad SPI
and QPI operation. When the QE bit is set to a 0 state (factory default), the /WP pin and /HOLD are
enabled. When the QE bit is set to a 1, the Quad IO2 and IO3 pins are enabled, and /WP and /HOLD
functions are disabled.

QE bit is required to be set to a 1 before issuing an “Enter QPI (38h)” to switch the device from

Standard/Dual/Quad SPI to QPI, otherwise the command will be ignored. When the device is in QPI mode,

QE bit will remain to be 1. A “Write Status Register” command in QPI mode cannot change QE bit from a

“1” to a “0”.

WARNING: If the /WP or /HOLD pins are tied directly to the power supply or ground during
standard SPI or Dual SPI operation, the QE bit should never be set to a 1.

Figure 3a. Status Register-1

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W25Q40EW

Figure 3b. Status Register-2

7.1.11 Reserved Bits – Non Functional

There are a few reserved Status Register bits that may be read out as a “0” or “1”. It is recommended to
ignore the values of those bits. During a “Write Status Register” instruction, the Reserved Bits can be

written as “0”, but there will not be any effects.

- 16 -

7.1.12 Status Register Memory Protection (CMP = 0)

STATUS REGISTER

(1)

W25Q40EW (4M-BIT) MEMORY PROTECTION

(2)

SEC

TB

BP2

BP1

BP0

BLOCK(S)

ADDRESSES

DENSITY

PORTION

X X 0 0 0

NONE

NONE

NONE

NONE

0 0 0 0 1 7 070000h – 07FFFFh

64KB

Upper 1/8

0 0 0 1 0

6 and 7

060000h – 07FFFFh

128KB

Upper 1/4

0 0 0 1 1

4 thru 7

040000h – 07FFFFh

256KB

Upper 1/2

0 1 0 0 1 0 000000h – 00FFFFh

64KB

Lower 1/8

0 1 0 1 0

0 and 1

000000h – 01FFFFh

128KB

Lower 1/4

0 1 0 1 1

0 thru 3

000000h – 03FFFFh

256KB

Lower 1/2

0 X 1 X X

0 thru 7

000000h – 07FFFFh

512KB

ALL

1 0 0 0 1 7 07F000h – 07FFFFh

4KB

Upper 1/128

1 0 0 1 0 7 07E000h – 07FFFFh

8KB

Upper 1/64

1 0 0 1 1 7 07C000h – 07FFFFh

16KB

Upper 1/32

1 0 1 0 X 7 078000h – 07FFFFh

32KB

Upper 1/16

1 0 1 1 0 7 078000h – 07FFFFh

32KB

Upper 1/16

1 1 0 0 1 0 000000h – 000FFFh

4KB

Lower 1/128

1 1 0 1 0

0

000000h – 001FFFh

8KB

Lower 1/64

1 1 0 1 1

0

000000h – 003FFFh

16KB

Lower 1/32

1 1 1 0 X

0

000000h – 007FFFh

32KB

Lower 1/16

1 1 1 1 0

0

000000h – 007FFFh

32KB

Lower 1/16

1 X 1 1 1

0 thru 7

000000h – 07FFFFh

512KB

ALL

W25Q40EW

Notes:

1. X = don’t care

2. If any Erase or Program command specifies a memory region that contains protected data portion, this
command will be ignored.

Publication Release Date: August 18, 2018

- 17 - Preliminary-Revision J

7.1.13 Status Register Memory Protection (CMP = 1)

STATUS REGISTER

(1)

W25Q40EW (4M-BIT) MEMORY PROTECTION

(2)

SEC

TB

BP2

BP1

BP0

BLOCK(S)

ADDRESSES

DENSITY

PORTION

X X 0 0 0

0 thru 7

000000h – 07FFFFh

512KB

ALL

0 0 0 0 1

0 thru 6

000000h – 06FFFFh

448KB

Lower 7/8

0 0 0 1 0

0 thru 5

000000h – 05FFFFh

384KB

Lower 3/4

0 0 0 1 1

0 thru 3

000000h – 03FFFFh

256KB

Lower 1/2

0 1 0 0 1

1 thru 7

010000h – 07FFFFh

448KB

Upper 7/8

0 1 0 1 0

2 thru 7

020000h – 07FFFFh

384KB

Upper 3/4

0 1 0 1 1

4 thru 7

040000h – 07FFFFh

256KB

Upper 1/2

0 X 1 X X

NONE

NONE

NONE

NONE

1 0 0 0 1

0 thru 7

000000h – 07EFFFh

508KB

Lower 127/128

1 0 0 1 0

0 thru 7

000000h – 07DFFFh

504KB

Lower 63/64

1 0 0 1 1

0 thru 7

000000h – 07BFFFh

496KB

Lower 31/32

1 0 1 0 X

0 thru 7

000000h – 077FFFh

480KB

Lower 15/16

1 0 1 1 0

0 thru 7

000000h – 077FFFh

480KB

Lower 15/16

1 1 0 0 1

0 thru 7

001000h – 07FFFFh

508KB

Upper 127/128

1 1 0 1 0

0 thru 7

002000h – 07FFFFh

504KB

Upper 63/64

1 1 0 1 1

0 thru 7

004000h – 07FFFFh

496KB

Upper 31/32

1 1 1 0 X

0 thru 7

008000h – 07FFFFh

480KB

Upper 15/16

1 1 1 1 0

0 thru 7

008000h – 07FFFFh

480KB

Upper 15/16

X X 1 1 1

NONE

NONE

NONE

NONE

W25Q40EW

Notes:

1. X = don’t care

2. If any Erase or Program command specifies a memory region that contains protected data portion, this
command will be ignored.

- 18 -

W25Q40EW

MANUFACTURER ID

(MF7-MF0)

Winbond Serial Flash

EFh

Device ID

(ID7-ID0)

(ID15-ID0)

Instruction

ABh, 90h, 92h, 94h

9Fh

W25Q40EW

12h

6013

7.1.14 INSTRUCTIONS

The instruction set of the W25Q40EW consists of thirty four basic instructions that are fully controlled
through the SPI bus (see Instruction Set table1-3). Instructions are initiated with the falling edge of Chip
Select (/CS). The first byte of data clocked into the DI input provides the instruction code. Data on the DI
input is sampled on the rising edge of clock with most significant bit (MSB) first.

The QPI instruction set of the W25Q40EW consists of 32 basic instructions that are fully controlled
through the SPI bus (see Instruction Set Table 3). Instructions are initiated with the falling edge of Chip
Select (/CS). The first byte of data clocked through IO[3:0] pins provides the instruction code. Data on all
four IO pins are sampled on the rising edge of clock with most significant bit (MSB) first. All QPI
instructions, addresses, data and dummy bytes are using all four IO pins to transfer every byte of data with
every two serial clocks (CLK).

Instructions vary in length from a single byte to several bytes and may be followed by address bytes, data

bytes, dummy bytes (don’t care), and in some cases, a combination. Instructions are completed with the

rising edge of edge /CS. Clock relative timing diagrams for each instruction are included in figures 4
through 36. All read instructions can be completed after any clocked bit. However, all instructions that
Write, Program or Erase must complete on a byte boundary (/CS driven high after a full 8-bits have been
clocked) otherwise the instruction will be ignored. This feature further protects the device from inadvertent
writes. Additionally, while the memory is being programmed or erased, or when the Status Register is
being written, all instructions except for Read Status Register will be ignored until the program or erase
cycle has completed.

7.1.15 Manufacturer and Device Identification

Publication Release Date: August 18, 2018

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W25Q40EW

Data Input Output

Byte 1

Byte 2

Byte 3

Byte 4

Byte 5

Byte 6

Byte 7

Number of Clock

(1-1-1)

8 8 8 8 8 8 8

Write Enable

06h

Volatile SR Write Enable

50h

Write Disable

04h

Release Power-down / ID

ABh

Dummy

Dummy

Dummy

(ID7-ID0)

(2)

Manufacturer/Device ID

90h

Dummy

Dummy

00h

(MF7-MF0)

(ID7-ID0)

JEDEC ID

9Fh

(MF7-MF0)

(ID15-ID8)

(ID7-ID0)

Read Unique ID

4Bh

Dummy

Dummy

Dummy

Dummy

(UID63-0)

Read Data

03h

A23-A16

A15-A8

A7-A0

(D7-D0)

Fast Read

0Bh

A23-A16

A15-A8

A7-A0

Dummy

(D7-D0)

Page Program

02h

A23-A16

A15-A8

A7-A0

D7-D0

D7-D0

(3)

Sector Erase (4KB)

20h

A23-A16

A15-A8

A7-A0

Block Erase (32KB)

52h

A23-A16

A15-A8

A7-A0

Block Erase (64KB)

D8h

A23-A16

A15-A8

A7-A0

Chip Erase

C7h/60h

Read Status Register-1

05h

(S7-S0)

(2)

Write Status Register-1

(4)

01h

(S7-S0)

(4)

Read Status Register-2

35h

(S15-S8)

(2)

Write Status Register-2

31h

(S15-S8)

Read SFDP Register

5Ah

A23-A16

A15-A8

A7-A0

Dummy

(D7-D0)

Erase Security Register

(5)

44h

A23-A16

A15-A8

A7-A0

Program Security Register

(5)

42h

A23-A16

A15-A8

A7-A0

D7-D0

D7-D0

(5)

Read Security Register

(5)

48h

A23-A16

A15-A8

A7-A0

Dummy

(D7-D0)

Erase / Program Suspend

(6)

75h

Erase / Program Resume

(6)

7Ah

Power-down

B9h

Enter QPI Mode

38h

Enable Reset

66h

Reset Device

99h

7.1.16 Instruction Set Table 1 (Standard SPI Instructions)

(1)

- 20 -

7.1.17 Instruction Set Table 2 (Dual/Quad SPI Instructions)

Data Input Output

Byte 1

Byte 2

Byte 3

Byte 4

Byte 5

Byte 6

Byte 7

Byte 8

Byte 9

Number of Clock

(1-1-2)

8 8 8 8 4 4 4 4 4

Fast Read Dual Output

3Bh

A23-A16

A15-A8

A7-A0

Dummy

Dummy

(D7-D0)

(7)

Number of Clock(1-2-2)

8 4 4 4 4 4 4

4

4

Fast Read Dual I/O

BBh

A23-A16

(6)

A15-A8

(6)

A7-A0

(6)

Dummy

(14)

(D7-D0)

(7)

Mftr./Device ID Dual I/O

92h

A23-A16

(6)

A15-A8

(6)

00

(6)

Dummy

(14)

(MF7-MF0)

(ID7-ID0)

(7)

Number of Clock(1-1-4)

8 8 8 8 2 2 2 2 2

Quad Input Page Program

32h

A23-A16

A15-A8

A7-A0

(D7-D0)

(9)

(D7-D0)

(3)

…

Fast Read Quad Output

6Bh

A23-A16

A15-A8

A7-A0

Dummy

Dummy

Dummy

Dummy

(D7-D0)

(10)

Number of Clock(1-4-4)

8

2

(8)

2

(8)

2

(8)

2 2 2 2

2

Mftr./Device ID Quad I/O

94h

A23-A16

A15-A8

00

Dummy

(14)

Dummy

Dummy

(MF7-MF0)

(ID7-ID0)

Fast Read Quad I/O

EBh

A23-A16

A15-A8

A7-A0

Dummy

(14)

Dummy

Dummy

(D7-D0)

Set Burst with Wrap

77h

Dummy

Dummy

Dummy

W8-W0

W25Q40EW

Publication Release Date: August 18, 2018

- 21 - Preliminary-Revision J

W25Q40EW

Data Input Output

Byte 1

Byte 2

Byte 3

Byte 4

Byte 5

Byte 6

Byte 7

Number of Clock

(4-4-4)

2 2 2 2 2 2 2

Write Enable

06h

Volatile SR Write Enable

50h

Write Disable

04h

Release Power-down / ID

ABh

Dummy

Dummy

Dummy

(ID7-ID0)

(2)

Manufacturer/Device ID

90h

Dummy

Dummy

00h

(MF7-MF0)

(ID7-ID0)

JEDEC ID

9Fh

(MF7-MF0)

(ID15-ID8)

(ID7-ID0)

Set Read Parameters

C0h

P7-P0

Fast Read

0Bh

A23-A16

A15-A8

A7-A0

Dummy

(12)

(D7-D0)

…

Burst Read with Wrap

(5,6)

0Ch

A23-A16

A15-A8

A7-A0

Dummy

(12)

(D7-D0)

…

Fast Read Quad I/O

EBh

A23-A16

A15-A8

A7-A0

M7-M0

(12)

(D7-D0)

…

Page Program

02h

A23-A16

A15-A8

A7-A0

D7-D0

(9)

D7-D0

(3)

…

Sector Erase (4KB)

20h

A23-A16

A15-A8

A7-A0

Block Erase (32KB)

52h

A23-A16

A15-A8

A7-A0

Block Erase (64KB)

D8h

A23-A16

A15-A8

A7-A0

Chip Erase

C7h/60h

Read Status Register-1

05h

(S7-S0)

(2)

Write Status Register-1

(4)

01h

(S7-S0)

(4)

Read Status Register-2

35h

(S15-S8)

(2)

Write Status Register-2

31h

(S15-S8)

Erase / Program Suspend

75h

Erase / Program Resume

7Ah

Power-down

B9h

Enable Reset

66h

Reset Device

99h

Exit QPI Mode

FFh

7.1.18 Instruction Set Table 3 (QPI Instructions)

(1)

- 22 -

W25Q40EW

Note:

1. Data bytes are shifted with Most Significant Bit first. Byte fields with data in parenthesis “D7-D0” indicate

data output from the device on either 1, 2 or 4 IO pins. . “D7 -D0” indicates single I/O pin; “D7-D0 /2”
indicates 2 I/O pins; “D7-D0 /4” indicates 4 I/O pins.

2. The Status Register contents and Device ID will repeat continuously until /CS terminates the instruction.

3. At least one byte of data input is required for Page Program, Quad Page Program and Program Security
Registers, up to 256 bytes of data input. If more than 256 bytes of data are sent to the device, the
addressing will wrap to the beginning of the page and overwrite previously sent data.

4. Write Status Register-1 (01h) can also be used to program Status Register-1&2, see section 8.2.5.

5. Security Register Address:
Security Register 1: A23-16 = 00h; A15-8 = 10h; A7-0 = byte address
Security Register 2: A23-16 = 00h; A15-8 = 20h; A7-0 = byte address
Security Register 3: A23-16 = 00h; A15-8 = 30h; A7-0 = byte address

6. Dual SPI address input format:
IO0 = A22, A20, A18, A16, A14, A12, A10, A8 A6, A4, A2, A0, M6, M4, M2, M0
IO1 = A23, A21, A19, A17, A15, A13, A11, A9 A7, A5, A3, A1, M7, M5, M3, M1

7. Dual SPI data input/output format:
IO0 = (D6, D4, D2, D0)
IO1 = (D7, D5, D3, D1)

8. Quad SPI address input format: Set Burst with Wrap input format:
IO0 = A20, A16, A12, A8, A4, A0, M4, M0 IO0 = x, x, x, x, x, x, W4, x
IO1 = A21, A17, A13, A9, A5, A1, M5, M1 IO1 = x, x, x, x, x, x, W5, x

IO2 = A22, A18, A14, A10, A6, A2, M6, M2 IO2 = x, x, x, x, x, x, W6, x
IO3 = A23, A19, A15, A11, A7, A3, M7, M3 IO3 = x, x, x, x, x, x, x, x

9. Quad SPI data input/output format:
IO0 = (D4, D0, …..)
IO1 = (D5, D1, …..)
IO2 = (D6, D2, …..)
IO3 = (D7, D3, …..)

10. Fast Read Quad I/O data output format:
IO0 = (x, x, x, x, D4, D0, D4, D0)
IO1 = (x, x, x, x, D5, D1, D5, D1)
IO2 = (x, x, x, x, D6, D2, D6, D2)
IO3 = (x, x, x, x, D7, D3, D7, D3)

11. QPI Command, Address, Data input/output format:
CLK # 0 1 2 3 4 5 6 7 8 9 10 11
IO0 = C4, C0, A20, A16, A12, A8, A4, A0, D4, D0, D4, D0
IO1 = C5, C1, A21, A17, A13, A9, A5, A1, D5, D1, D5, D1
IO2 = C6, C2, A22, A18, A14, A10, A6, A2, D6, D2, D6, D2
IO3 = C7, C3, A23, A19, A15, A11, A7, A3, D7, D3, D7, D3

12. The number of dummy clocks for QPI Fast Read, QPI Fast Read Quad I/O & QPI Burst Read with Wrap is
controlled by read parameter P7 – P4.

13. The wrap around length for QPI Burst Read with Wrap is controlled by read parameter P3 – P0.

14. The first dummy is M7-M0 should be set to Fxh

Publication Release Date: August 18, 2018

- 23 - Preliminary-Revision J

W25Q40EW

/CS

CLK

DI

(IO0)

DO

(IO1)

Mode 0

Mode 3 0 1 2 3 4 5 6 7

Mode 0

Mode 3

Instruction (06h)

High Impedance

/CS

CLK

Mode 0

Mode 3 0 1

Mode 0

Mode 3

IO

0

IO

1

IO

2

IO

3

06h

Instruction

/CS

CLK

DI

(IO0)

DO

(IO1)

Mode 0

Mode 3 0 1 2 3 4 5 6 7

Mode 0

Mode 3

Instruction (50h)

High Impedance

/CS

CLK

Mode 0

Mode 3 0 1

Mode 0

Mode 3

IO

0

IO

1

IO

2

IO

3

50h

Instruction

7.2 Instruction Descriptions

7.2.1 Write Enable (06h)

The Write Enable instruction (Figure 4) sets the Write Enable Latch (WEL) bit in the Status Register to a

1. The WEL bit must be set prior to every Page Program, Quad Page Program, Sector Erase, Block
Erase, Chip Erase, Write Status Register and Erase/Program Security Registers instruction. The Write
Enable instruction is entered by driving /CS low, shifting the instruction code “06h” into the Data Input (DI)
pin on the rising edge of CLK, and then driving /CS high.

Figure 5. Write Enable Instruction for SPI Mode (left) or QPI Mode (right)

7.2.2 Write Enable for Volatile Status Register (50h)

The non-volatile Status Register bits described in section 8.1 can also be written to as volatile bits. This
gives more flexibility to change the system configuration and memory protection schemes quickly without
waiting for the typical non-volatile bit write cycles or affecting the endurance of the Status Register non­volatile bits. To write the volatile values into the Status Register bits, the Write Enable for Volatile Status
Register (50h) instruction must be issued prior to a Write Status Register (01h) instruction. Write Enable
for Volatile Status Register instruction (Figure 5) will not set the Write Enable Latch (WEL) bit, it is only
valid for the Write Status Register instruction to change the volatile Status Register bit values.

Figure 6. Write Enable for Volatile Status Register Instruction for SPI Mode (left) or QPI Mode (right)

- 24 -

W25Q40EW

/CS

CLK

DI

(IO0)

DO

(IO1)

Mode 0

Mode 3 0 1 2 3 4 5 6 7

Mode 0

Mode 3

Instruction (04h)

High Impedance

/CS

CLK

Mode 0

Mode 3 0 1

Mode 0

Mode 3

IO

0

IO

1

IO

2

IO

3

04h

Instruction

7.2.3 Write Disable (04h)

The Write Disable instruction (Figure 6) resets the Write Enable Latch (WEL) bit in the Status Register to
a 0. The Write Disable instruction is entered by driving /CS low, shifting the instruction code “04h” into the
DI pin and then driving /CS high. Note that the WEL bit is automatically reset after Power-up and upon
completion of the Write Status Register, Erase/Program Security Registers, Page Program, Quad Page
Program, Sector Erase, Block Erase and Chip Erase instructions.

Write Disable instruction can also be used to invalidate the Write Enable for Volatile Status Register
instruction.

Figure 7. Write Disable Instruction for SPI Mode (left) or QPI Mode (right)

Publication Release Date: August 18, 2018

- 25 - Preliminary-Revision J

W25Q40EW

/CS

CLK

DI

(IO0)

DO

(IO1)

Mode 0

Mode 3 0 1 2 3 4 5 6 7

Instruction (05h/35h/15h)

High Impedance

8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7

Status Register-1/2/3 out Status Register-1/2/3 out

* *

= MSB

*

/CS

CLK

Mode 0

Mode 3 0 1

IO

0

IO

1

IO

2

IO

3

05h/35h/15h

2 3 4 5

4 0 4 0

5 1

6 2

7 3

5 1

6 2

7 3

4

5

6

7

SR-1/2/3

out

SR-1/2/3

out

Instruction

7.2.4 Read Status Register-1(05h) and Read Status Register-2(35h)

The Read Status Register instructions allow the 8-bit Status Registers to be read. The instruction is
entered by driving /CS low and shifting the instruction code “05h” for Status Register-1 or “35h” for
Status Register-2 into the DI pin on the rising edge of CLK. The status register bits are then shifted out on
the DO pin at the falling edge of CLK with most significant bit (MSB) first as shown in figure 7. The Status
Register bits are shown in figure 3a and 3b and include the BUSY, WEL, BP2-BP0, TB, SEC, SRP, SRL,
QE, LB[3:0], CMP and SUS bits (see Status Register section earlier in this datasheet).

The Read Status Register instruction may be used at any time, even while a Program, Erase or Write
Status Register cycle is in progress. This allows the BUSY status bit to be checked to determine when the
cycle is complete and if the device can accept another instruction. The Status Register can be read
continuously, as shown in Figure 7. The instruction is completed by driving /CS high.

Figure 7. Read Status Register Instruction Sequence Diagram

Figure 8b. Read Status Register Instruction (QPI Mode)

- 26 -

W25Q40EW

/CS

CLK

DI

(IO0)

DO

(IO1)

Mode 0

Mode 3 0 1 2 3 4 5 6 7

Instruction

(01h/31h/11h)

High Impedance

8 9 10 11 12 13 14 15

7 6 5 4 3 2 1 0

Register-1/2/3 in

Mode 0

Mode 3

*

= MSB

*

7.2.5 Write Status Register-1 (01h), Status Register-2 (31h)

The Write Status Register instruction allows the Status Registers to be written. The writable Status
Register bits include: SRP, SEC, TB, BP[2:0] in Status Register-1; CMP, LB[3:0], QE, SRL in Status
Register-2. All other Status Register bit locations are read-only and will not be affected by the Write Status
Register instruction. LB[3:0] are non-volatile OTP bits, once it is set to 1, it cannot be cleared to 0.

To write non-volatile Status Register bits, a standard Write Enable (06h) instruction must previously have
been executed for the device to accept the Write Status Register instruction (Status Register bit WEL
must equal 1). Once write enabled, the instruction is entered by driving /CS low, sending the instruction
code “01h/31h/11h”, and then writing the status register data byte as illustrated in Figure 9a & 9b.

To write volatile Status Register bits, a Write Enable for Volatile Status Register (50h) instruction must
have been executed prior to the Write Status Register instruction (Status Register bit WEL remains 0).
However, SRL and LB[3:0] cannot be changed from “1” to “0” because of the OTP protection for these
bits. Upon power off or the execution of a Software/Hardware Reset, the volatile Status Register bit values
will be lost, and the non-volatile Status Register bit values will be restored.

During non-volatile Status Register write operation (06h combined with 01h/31h/11h), after /CS is driven
high, the self-timed Write Status Register cycle will commence for a time duration of tW (See AC
Characteristics). While the Write Status Register cycle is in progress, the Read Status Register instruction
may still be accessed to check the status of the BUSY bit. The BUSY bit is a 1 during the Write Status
Register cycle and a 0 when the cycle is finished and ready to accept other instructions again. After the
Write Status Register cycle has finished, the Write Enable Latch (WEL) bit in the Status Register will be
cleared to 0.

During volatile Status Register write operation (50h combined with 01h/31h/11h), after /CS is driven high,
the Status Register bits will be refreshed to the new values within the time period of tSHSL2 (See AC
Characteristics). BUSY bit will remain 0 during the Status Register bit refresh period.

The Write Status Register instruction can be used in both SPI mode and QPI mode. However, the QE bit
cannot be written to when the device is in the QPI mode, because QE=1 is required for the device to enter
and operate in the QPI mode

Refer to section 7.1 for Status Register descriptions.

Figure 9a. Write Status Register-1/2 Instruction (SPI Mode)

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Publication Release Date: August 18, 2018

W25Q40EW

/CS

CLK

Mode 0

Mode 3 0 1

IO

0

IO

1

IO

2

IO

3

01/31/11h

2 3

4 0

5 1

6 2

7 3

SR1/2/3

in

Mode 0

Mode 3

Instruction

/CS

CLK

DI

(IO0)

DO

(IO1)

Mode 0

Mode 3 0 1 2 3 4 5 6 7

Instruction (01h)

High Impedance

8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8

Status Register 1 in Status Register 2 in

Mode 0

Mode 3

* *

= MSB

*

/CS

CLK

Mode 0

Mode 3 0 1

IO

0

IO

1

IO

2

IO

3

01h

2 3 4 5

4 0 12 8

5 1

6 2

7 3

13 9

14 10

15 11

SR1 in SR2 in

Mode 0

Mode 3

Instruction

Figure 9b. Write Status Register-1/2 Instruction (QPI Mode)

The W25Q40EW is also backward compatible to Winbond’s previous generations of serial flash
memories, in which the Status Register-1&2 can be written using a single “Write Status Register-1 (01h)”
command. To complete the Write Status Register-1&2 instruction, the /CS pin must be driven high after
the sixteenth bit of data that is clocked in as shown in Figure 9c. If /CS is driven high after the eighth clock,
the Write Status Register-1 (01h) instruction will only program the Status Register-1, the Status Register-2
will not be affected (Previous generations will clear CMP and QE bits).

Figure 9c. Write Status Register-1/2 Instruction (SPI Mode)

Figure 9d. Write Status Register-1/2 Instruction (QPI Mode)

- 28 -

W25Q40EW

/CS

CLK

DI

(IO0)

DO

(IO1)

Mode 0

Mode 3 0 1 2 3 4 5 6 7

Instruction (03h)

High Impedance

8 9 10 28 29 30 31 32 33 34 35 36 37 38 39

7 6 5 4 3 2 1 0 7

24-Bit Address

23 22 21 3 2 1 0

Data Out 1

*

*

= MSB

*

7.2.6 Read Data (03h)

The Read Data instruction allows one or more data bytes to be sequentially read from the memory. The
instruction is initiated by driving the /CS pin low and then shifting the instruction code “03h” followed by a
24-bit address (A23-A0) into the DI pin. The code and address bits are latched on the rising edge of the
CLK pin. After the address is received, the data byte of the addressed memory location will be shifted out
on the DO pin at the falling edge of CLK with most significant bit (MSB) first. The address is automatically
incremented to the next higher address after each byte of data is shifted out allowing for a continuous
stream of data. This means that the entire memory can be accessed with a single instruction as long as
the clock continues. The instruction is completed by driving /CS high.

The Read Data instruction sequence is shown in figure 10. If a Read Data instruction is issued while an
Erase, Program or Write cycle is in process (BUSY=1) the instruction is ignored and will not have any
effects on the current cycle. The Read Data instruction allows clock rates from D.C. to a maximum of fR
(see AC Electrical Characteristics).

Figure 10. Read Data Instruction Sequence Diagram

- 29 - Preliminary-Revision J

Publication Release Date: August 18, 2018

W25Q40EW

/CS

CLK

DI

(IO0)

DO

(IO1)

Mode 0

Mode 3 0 1 2 3 4 5 6 7

Instruction (0Bh)

High Impedance

8 9 10 28 29 30 31

24-Bit Address

23 22 21 3 2 1 0

Data Out 1

*

/CS

CLK

DI

(IO0)

DO

(IO1)

32 33 34 35 36 37 38 39

Dummy Clocks

High Impedance

40 41 42 44 45 46 47 48 49 50 51 52 53 54 55

7 6 5 4 3 2 1 0 7

Data Out 2

*

7 6 5 4 3 2 1 0

*

4331

0

= MSB

*

7.2.7 Fast Read (0Bh)

The Fast Read instruction is similar to the Read Data instruction except that it can operate at the highest
possible frequency of FR (see AC Electrical Characteristics). This is accomplished by adding eight
“dummy” clocks after the 24-bit address as shown in figure 11. The dummy clocks allow the devices
internal circuits additional time for setting up the initial address. During the dummy clocks the data value
on the DO pin is a “don’t care”.

Figure 11. Fast Read Instruction Sequence Diagram(SPI Mode)

- 30 -

W25Q40EW

/CS

CLK

Mode 0

Mode 3 0 1

IO

0

IO

1

IO

2

IO

3

0Bh

2 3 4 5

20 16 12 8

21 17

22 18

23 19

13 9

14 10

15 11

A23-16

6 7 8 9

4 0

5 1

6 2

7 3

A15-8 A7-0

Dummy*

Byte 1 Byte 2

4 0

5 1

6 2

7 3

4 0

5 1

6 2

7 3

4 0

5 1

6 2

7 3

10 11 12 13

4

5

6

7

IOs switch from
Input to Output

* "Set Read Parameters" instruction (C0h) can set

the number of dummy clocks.

Instruction

Fast Read (0Bh) in QPI Mode

The Fast Read instruction is also supported in QPI mode. When QPI mode is enabled, the number of
dummy clocks is configured by the “Set Read Parameters (C0h)” instruction to accommodate a wide
range of applications with different needs for either maximum Fast Read frequency or minimum data
access latency. Depending on the Read Parameter Bits P[5:4] setting, the number of dummy clocks can
be configured as either 2, 4, 6 or 8. The default number of dummy clocks upon power up or after a Reset
instruction is 2.

Figure 16b. Fast Read Instruction (QPI Mode)

Publication Release Date: August 18, 2018

- 31 - Preliminary-Revision J

W25Q40EW

/CS

CLK

DI

(IO0)

DO

(IO1)

Mode 0

Mode 3 0 1 2 3 4 5 6 7

Instruction (3Bh)

High Impedance

8 9 10 28 29 30

32 33 34 35 36 37 38 39

6 4 2 0

24-Bit Address

23 22 21 3 2 1 0

*

*

31

31

/CS

CLK

DI

(IO0)

DO

(IO1)

Dummy Clocks

0

40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55

7 5 3 1

High Impedance

6 4 2 0

7 5 3 1

6 4 2 0

7 5 3 1

6 4 2 0

7 5 3 1

IO0 switches from
Input to Output

6

7

Data Out 1

*

Data Out 2

*

Data Out 3

*

Data Out 4

= MSB

*

7.2.8 Fast Read Dual Output (3Bh)

The Fast Read Dual Output (3Bh) instruction is similar to the standard Fast Read (0Bh) instruction except
that data is output on two pins; IO0 and IO1. This allows data to be transferred from the W25Q40EW at
twice the rate of standard SPI devices. The Fast Read Dual Output instruction is ideal for quickly
downloading code from Flash to RAM upon power-up or for applications that cache code-segments to
RAM for execution.

Similar to the Fast Read instruction, the Fast Read Dual Output instruction can operate at the highest
possible frequency of FR (see AC Electrical Characteristics). This is accomplished by adding eight
“dummy” clocks after the 24-bit address as shown in figure 12. The dummy clocks allow the device's
internal circuits additional time for setting up the initial address. The input data during the dummy clocks is

“don’t care”. However, the IO

clock.

pin should be high-impedance prior to the falling edge of the first data out

0

Figure 12. Fast Read Dual Output Instruction Sequence Diagram

- 32 -

W25Q40EW

/CS

CLK

Mode 0

Mode 3 0 1 2 3 4 5 6 7

Instruction (6Bh)

High Impedance

8 9 10 28 29 30

32 33 34 35 36 37 38 39

4 0

24-Bit Address

23 22 21 3 2 1 0

*

31

31

/CS

CLK

Dummy Clocks

0

40 41 42 43 44 45 46 47

5 1

High Impedance

4

5

Byte 1

High Impedance

High Impedance

6 2

7 3

High Impedance

6

7

High Impedance

4 0

5 1

6 2

7 3

4 0

5 1

6 2

7 3

4 0

5 1

6 2

7 3

Byte 2 Byte 3 Byte 4

IO0 switches from
Input to Output

IO

0

IO

1

IO

2

IO

3

IO

0

IO

1

IO

2

IO

3

= MSB

*

7.2.9 Fast Read Quad Output (6Bh)

The Fast Read Quad Output (6Bh) instruction is similar to the Fast Read Dual Output (3Bh) instruction
except that data is output on four pins, IO0, IO1, IO2, and IO3. A Quad enable of Status Register-2 must be
executed before the device will accept the Fast Read Quad Output Instruction (Status Register bit QE
must equal 1). The Fast Read Quad Output Instruction allows data to be transferred from the W25Q40EW
at four times the rate of standard SPI devices.

The Fast Read Quad Output instruction can operate at the highest possible frequency of FR (see AC
Electrical Characteristics). This is accomplished by adding eight “dummy” clocks after the 24-bit address
as shown in figure 13. The dummy clocks allow the device's internal circuits additional time for setting up
the initial address. The input data during the dummy clocks is “don’t care”. However, the IO pins should be
high-impedance prior to the falling edge of the first data out clock.

Figure 13. Fast Read Quad Output Instruction Sequence Diagram

- 33 - Preliminary-Revision J

Publication Release Date: August 18, 2018

W25Q40EW

/CS

CLK

DI

(IO0)

DO

(IO1)

Mode 0

Mode 3 0 1 2 3 4 5 6 7

Instruction (BBh)

8 9 10 12 13 14

24 25 26 27 28 29 30 31

6 4 2 0

*

*

23

/CS

CLK

DI

(IO0)

DO

(IO1)

0

32 33 34 35 36 37 38 39

7 5 3 1

*

6 4 2 0

7 5 3 1

6 4 2 0

7 5 3 1

6 4 2 0

7 5 3 1

* *

IOs switch from
Input to Output

6

7

22 20 18 16

23 21 19 17

14 12 10 8

15 13 11 9

6 4 2 0

7 5 3 1

6 4 2 0

7 5 3 1

11 15 16 17 18 20 21 2219 23

1

A23-16 A15-8 A7-0 M7-0

Byte 1 Byte 2 Byte 3 Byte 4

= MSB

*

*

7.2.10 Fast Read Dual I/O (BBh)

The Fast Read Dual I/O (BBh) instruction allows for improved random access while maintaining two IO
pins, IO0 and IO1. It is similar to the Fast Read Dual Output (3Bh) instruction but with the capability to input
the Address bits (A23-0) two bits per clock. This reduced instruction overhead may allow for code
execution (XIP) directly from the Dual SPI in some applications.

Figure 14a. Fast Read Dual I/O Instruction Sequence (Initial instruction or previous M5-4  10)

- 34 -

W25Q40EW

M7-0

/CS

CLK

Mode 0

Mode 3 0 1

IO

0

IO

1

IO

2

IO

3

2 3 4 5

20 16 12 8

21 17

22 18

23 19

13 9

14 10

15 11

A23-16

6 7 8 9

4 0

5 1

6 2

7 3

A15-8 A7-0

Byte 1 Byte 2

4 0

5 1

6 2

7 3

4 0

5 1

6 2

7 3

4 0

5 1

6 2

7 3

10 11 12 13 14

4

5

6

7

IOs switch from
Input to Output

Byte 3

15 16 17 18 19 20 21 22 23

Dummy Dummy

Instruction (EBh)

7.2.11 Fast Read Quad I/O (EBh)

The Fast Read Quad I/O (EBh) instruction is similar to the Fast Read Dual I/O (BBh) instruction except
that address and data bits are input and output through four pins IO0, IO1, IO2 and IO3 and four Dummy
clock are required prior to the data output. The Quad I/O dramatically reduces instruction overhead
allowing faster random access for code execution (XIP) directly from the Quad SPI. The Quad Enable bit
(QE) of Status Register-2 must be set to enable the Fast Read Quad I/O Instruction.

Fast Read Quad I/O with “8/16/32/64-Byte Wrap Around”

The Fast Read Quad I/O instruction can also be used to access a specific portion within a page by issuing
a “Set Burst with Wrap” command prior to EBh. The “Set Burst with Wrap” command can either enable or
disable the “Wrap Around” feature for the following EBh commands. When “Wrap Around” is enabled, the
data being accessed can be limited to either a 8, 16, 32 or 64-byte section of a 256-byte page. The output
data starts at the initial address specified in the instruction, once it reaches the ending boundary of the
8/16/32/64-byte section, the output will wrap around to the beginning boundary automatically until /CS is
pulled high to terminate the command.

The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and then
fill the cache afterwards within a fixed length (8/16/32/64-byte) of data without issuing multiple read
commands.

The “Set Burst with Wrap” instruction allows three “Wrap Bits”, W6-4 to be set. The W4 bit is used to
enable or disable the “Wrap Around” operation while W6-5 are used to specify the length of the wrap

around section within a page. See 7.2.18 for detail descriptions.

Figure 15a. Fast Read Quad I/O Instruction Sequence (Initial instruction or previous M5-4  10)

Publication Release Date: August 18, 2018

- 35 - Preliminary-Revision J

W25Q40EW

M7-0*

/CS

CLK

Mode 0

Mode 3 0 1

IO

0

IO

1

IO

2

IO

3

EBh

2 3 4 5

20 16 12 8

21 17

22 18

23 19

13 9

14 10

15 11

A23-16

6 7 8 9

4 0

5 1

6 2

7 3

A15-8 A7-0

Byte 1 Byte 2

4 0

5 1

6 2

7 3

4 0

5 1

6 2

7 3

4 0

5 1

6 2

7 3

10 11 12 13 14

4

5

6

7

IOs switch from
Input to Output

* "Set Read Parameters" instruction (C0h) can

set the number of dummy clocks.

Byte 3

Instruction

Fast Read Quad I/O (EBh) in QPI Mode

The Fast Read Quad I/O instruction is also supported in QPI mode, as shown in Figure 19c. When QPI
mode is enabled, the number of dummy clocks is configured by the “Set Read Parameters (C0h)”
instruction to accommodate a wide range of applications with different needs for either maximum Fast
Read frequency or minimum data access latency. Depending on the Read Parameter Bits P[5:4] setting,
the number of dummy clocks can be configured as either 2, 4, 6 or 8. The default number of dummy
clocks upon power up or after a Reset instruction is 2.

“Wrap Around” feature is not available in QPI mode for Fast Read Quad I/O instruction. To perform a read

operation with fixed data length wrap around in QPI mode, a dedicated “Burst Read with Wrap” (0Ch)

instruction must be used. Please refer to 8.2.45 for details.

Figure 24c. Fast Read Quad I/O Instruction (Initial instruction or previous M5-410, QPI Mode)

- 36 -

W25Q40EW

W6, W5

W4 = 0

W4 =1 (DEFAULT)

Wrap Around

Wrap Length

Wrap Around

Wrap Length

0 0

Yes

8-byte

No

N/A

0 1

Yes

16-byte

No

N/A

1 0

Yes

32-byte

No

N/A

1 1

Yes

64-byte

No

N/A

Wrap Bit

/CS

CLK

Mode 0

Mode 3 0 1

IO

0

IO

1

IO

2

IO

3

2 3 4 5

X X

X X

X X

X X

don't
care

6 7 8 9

don't

care

don't
care

10 11 12 13 14 15

Instruction (77h)

Mode 0

Mode 3

X X

X X

X X

X X

X X

X X

X X

X X

w4 X

w5 X

w6 X

X X

7.2.12 Set Burst with Wrap (77h)

The Set Burst with Wrap (77h) instruction is used in conjunction with “Fast Read Quad I/O” and “Word
Read Quad I/O” instructions to access a fixed length of 8/16/32/64-byte section within a 256-byte page.
Certain applications can benefit from this feature and improve the overall system code execution
performance.

Similar to a Quad I/O instruction, the Set Burst with Wrap instruction is initiated by driving the /CS pin low
and then shifting the instruction code “77h” followed by 24 dummy bits and 8 “Wrap Bits”, W7-0. The
instruction sequence is shown in figure 17. Wrap bit W7 and the lower nibble W3-0 are not used.

Once W6-4 is set by a Set Burst with Wrap instruction, all the following “Fast Read Quad I/O” and “Word

Read Quad I/O” instructions will use the W6-4 setting to access the 8/16/32/64-byte section within any

page. To exit the “Wrap Around” function and return to normal read operation, another Set Burst with

Wrap instruction should be issued to set W4 = 1. The default value of W4 upon power on is 1. In the case
of a system Reset while W4 = 0, it is recommended that the controller issues a Set Burst with Wrap
instruction to reset W4 = 1 prior to any normal Read instructions since W25Q40EW does not have a
hardware Reset Pin.

In QPI mode, the “Burst Read with Wrap (0Ch)” instruction should be used to perform the Read operation
with “Wrap Around” feature. The Wrap Length set by W5-4 in Standard SPI mode is still valid in QPI mode
and can also be re-configured by “Set Read Parameters (C0h)” instruction. Refer to 8.2.44 and 8.2.45 for
details.

Figure 17. Set Burst with Wrap Instruction Sequence

Publication Release Date: August 18, 2018

- 37 - Preliminary-Revision J

W25Q40EW

/CS

CLK

DI

(IO0)

Mode 0

Mode 3 0 1 2 3 4 5 6 7

Instruction (02h)

8 9 10 28 29 30 39

24-Bit Address

23 22 21 3 2 1

*

/CS

CLK

DI

(IO0)

40 41 42 43 44 45 46 47

Data Byte 2

48 49 50 52 53 54 55

2072

7 6 5 4 3 2 1 0

5139

0

31032 33 34 35 36 37 38

Data Byte 1

7 6 5 4 3 2 1

*

Mode 0

Mode 3

Data Byte 3

2073

2074

2075

2076

2077

2078

2079

0

Data Byte 256

*

7 6 5 4 3 2 1 0

*

7 6 5 4 3 2 1 0

*

= MSB

*

7.2.13 Page Program (02h)

The Page Program instruction allows from one byte to 256 bytes (a page) of data to be programmed at
previously erased (FFh) memory locations. A Write Enable instruction must be executed before the device
will accept the Page Program Instruction (Status Register bit WEL= 1). The instruction is initiated by
driving the /CS pin low then shifting the instruction code “02h” followed by a 24-bit address (A23-A0) and
at least one data byte, into the DI pin. The /CS pin must be held low for the entire length of the instruction
while data is being sent to the device. The Page Program instruction sequence is shown in figure 19.

If an entire 256 byte page is to be programmed, the last address byte (the 8 least significant address bits)
should be set to 0. If the last address byte is not zero, and the number of clocks exceed the remaining
page length, the addressing will wrap to the beginning of the page. In some cases, less than 256 bytes (a
partial page) can be programmed without having any effect on other bytes within the same page. One
condition to perform a partial page program is that the number of clocks can not exceed the remaining
page length. If more than 256 bytes are sent to the device the addressing will wrap to the beginning of the
page and overwrite previously sent data.

As with the write and erase instructions, the /CS pin must be driven high after the eighth bit of the last byte
has been latched. If this is not done the Page Program instruction will not be executed. After /CS is driven
high, the self-timed Page Program instruction will commence for a time duration of tpp (See AC
Characteristics). While the Page Program cycle is in progress, the Read Status Register instruction may
still be accessed for checking the status of the BUSY bit. The BUSY bit is a 1 during the Page Program
cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions
again. After the Page Program cycle has finished the Write Enable Latch (WEL) bit in the Status Register
is cleared to 0. The Page Program instruction will not be executed if the addressed page is protected by
the Block Protect (CMP, SEC, TB, BP2, BP1, and BP0) bits.

Figure 19. Page Program Instruction Sequence Diagram

- 38 -

/CS

CLK

Mode 0

Mode 3 0 1

IO

0

IO

1

IO

2

IO

3

02h

Instruction

2 3 4 5

20 16 12 8

21 17

22 18

23 19

13 9

14 10

15 11

A23-16

6 7 8 9

4 0

5 1

6 2

7 3

A15-8 A7-0 Byte1 Byte 2 Byte 3

4 0

5 1

6 2

7 3

4 0

5 1

6 2

7 3

4 0

5 1

6 2

7 3

10 11 12 13

Byte 255 Byte 256

4 0

5 1

6 2

7 3

4 0

5 1

6 2

7 3

Mode 0

Mode 3

516

517

518

519

Figure 29b. Page Program Instruction (QPI Mode)

W25Q40EW

- 39 - Preliminary-Revision J

Publication Release Date: August 18, 2018

W25Q40EW

/CS

CLK

Mode 0

Mode 3 0 1 2 3 4 5 6 7

Instruction (32h)

8 9 10 28 29 30

32 33 34 35 36 37

4 0

24-Bit Address

23 22 21 3 2 1 0

*

31

31

/CS

CLK

5 1

Byte 1

6 2

7 3

4 0

5 1

6 2

7 3

4 0

5 1

6 2

7 3

4 0

5 1

6 2

7 3

Byte 2 Byte 3

Byte

256

0 4 0

5 1

6 2

7 3

4 0

5 1

6 2

7 3

4 0

5 1

6 2

7 3

536

537

538

539

540

541

542

543

Mode 0

Mode 3

Byte

253

Byte

254

Byte

255

IO

0

IO

1

IO

2

IO

3

IO

0

IO

1

IO

2

IO

3

* * * * * * *

= MSB

*

7.2.14 Quad Input Page Program (32h)

The Quad Page Program instruction allows up to 256 bytes of data to be programmed at previously
erased (FFh) memory locations using four pins: IO0, IO1, IO2, and IO3. The Quad Page Program can
improve performance for PROM Programmer and applications that have slow clock speeds <5MHz.
Systems with faster clock speed will not realize much benefit for the Quad Page Program instruction since
the inherent page program time is much greater than the time it take to clock-in the data.

To use Quad Page Program the Quad Enable in Status Register-2 must be set (QE=1). A Write Enable
instruction must be executed before the device will accept the Quad Page Program instruction (Status
Register-1, WEL=1). The instruction is initiated by driving the /CS pin low then shifting the instruction code
“32h” followed by a 24-bit address (A23-A0) and at least one data byte, into the IO pins. The /CS pin must
be held low for the entire length of the instruction while data is being sent to the device. All other functions
of Quad Page Program are identical to standard Page Program. The Quad Page Program instruction
sequence is shown in figure 20.

Figure 20. Quad Input Page Program Instruction Sequence Diagram

- 40 -

W25Q40EW

/CS

CLK

DI

(IO0)

DO

(IO1)

Mode 0

Mode 3 0 1 2 3 4 5 6 7

Instruction (20h)

High Impedance

8 9 29 30 31

24-Bit Address

23 22 2 1 0

*

Mode 0

Mode 3

= MSB

*

/CS

CLK

Mode 0

Mode 3 0 1

IO

0

IO

1

IO

2

IO

3

20h

Instruction

2 3 4 5

20 16 12 8

21 17

22 18

23 19

13 9

14 10

15 11

A23-16

6 7

4 0

5 1

6 2

7 3

A15-8 A7-0

Mode 0

Mode 3

7.2.15 Sector Erase (20h)

The Sector Erase instruction sets all memory within a specified sector (4K-bytes) to the erased state of all
1s (FFh). A Write Enable instruction must be executed before the device will accept the Sector Erase
Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low
and shifting the instruction code “20h” followed a 24-bit sector address (A23-A0). The Sector Erase
instruction sequence is shown in Figure 31a & 31b.

The /CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not done the
Sector Erase instruction will not be executed. After /CS is driven high, the self-timed Sector Erase
instruction will commence for a time duration of tSE (See AC Characteristics). While the Sector Erase
cycle is in progress, the Read Status Register instruction may still be accessed for checking the status of
the BUSY bit. The BUSY bit is a 1 during the Sector Erase cycle and becomes a 0 when the cycle is
finished and the device is ready to accept other instructions again. After the Sector Erase cycle has
finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Sector Erase
instruction will not be executed if the addressed page is protected by the Block Protect (CMP, SEC, TB,
BP2, BP1, and BP0) bits or the Individual Block/Sector Locks.

Figure 31a. Sector Erase Instruction (SPI Mode)

Figure 31b. Sector Erase Instruction (QPI Mode)

Publication Release Date: August 18, 2018

- 41 - Preliminary-Revision J

W25Q40EW

/CS

CLK

DI

(IO0)

DO

(IO1)

Mode 0

Mode 3 0 1 2 3 4 5 6 7

Instruction (52h)

High Impedance

8 9 29 30 31

24-Bit Address

23 22 2 1 0

*

Mode 0

Mode 3

= MSB

*

/CS

CLK

Mode 0

Mode 3 0 1

IO

0

IO

1

IO

2

IO

3

52h

Instruction

2 3 4 5

20 16 12 8

21 17

22 18

23 19

13 9

14 10

15 11

A23-16

6 7

4 0

5 1

6 2

7 3

A15-8 A7-0

Mode 0

Mode 3

7.2.16 32KB Block Erase (52h)

The Block Erase instruction sets all memory within a specified block (32K-bytes) to the erased state of all
1s (FFh). A Write Enable instruction must be executed before the device will accept the Block Erase
Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low
and shifting the instruction code “52h” followed a 24-bit block address (A23-A0). The Block Erase
instruction sequence is shown in Figure 32a & 32b.

The /CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not done the
Block Erase instruction will not be executed. After /CS is driven high, the self-timed Block Erase instruction
will commence for a time duration of tBE1 (See AC Characteristics). While the Block Erase cycle is in
progress, the Read Status Register instruction may still be accessed for checking the status of the BUSY
bit. The BUSY bit is a 1 during the Block Erase cycle and becomes a 0 when the cycle is finished and the
device is ready to accept other instructions again. After the Block Erase cycle has finished the Write
Enable Latch (WEL) bit in the Status Register is cleared to 0. The Block Erase instruction will not be
executed if the addressed page is protected by the Block Protect (CMP, SEC, TB, BP2, BP1, and BP0)
bits or the Individual Block/Sector Locks.

Figure 32a. 32KB Block Erase Instruction (SPI Mode)

Figure 32b. 32KB Block Erase Instruction (QPI Mode)

- 42 -

W25Q40EW

/CS

CLK

DI

(IO0)

DO

(IO1)

Mode 0

Mode 3 0 1 2 3 4 5 6 7

Instruction (D8h)

High Impedance

8 9 29 30 31

24-Bit Address

23 22 2 1 0

*

Mode 0

Mode 3

= MSB

*

/CS

CLK

Mode 0

Mode 3 0 1

IO

0

IO

1

IO

2

IO

3

D8h

Instruction

2 3 4 5

20 16 12 8

21 17

22 18

23 19

13 9

14 10

15 11

A23-16

6 7

4 0

5 1

6 2

7 3

A15-8 A7-0

Mode 0

Mode 3

7.2.17 64KB Block Erase (D8h)

The Block Erase instruction sets all memory within a specified block (64K-bytes) to the erased state of all
1s (FFh). A Write Enable instruction must be executed before the device will accept the Block Erase
Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low
and shifting the instruction code “D8h” followed a 24-bit block address (A23-A0). The Block Erase
instruction sequence is shown in Figure 33a & 33b.

The /CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not done the
Block Erase instruction will not be executed. After /CS is driven high, the self-timed Block Erase instruction
will commence for a time duration of tBE (See AC Characteristics). While the Block Erase cycle is in
progress, the Read Status Register instruction may still be accessed for checking the status of the BUSY
bit. The BUSY bit is a 1 during the Block Erase cycle and becomes a 0 when the cycle is finished and the
device is ready to accept other instructions again. After the Block Erase cycle has finished the Write
Enable Latch (WEL) bit in the Status Register is cleared to 0. The Block Erase instruction will not be
executed if the addressed page is protected by the Block Protect (CMP, SEC, TB, BP2, BP1, and BP0)
bits or the Individual Block/Sector Locks.

Figure 33a. 64KB Block Erase Instruction (SPI Mode)

Figure 33b. 64KB Block Erase Instruction (QPI Mode)

- 43 - Preliminary-Revision J

Publication Release Date: August 18, 2018

W25Q40EW

/CS

CLK

DI

(IO0)

DO

(IO1)

Mode 0

Mode 3 0 1 2 3 4 5 6 7

Instruction (C7h/60h)

High Impedance

Mode 0

Mode 3

/CS

CLK

Mode 0

Mode 3 0 1

IO

0

IO

1

IO

2

IO

3

C7h/60h

Instruction

Mode 0

Mode 3

7.2.18 Chip Erase (C7h / 60h)

The Chip Erase instruction sets all memory within the device to the erased state of all 1s (FFh). A Write
Enable instruction must be executed before the device will accept the Chip Erase Instruction (Status
Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and shifting the
instruction code “C7h” or “60h”. The Chip Erase instruction sequence is shown in Figure 34.

The /CS pin must be driven high after the eighth bit has been latched. If this is not done the Chip Erase
instruction will not be executed. After /CS is driven high, the self-timed Chip Erase instruction will
commence for a time duration of tCE (See AC Characteristics). While the Chip Erase cycle is in progress,
the Read Status Register instruction may still be accessed to check the status of the BUSY bit. The BUSY
bit is a 1 during the Chip Erase cycle and becomes a 0 when finished and the device is ready to accept
other instructions again. After the Chip Erase cycle has finished the Write Enable Latch (WEL) bit in the
Status Register is cleared to 0. The Chip Erase instruction will not be executed if any memory region is
protected by the Block Protect (CMP, SEC, TB, BP2, BP1, and BP0) bits or the Individual Block/Sector
Locks.

Figure 34. Chip Erase Instruction for SPI Mode (left) or QPI Mode (right)

- 44 -

W25Q40EW

/CS

CLK

DI

(IO0)

DO

(IO1)

Mode 0

Mode 3 0 1 2 3 4 5 6 7

Instruction (75h)

High Impedance

Mode 0

Mode 3

tSUS

Accept instructions

7.2.19 Erase / Program Suspend (75h)

The Erase/Program Suspend instruction “75h”, allows the system to interrupt a Sector or Block Erase
operation or a Page Program operation and then read from or program/erase data to, any other sectors or
blocks. The Erase/Program Suspend instruction sequence is shown in Figure 35a & 35b.

The Write Status Register instruction (01h) and Erase instructions (20h, 52h, D8h, C7h, 60h, 44h) are not
allowed during Erase Suspend. Erase Suspend is valid only during the Sector or Block erase operation. If
written during the Chip Erase operation, the Erase Suspend instruction is ignored. The Write Status
Register instruction (01h) and Program instructions (02h, 32h, 42h) are not allowed during Program
Suspend. Program Suspend is valid only during the Page Program or Quad Page Program operation.

The Erase/Program Suspend instruction “75h” will be accepted by the device only if the SUS bit in the
Status Register equals to 0 and the BUSY bit equals to 1 while a Sector or Block Erase or a Page
Program operation is on-going. If the SUS bit equals to 1 or the BUSY bit equals to 0, the Suspend
instruction will be ignored by the device. A maximum of time of “t
to suspend the erase or program operation. The BUSY bit in the Status Register will be cleared from 1 to

0 within “t

” and the SUS bit in the Status Register will be set from 0 to 1 immediately after

SUS

Erase/Program Suspend. For a previously resumed Erase/Program operation, it is also required that the

Suspend instruction “75h” is not issued earlier than a minimum of time of “t

Resume instruction “7Ah”.

” (See AC Characteristics) is required

SUS

” following the preceding

SUS

Unexpected power off during the Erase/Program suspend state will reset the device and release the
suspend state. SUS bit in the Status Register will also reset to 0. The data within the page, sector or block
that was being suspended may become corrupted. It is recommended for the user to implement system
design techniques against the accidental power interruption and preserve data integrity during
erase/program suspend state.

Figure 35a. Erase/Program Suspend Instruction (SPI Mode)

Publication Release Date: August 18, 2018

- 45 - Preliminary-Revision J

W25Q40EW

/CS

CLK

Mode 0

Mode 3 0 1

IO

0

IO

1

IO

2

IO

3

75h

Instruction

Mode 0

Mode 3

tSUS

Accept instructions

Figure 35b. Erase/Program Suspend Instruction (QPI Mode)

- 46 -

W25Q40EW

/CS

CLK

DI

(IO0)

Mode 0

Mode 3 0 1 2 3 4 5 6 7

Instruction (7Ah)

Mode 0

Mode 3

Resume previously
suspended Program or
Erase

/CS

CLK

Mode 0

Mode 3 0 1

IO

0

IO

1

IO

2

IO

3

7Ah

Instruction

Mode 0

Mode 3

Resume previously
suspended Program or
Erase

7.2.20 Erase / Program Resume (7Ah)

The Erase/Program Resume instruction “7Ah” must be written to resume the Sector or Block Erase

operation or the Page Program operation after an Erase/Program Suspend. The Resume instruction “7Ah”
will be accepted by the device only if the SUS bit in the Status Register equals to 1 and the BUSY bit
equals to 0. After issued the SUS bit will be cleared from 1 to 0 immediately, the BUSY bit will be set from
0 to 1 within 200ns and the Sector or Block will complete the erase operation or the page will complete the

program operation. If the SUS bit equals to 0 or the BUSY bit equals to 1, the Resume instruction “7Ah”

will be ignored by the device. The Erase/Program Resume instruction sequence is shown in Figure 36a &
36b.

Resume instruction is ignored if the previous Erase/Program Suspend operation was interrupted by
unexpected power off. It is also required that a subsequent Erase/Program Suspend instruction not to be
issued within a minimum of time of “t

” following a previous Resume instruction.

SUS

Figure 36a. Erase/Program Resume Instruction (SPI Mode)

Figure 36b. Erase/Program Resume Instruction (QPI Mode)

Publication Release Date: August 18, 2018

- 47 - Preliminary-Revision J

W25Q40EW

/CS

CLK

DI

(IO0)

Mode 0

Mode 3 0 1 2 3 4 5 6 7

Instruction (B9h)

Mode 0

Mode 3

tDP

Power-down currentStand-by current

/CS

CLK

Mode 0

Mode 3 0 1

IO

0

IO

1

IO

2

IO

3

B9h

Instruction

Mode 0

Mode 3

tDP

Power-down currentStand-by current

7.2.21 Power-down (B9h)

Although the standby current during normal operation is relatively low, standby current can be further
reduced with the Power-down instruction. The lower power consumption makes the Power-down
instruction especially useful for battery powered applications (See ICC1 and ICC2 in AC Characteristics).
The instruction is initiated by driving the /CS pin low and shifting the instruction code “B9h” as shown in
Figure 37a & 37b.

The /CS pin must be driven high after the eighth bit has been latched. If this is not done the Power-down
instruction will not be executed. After /CS is driven high, the power-down state will entered within the time
duration of tDP (See AC Characteristics). While in the power-down state only the Release Power-down /
Device ID (ABh) instruction, which restores the device to normal operation, will be recognized. All other
instructions are ignored. This includes the Read Status Register instruction, which is always available
during normal operation. Ignoring all but one instruction makes the Power Down state a useful condition
for securing maximum write protection. The device always powers-up in the normal operation with the
standby current of ICC1.

Figure 37a. Deep Power-down Instruction (SPI Mode)

Figure 37b. Deep Power-down Instruction (QPI Mode)

- 48 -

W25Q40EW

/CS

CLK

DI

(IO0)

Mode 0

Mode 3 0 1 2 3 4 5 6 7

Instruction (ABh)

Mode 0

Mode 3

tRES1

Power-down current Stand-by current

7.2.22 Release Power-down / Device ID (ABh)

The Release from Power-down / Device ID instruction is a multi-purpose instruction. It can be used to
release the device from the power-down state, or obtain the devices electronic identification (ID) number.

To release the device from the power-down state, the instruction is issued by driving the /CS pin low,
shifting the instruction code “ABh” and driving /CS high as shown in Figure 38a & 38b. Release from
power-down will take the time duration of tRES1 (See AC Characteristics) before the device will resume
normal operation and other instructions are accepted. The /CS pin must remain high during the tRES1 time
duration.

When used only to obtain the Device ID while not in the power-down state, the instruction is initiated by
driving the /CS pin low and shifting the instruction code “ABh” followed by 3-dummy bytes. The Device ID
bits are then shifted out on the falling edge of CLK with most significant bit (MSB) first. The Device ID
value for the W25Q40EW is listed in Manufacturer and Device Identification table. The Device ID can be
read continuously. The instruction is completed by driving /CS high.

When used to release the device from the power-down state and obtain the Device ID, the instruction is
the same as previously described, and shown in Figure 38c & 38d, except that after /CS is driven high it
must remain high for a time duration of tRES2 (See AC Characteristics). After this time duration the device
will resume normal operation and other instructions will be accepted. If the Release from Power-down /
Device ID instruction is issued while an Erase, Program or Write cycle is in process (when BUSY equals

1) the instruction is ignored and will not have any effects on the current cycle.

Figure 38a. Release Power-down Instruction (SPI Mode)

Publication Release Date: August 18, 2018

- 49 - Preliminary-Revision J

/CS

CLK

Mode 0

Mode 3 0 1

IO

0

IO

1

IO

2

IO

3

ABh

Instruction

Mode 0

Mode 3

tRES1

Power-down current Stand-by current

Figure 38b. Release Power-down Instruction (QPI Mode)

tRES2

/CS

CLK

DI

(IO0)

DO

(IO1)

Mode 0

Mode 3 0 1 2 3 4 5 6 7

Instruction (ABh)

High Impedance

8 9 29 30 31

3 Dummy Bytes

23 22 2 1 0

*

Mode 0

Mode 3

7 6 5 4 3 2 1 0

*

32 33 34 35 36 37 38

Device ID

Power-down current Stand-by current

= MSB

*

Power-down current Stand-by current

Device ID

/CS

CLK

Mode 0

Mode 3 0 1

IO

0

IO

1

IO

2

IO

3

ABh

2 3 4 5

X X

X X

X X

X X

6 7 8

4 0

5 1

6 2

7 3

IOs switch from
Input to Output

Instruction

tRES2

Mode 0

Mode 3

X X

X X

X X

X X

X X

X X

X X

X X

3 Dummy Bytes

W25Q40EW

Figure 38c. Release Power-down / Device ID Instruction (SPI Mode)

Figure 38d. Release Power-down / Device ID Instruction (QPI Mode)

- 50 -

W25Q40EW

/CS

CLK

DI

(IO0)

DO

(IO1)

Mode 0

Mode 3 0 1 2 3 4 5 6 7

Instruction (90h)

High Impedance

8 9 10 28 29 30 31

Address (000000h)

23 22 21 3 2 1 0

Device ID

*

/CS

CLK

DI

(IO0)

DO

(IO1)

32 33 34 35 36 37 38 39

Manufacturer ID (EFh)

40 41 42 44 45 46

7 6 5 4 3 2 1 0

*

4331

0

Mode 0

Mode 3

= MSB

*

7.2.23 Read Manufacturer / Device ID (90h)

The Read Manufacturer/Device ID instruction is an alternative to the Release from Power-down / Device
ID instruction that provides both the JEDEC assigned manufacturer ID and the specific device ID.

The Read Manufacturer/Device ID instruction is very similar to the Release from Power-down / Device ID
instruction. The instruction is initiated by driving the /CS pin low and shifting the instruction code “90h”
followed by a 24-bit address (A23-A0) of 000000h. After which, the Manufacturer ID for Winbond (EFh)
and the Device ID are shifted out on the falling edge of CLK with most significant bit (MSB) first as shown
in figure 29. The Device ID values for the W25Q40EW is listed in Manufacturer and Device Identification
table. The Manufacturer and Device IDs can be read continuously, alternating from one to the other. The
instruction is completed by driving /CS high.

Figure 29. Read Manufacturer / Device ID Diagram

- 51 - Preliminary-Revision J

Publication Release Date: August 18, 2018

W25Q40EW

/CS

CLK

DI

(IO0)

DO

(IO1)

Mode 0

Mode 3 0 1 2 3 4 5 6 7

Instruction (92h)

High Impedance

8 9 10 11 12 13 14 15 16 17 18 19 20 21 22

7 5 3 1

* *

6 4 2 0

7 5 3 1

6 4 2 0

7 5 3 1

6 4 2 0

7 5 3 1

6 4 2 0

23

* *

A23-16 A15-8 A7-0 (00h) M7-0

/CS

CLK

DI

(IO0)

DO

(IO1)

24 25 26 27 28 29 30 31 32 33 34 36 37 383523

0

Mode 0

Mode 3

7 5 3 1

6 4 2 0

7 5 3 1

6 4 2 0

7 5 3 1

6 4 2 0

7 5 3

6 4 210

1

MFR ID Device ID

MFR ID

(repeat)

Device ID

(repeat)

IOs switch from
Input to Output

* ** *

= MSB

*

7.2.24 Read Manufacturer / Device ID Dual I/O (92h)

The Manufacturer / Device ID Dual I/O instruction is an alternative to the Read Manufacturer/Device ID
instruction that provides both the JEDEC assigned manufacturer ID and the specific device ID at 2x
speed.

The Read Manufacturer / Device ID Dual I/O instruction is similar to the Fast Read Dual I/O instruction.
The instruction is initiated by driving the /CS pin low and shifting the instruction code “92h” followed by a
24-bit address (A23-A0) of 000000h, with the capability to input the Address bits two bits per clock. After
which, the Manufacturer ID for Winbond (EFh) and the Device ID are shifted out 2 bits per clock on the
falling edge of CLK with most significant bits (MSB) first as shown in figure 30. The Device ID values for
the W25Q40EW is listed in Manufacturer and Device Identification table. The Manufacturer and Device
IDs can be read continuously, alternating from one to the other. The instruction is completed by driving
/CS high.

Note:

The “Continuous Read Mode” bits M7-0 must be set to Fxh to be compatible with Fast Read Dual I/O instruction.

Figure 30. Read Manufacturer / Device ID Dual I/O Diagram

- 52 -

W25Q40EW

Mode 0

Mode 3 0 1 2 3 4 5 6 7

Instruction (94h)

High Impedance

8 9 10 11 12 13 14 15 16 17 18 19 20 21 22

5 1

4 0

23

Mode 0

Mode 3

IOs switch from
Input to Output

High Impedance

7 3

6 2

/CS

CLK

IO

0

IO

1

IO

2

IO

3

High Impedance

A23-16 A15-8

A7-0

(00h)

M7-0

MFR ID Device ID

Dummy Dummy

/CS

CLK

IO

0

IO

1

IO

2

IO

3

23

0

1

2

3

5 1

4 0

7 3

6 2

5 1

4 0

7 3

6 2

5 1

4 0

7 3

6 2

5 1

4 0

7 3

6 2

5 1

4 0

7 3

6 2

5 1

4 0

7 3

6 2

5 1

4 0

7 3

6 2

5 1

4 0

7 3

6 2

5 1

4 0

7 3

6 2

24 25 26 27 28 29 30

MFR ID
(repeat)

Device ID

(repeat)

MFR ID
(repeat)

Device ID

(repeat)

7.2.25 Read Manufacturer / Device ID Quad I/O (94h)

The Read Manufacturer / Device ID Quad I/O instruction is an alternative to the Read Manufacturer /
Device ID instruction that provides both the JEDEC assigned manufacturer ID and the specific device ID
at 4x speed.

The Read Manufacturer / Device ID Quad I/O instruction is similar to the Fast Read Quad I/O instruction.
The instruction is initiated by driving the /CS pin low and shifting the instruction code “94h” followed by a
24-bit address (A23-A0) of 000000h, with the capability to input the Address bits four bits per clock. After
which, the Manufacturer ID for Winbond (EFh) and the Device ID are shifted out four bits per clock on the
falling edge of CLK with most significant bit (MSB) first as shown in figure 31. The Device ID values for the
W25Q40EW is listed in Manufacturer and Device Identification table. The Manufacturer and Device IDs
can be read continuously, alternating from one to the other. The instruction is completed by driving /CS
high.

Note:

The “Continuous Read Mode” bits M7-0 must be set to Fxh to be compatible with Fast Read Quad I/O instruction.

Figure 31. Read Manufacturer / Device ID Quad I/O Diagram

Publication Release Date: August 18, 2018

- 53 - Preliminary-Revision J

W25Q40EW

/CS

CLK

DI

(IO0)

DO

(IO1)

Mode 0

Mode 3 0 1 2 3 4 5 6 7

Instruction (4Bh)

High Impedance

8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

/CS

CLK

DI

(IO0)

DO

(IO1)

24 25 26 27 28 29 30 31 32 33 34 36 37 383523

Mode 0

Mode 3

*

Dummy Byte 1 Dummy Byte 2

39 40 41 42

Dummy Byte 3 Dummy Byte 4

63 62 61 2 1 0

64-bit Unique Serial Number

100

101

102

High Impedance

= MSB

*

7.2.26 Read Unique ID Number (4Bh)

The Read Unique ID Number instruction accesses a factory-set read-only 64-bit number that is unique to
each W25Q40EW device. The ID number can be used in conjunction with user software methods to help
prevent copying or cloning of a system. The Read Unique ID instruction is initiated by driving the /CS pin
low and shifting the instruction code “4Bh” followed by a four bytes of dummy clocks. After which, the 64­bit ID is shifted out on the falling edge of CLK as shown in figure 32.

Figure 32. Read Unique ID Number Instruction Sequence

- 54 -

W25Q40EW

/CS

CLK

DI

(IO0)

DO

(IO1)

Mode 0

Mode 3 0 1 2 3 4 5 6 7

Instruction (9Fh)

High Impedance

8 9 10 12 13 14 15

Capacity ID7-0

/CS

CLK

DI

(IO0)

DO

(IO1)

16 17 18 19 20 21 22 23

Manufacturer ID (EFh)

24 25 26 28 29 30

7 6 5 4 3 2 1 0

*

2715

Mode 0

Mode 3

11

7 6 5 4 3 2 1 0

*

Memory Type ID15-8

= MSB

*

/CS

CLK

Mode 0

Mode 3 0 1

IO

0

IO

1

IO

2

IO

3

9Fh

2 3 4 5

12 8

13 9

14 10

15 11

EFh

6

4 0

5 1

6 2

7 3

ID15-8 ID7-0

IOs switch from
Input to Output

Instruction

Mode 0

Mode 3

7.2.27 Read JEDEC ID (9Fh)

For compatibility reasons, the W25Q40EW provides several instructions to electronically determine the
identity of the device. The Read JEDEC ID instruction is compatible with the JEDEC standard for SPI
compatible serial memories that was adopted in 2003. The instruction is initiated by driving the /CS pin low
and shifting the instruction code “9Fh”. The JEDEC assigned Manufacturer ID byte for Winbond (EFh) and
two Device ID bytes, Memory Type (ID15-ID8) and Capacity (ID7-ID0) are then shifted out on the falling
edge of CLK with most significant bit (MSB) first as shown in Figure 43a & 43b. For memory type and
capacity values refer to Manufacturer and Device Identification table.

Figure 43a. Read JEDEC ID Instruction (SPI Mode)

Figure 43b. Read JEDEC ID Instruction (QPI Mode)

- 55 - Preliminary-Revision J

Publication Release Date: August 18, 2018

W25Q40EW

/CS

CLK

DI

(IO0)

DO

(IO1)

Mode 0

Mode 3 0 1 2 3 4 5 6 7

Instruction (5Ah)

High Impedance

8 9 10 28 29 30 31

24-Bit Address

23 22 21 3 2 1 0

Data Out 1

*

/CS

CLK

DI

(IO0)

DO

(IO1)

32 33 34 35 36 37 38 39

Dummy Byte

High Impedance

40 41 42 44 45 46 47 48 49 50 51 52 53 54 55

7 6 5 4 3 2 1 0 7

Data Out 2

*

7 6 5 4 3 2 1 0

*

7 6 5 4 3 2 1 0

4331

0

= MSB

*

7.2.28 Read SFDP Register (5Ah)

The W25Q40EW features a 256-Byte Serial Flash Discoverable Parameter (SFDP) register that contains
information about device configurations, available instructions and other features. The SFDP parameters
are stored in one or more Parameter Identification (PID) tables. Currently only one PID table is specified,
but more may be added in the future. The Read SFDP Register instruction is compatible with the SFDP
standard initially established in 2010 for PC and other applications, as well as the JEDEC standard
JESD216-serials that is published in 2011. Most Winbond SpiFlash Memories shipped after June 2011
(date code 1124 and beyond) support the SFDP feature as specified in the applicable datasheet.

The Read SFDP instruction is initiated by driving the /CS pin low and shifting the instruction code “5Ah”
followed by a 24-bit address (A23-A0)

(1)

into the DI pin. Eight “dummy” clocks are also required before the
SFDP register contents are shifted out on the falling edge of the 40th CLK with most significant bit (MSB)
first as shown in Figure 44. For SFDP register values and descriptions, please refer to the Winbond
Application Note for SFDP Definition table.

Note: 1. A23-A8 = 0; A7-A0 are used to define the starting byte address for the 256-Byte SFDP Register.

Figure 44. Read SFDP Register Instruction Sequence Diagram(SPI mode only)

- 56 -

W25Q40EW

ADDRESS

A23-16

A15-12

A11-8

A7-0

Security Register #1

00h

0 0 0 1

0 0 0 0

Don’t Care

Security Register #2

00h

0 0 1 0

0 0 0 0

Don’t Care

Security Register #3

00h

0 0 1 1

0 0 0 0

Don’t Care

/CS

CLK

DI

(IO0)

DO

(IO1)

Mode 0

Mode 3 0 1 2 3 4 5 6 7

Instruction (44h)

High Impedance

8 9 29 30 31

24-Bit Address

23 22 2 1 0

*

Mode 0

Mode 3

= MSB

*

7.2.29 Erase Security Registers (44h)

The W25Q40EW offers three 256-byte Security Registers which can be erased and programmed
individually. These registers may be used by the system manufacturers to store security and other
important information separately from the main memory array.

The Erase Security Register instruction is similar to the Sector Erase instruction. A Write Enable
instruction must be executed before the device will accept the Erase Security Register Instruction (Status
Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and shifting the
instruction code “44h” followed by a 24-bit address (A23-A0) to erase one of the three security registers.

The Erase Security Register instruction sequence is shown in Figure 45. The /CS pin must be driven high
after the eighth bit of the last byte has been latched. If this is not done the instruction will not be executed.
After /CS is driven high, the self-timed Erase Security Register operation will commence for a time
duration of tSE (See AC Characteristics). While the Erase Security Register cycle is in progress, the Read
Status Register instruction may still be accessed for checking the status of the BUSY bit. The BUSY bit is
a 1 during the erase cycle and becomes a 0 when the cycle is finished and the device is ready to accept
other instructions again. After the Erase Security Register cycle has finished the Write Enable Latch
(WEL) bit in the Status Register is cleared to 0. The Security Register Lock Bits LB[3:1] in the Status
Register-2 can be used to OTP protect the security registers. Once a lock bit is set to 1, the corresponding
security register will be permanently locked, Erase Security Register instruction to that register will be
ignored (See 7.1.9 for detail descriptions).

Figure 45. Erase Security Registers Instruction (SPI Mode only)

- 57 - Preliminary-Revision J

Publication Release Date: August 18, 2018

W25Q40EW

ADDRESS

A23-16

A15-12

A11-8

A7-0

Security Register #1

00h

0 0 0 1

0 0 0 0

Byte Address

Security Register #2

00h

0 0 1 0

0 0 0 0

Byte Address

Security Register #3

00h

0 0 1 1

0 0 0 0

Byte Address

/CS

CLK

DI

(IO0)

Mode 0

Mode 3 0 1 2 3 4 5 6 7

Instruction (42h)

8 9 10 28 29 30 39

24-Bit Address

23 22 21 3 2 1

*

/CS

CLK

DI

(IO0)

40 41 42 43 44 45 46 47

Data Byte 2

48 49 50 52 53 54 55

2072

7 6 5 4 3 2 1 0

5139

0

31032 33 34 35 36 37 38

Data Byte 1

7 6 5 4 3 2 1

*

Mode 0

Mode 3

Data Byte 3

2073

2074

2075

2076

2077

2078

2079

0

Data Byte 256

*

7 6 5 4 3 2 1 0

*

7 6 5 4 3 2 1 0

*

= MSB

*

7.2.30 Program Security Registers (42h)

The Program Security Register instruction is similar to the Page Program instruction. It allows from one
byte to 256 bytes of security register data to be programmed at previously erased (FFh) memory locations.
A Write Enable instruction must be executed before the device will accept the Program Security Register
Instruction (Status Register bit WEL= 1). The instruction is initiated by driving the /CS pin low then shifting
the instruction code “42h” followed by a 24-bit address (A23-A0) and at least one data byte, into the DI pin.
The /CS pin must be held low for the entire length of the instruction while data is being sent to the device.

The Program Security Register instruction sequence is shown in Figure 46. The Security Register Lock
Bits LB[3:1] in the Status Register-2 can be used to OTP protect the security registers. Once a lock bit is
set to 1, the corresponding security register will be permanently locked, Program Security Register
instruction to that register will be ignored (See 7.1.9, 7.2.21 for detail descriptions).

Figure 46. Program Security Registers Instruction (SPI Mode only)

- 58 -

W25Q40EW

ADDRESS

A23-16

A15-12

A11-8

A7-0

Security Register #1

00h

0 0 0 1

0 0 0 0

Byte Address

Security Register #2

00h

0 0 1 0

0 0 0 0

Byte Address

Security Register #3

00h

0 0 1 1

0 0 0 0

Byte Address

/CS

CLK

DI

(IO0)

DO

(IO1)

Mode 0

Mode 3 0 1 2 3 4 5 6 7

Instruction (48h)

High Impedance

8 9 10 28 29 30 31

24-Bit Address

23 22 21 3 2 1 0

Data Out 1

*

/CS

CLK

DI

(IO0)

DO

(IO1)

32 33 34 35 36 37 38 39

Dummy Byte

High Impedance

40 41 42 44 45 46 47 48 49 50 51 52 53 54 55

7 6 5 4 3 2 1 0 7

Data Out 2

*

7 6 5 4 3 2 1 0

*

7 6 5 4 3 2 1 0

4331

0

= MSB

*

7.2.31 Read Security Registers (48h)

The Read Security Register instruction is similar to the Fast Read instruction and allows one or more data
bytes to be sequentially read from one of the three security registers. The instruction is initiated by driving

the /CS pin low and then shifting the instruction code “48h” followed by a 24-bit address (A23-A0) and
eight “dummy” clocks into the DI pin. The code and address bits are latched on the rising edge of the CLK

pin. After the address is received, the data byte of the addressed memory location will be shifted out on
the DO pin at the falling edge of CLK with most significant bit (MSB) first. The byte address is
automatically incremented to the next byte address after each byte of data is shifted out. Once the byte
address reaches the last byte of the register (byte FFh), it will reset to 00h, the first byte of the register,
and continue to increment. The instruction is completed by driving /CS high. The Read Security Register
instruction sequence is shown in Figure 47. If a Read Security Register instruction is issued while an
Erase, Program or Write cycle is in process (BUSY=1) the instruction is ignored and will not have any
effects on the current cycle. The Read Security Register instruction allows clock rates from D.C. to a
maximum of FR (see AC Electrical Characteristics).

Figure 47. Read Security Registers Instruction (SPI Mode only)

Publication Release Date: August 18, 2018

- 59 - Preliminary-Revision J

W25Q40EW

P5 – P4

DUMMY

CLOCKS

MAXIMUM

READ FREQ.

MAXIMUM

READ FREQ.

(A[1:0]=0,0)

P1 – P0

WRAP

LENGTH

0 0 2 26MHz

26MHz

0 0

8-byte

0 1

4

55MHz

80MHz

0 1

16-byte

1 0

6

80MHz

104MHz

1 0

32-byte

1 1

8

104MHz

104MHz

1 1

64-byte

/CS

CLK

Mode 0

Mode 3 0 1

IO

0

IO

1

IO

2

IO

3

C0h

2 3

Read

Parameters

P4 P0

P5 P1

P6 P2

P7 P3

Instruction

Mode 0

Mode 3

7.2.32 Set Read Parameters (C0h)

In QPI mode, to accommodate a wide range of applications with different needs for either maximum read

frequency or minimum data access latency, “Set Read Parameters (C0h)” instruction can be used to
configure the number of dummy clocks for “Fast Read (0Bh)”, “Fast Read Quad I/O (EBh)” & “Burst Read
with Wrap (0Ch)” instructions, and to configure the number of bytes of “Wrap Length” for the “Burst Read

with Wrap (0Ch)” instruction.

In Standard SPI mode, the “Set Read Parameters (C0h)” instruction is not accepted. The dummy clocks

for various Fast Read instructions in Standard/Dual/Quad SPI mode are fixed, please refer to the
Instruction Table 1-2 for details. The “Wrap Length” is set by W5-4 bit in the “Set Burst with Wrap (77h)”
instruction. This setting will remain unchanged when the device is switched from Standard SPI mode to
QPI mode.

The default “Wrap Length” after a power up or a Reset instruction is 8 bytes, the default number of
dummy clocks is 2. The number of dummy clocks is only programmable for “Fast Read (0Bh)”, “Fast

Read Quad I/O (EBh)” & “Burst Read with Wrap (0Ch)” instructions in the QPI mode. Whenever the
device is switched from SPI mode to QPI mode, the number of dummy clocks should be set again, prior to
any 0Bh, EBh or 0Ch instructions.

Figure 48. Set Read Parameters Instruction (QPI Mode only)

- 60 -

W25Q40EW

Dummy*

/CS

CLK

Mode 0

Mode 3 0 1

IO

0

IO

1

IO

2

IO

3

0Ch

2 3 4 5

20 16 12 8

21 17

22 18

23 19

13 9

14 10

15 11

A23-16

6 7 8 9

4 0

5 1

6 2

7 3

A15-8 A7-0

Byte 1 Byte 2

4 0

5 1

6 2

7 3

4 0

5 1

6 2

7 3

10 11 12 13 14

4

5

6

7

IOs switch from
Input to Output

* "Set Read Parameters" instruction (C0h) can

set the number of dummy clocks.

Byte 3

Instruction

7.2.33 Burst Read with Wrap (0Ch)

The “Burst Read with Wrap (0Ch)” instruction provides an alternative way to perform the read operation

with “Wrap Around” in QPI mode. The instruction is similar to the “Fast Read (0Bh)” instruction in QPI

mode, except the addressing of the read operation will “W rap Around” to the beginning boundary of the

“Wrap Length” once the ending boundary is reached.
The “W rap Length” and the number of dummy clocks can be configured by the “Set Read Parameters

(C0h)” instruction.

Figure 49. Burst Read with Wrap Instruction (QPI Mode only)

Publication Release Date: August 18, 2018

- 61 - Preliminary-Revision J

W25Q40EW

/CS

CLK

DI

(IO0)

DO

(IO1)

Mode 0

Mode 3 0 1 2 3 4 5 6 7

Instruction (38h)

High Impedance

Mode 0

Mode 3

7.2.34 Enter QPI Mode (38h)

The W25Q40EW support both Standard/Dual/Quad Serial Peripheral Interface (SPI) and Quad Peripheral
Interface (QPI). However, SPI mode and QPI mode cannot be used at the same time. “Enter QPI (38h)”
instruction is the only way to switch the device from SPI mode to QPI mode.

Upon power-up, the default state of the device upon is Standard/Dual/Quad SPI mode. This provides full
backward compatibility with earlier generations of Winbond serial flash memories. See Instruction Set
Table 1-3 for all supported SPI commands. In order to switch the device to QPI mode, the Quad Enable
(QE) bit in Status Register-2 must be set to 1 first, and an “Enter QPI (38h)” instruction must be issued. If

the Quad Enable (QE) bit is 0, the “Enter QPI (38h)” instruction will be ignored and the device will remain

in SPI mode.
See Instruction Set Table 3 for all the commands supported in QPI mode.
When the device is switched from SPI mode to QPI mode, the existing Write Enable and Program/Erase

Suspend status, and the Wrap Length setting will remain unchanged.

Figure 50. Enter QPI Instruction (SPI Mode only)

- 62 -

W25Q40EW

/CS

CLK

Mode 0

Mode 3 0 1

IO

0

IO

1

IO

2

IO

3

FFh

Instruction

Mode 0

Mode 3

7.2.35 Exit QPI Mode (FFh)

In order to exit the QPI mode and return to the Standard/Dual/Quad SPI mode, an “Exit QPI (FFh)”

instruction must be issued.
When the device is switched from QPI mode to SPI mode, the existing Write Enable Latch (WEL) and

Program/Erase Suspend status, and the Wrap Length setting will remain unchanged.

Figure 51. Exit QPI Instruction (QPI Mode only)

Publication Release Date: November 19, 2012

- 63 -

W25Q40EW

Mode 0

Mode 3 0 1 2 3 4 5 6 7

Instruction (99h)

Mode 0

Mode 3

/CS

CLK

DI

(IO0)

DO

(IO1)

Mode 0

Mode 3 0 1 2 3 4 5 6 7

Instruction (66h)

High Impedance

Mode 0

Mode 3 0 1

99h

Instruction

Mode 0

Mode 3

/CS

CLK

Mode 0

Mode 3 0 1

IO

0

IO

1

IO

2

IO

3

66h

Instruction

7.2.36 Enable Reset (66h) and Reset Device (99h)

Because of the small package and the limitation on the number of pins, the W25Q40EW provide a
software Reset instruction instead of a dedicated RESET pin. Once the Reset instruction is accepted, any
on-going internal operations will be terminated and the device will return to its default power-on state and
lose all the current volatile settings, such as Volatile Status Register bits, Write Enable Latch (WEL)
status, Program/Erase Suspend status, Read parameter setting (P7-P0), Continuous Read Mode bit
setting (M7-M0) and Wrap Bit setting (W6-W4).

“Enable Reset (66h)” and “Reset (99h)” instructions can be issued in either SPI mode or QPI mode. To

avoid accidental reset, both instructions must be issued in sequence. Any other commands other than

“Reset (99h)” after the “Enable Reset (66h)” command will disable the “Reset Enable” state. A new

sequence of “Enable Reset (66h)” and “Reset (99h)” is needed to reset the device. Once the Reset

command is accepted by the device, the device will take approximately tRST=30us to reset. During this
period, no command will be accepted.

Data corruption may happen if there is an on-going or suspended internal Erase or Program operation
when Reset command sequence is accepted by the device. It is recommended to check the BUSY bit and
the SUS bit in Status Register before issuing the Reset command sequence.

Figure 56a. Enable Reset and Reset Instruction Sequence (SPI Mode)

Figure 56b. Enable Reset and Reset Instruction Sequence (QPI Mode)

- 64 -

8. ELECTRICAL CHARACTERISTICS

PARAMETERS

SYMBOL

CONDITIONS

RANGE

UNIT

Supply Voltage

VCC

–0.6 to 2.5V

V

Voltage Applied to Any Pin

VIO

Relative to Ground

–0.6 to VCC+0.4

V

Transient Voltage on any Pin

VIOT

<20nS Transient
Relative to Ground

–2.0V to VCC+2.0V

V

Storage Temperature

TSTG

–65 to +150

°C

Lead Temperature

TLEAD

See Note

(2)

°C

Electrostatic Discharge Voltage

VESD

Human Body Model

(3)

–2000 to +2000

V

PARAMETER

SYMBOL

CONDITIONS

SPEC

UNIT

MIN

MAX

Supply Voltage

VCC

FR = 104MHz, fR = 50MHz

1.65

1.95

V

Ambient Temperature,
Operating

TA

Industrial

–40

+85

°C

W25Q40EW

8.1 Absolute Maximum Ratings

(1)

Notes:

1. This device has been designed and tested for the specified operation ranges. Proper operation outside

of these levels is not guaranteed. Exposure to absolute maximum ratings may affect device reliability.
Exposure beyond absolute maximum ratings may cause permanent damage.

2. Compliant with JEDEC Standard J-STD-20C for small body Sn-Pb or Pb-free (Green) assembly and the

European directive on restrictions on hazardous substances (RoHS) 2002/95/EU.

3. JEDEC Std JESD22-A114A (C1=100pF, R1=1500 ohms, R2=500 ohms).

8.2 Operating Ranges

Note:

1. VCC voltage during Read can operate across the min and max range but should not exceed ±10% of

the programming (erase/write) voltage.

Publication Release Date: August 18, 2018

- 65 - Preliminary-Revision J

8.3 Power-up Timing and Write Inhibit Threshold

Parameter

Symbol

spec

Unit

MIN

MAX

VCC (min) to /CS Low

tVSL

(1)

10

µs

Time Delay Before Write Instruction

tPUW

(1)

1

10

ms

Write Inhibit Threshold Voltage

VWI

(1)

1.0

1.4

V

VCC

tVSL

Read Instructions

Allowed

Device is fully

Accessible

tPUW

/CS must track VCC

Program, Erase and Write Instructions are ignored

Reset
State

VCC (max)

VCC (min)

VWI

Time

Note:

1. These parameters are characterized only.

W25Q40EW

Figure 37. Power-up Timing and Voltage Levels

Figure 37b. Power-up, Power-Down Requirement

- 66 -

8.4 DC Electrical Characteristics: Industrial:

PARAMETER

SYMBOL

CONDITIONS

SPEC

UNIT

MIN

TYP

MAX

Input Capacitance

CIN

(1)

VIN = 0V

6

pF

Output Capacitance

Cout

(1)

VOUT = 0V

8

pF

Input Leakage

ILI

±2

µA

I/O Leakage

ILO

±2

µA

Standby Current

ICC1

/CS = VCC,
VIN = GND or VCC

10

25

µA

Power-down Current

ICC2

/CS = VCC,
VIN = GND or VCC

0.5

7.5

µA

Current Read Data /
Dual /Quad 1MHz

ICC3

(2)

C = 0.1 VCC / 0.9 VCC
DO = Open

1 3

mA

Current Read Data /
Dual /Quad 50MHz

ICC3

(2)

C = 0.1 VCC / 0.9 VCC
DO = Open

4 6

mA

Current Read Data /
Dual Output / Quad
Output Read 104MHz

Icc3

(2)

C = 0.1 VCC / 0.9 VCC
DO = Open

6 8

mA

Current Write Status
Register

Icc4

/CS = VCC

15

20

mA

Current Page Program

Icc5

/CS = VCC

15

20

mA

Current Sector/Block
Erase

Icc6

/CS = VCC

15

20

mA

Current Chip Erase

Icc7

/CS = VCC

15

20

mA

Input Low Voltage

Vil -0.5

VCC x 0.3

V

Input High Voltage

Vih

VCC x 0.7

VCC + 0.4

V

Output Low Voltage

Vol

Iol = 100 µA

0.2

V

Output High Voltage

Voh

Ioh = –100 µA

VCC – 0.2

V

W25Q40EW

Notes:

1. Tested on sample basis and specified through design and characterization data. TA = 25° C, VCC = 1.8V.

2. Checker Board Pattern.

Publication Release Date: August 18, 2018

- 67 - Preliminary-Revision J

8.5 AC Measurement Conditions

PARAMETER

SYMBOL

SPEC

UNIT

MIN

MAX

Load Capacitance

CL 30

pF

Input Rise and Fall Times

TR, TF 5

ns

Input Pulse Voltages

VIN

0.1 VCC to 0.9 VCC

V

Input Timing Reference Voltages

IN

0.3 VCC to 0.7 VCC

V

Output Timing Reference Voltages

OUT

0.5 VCC to 0.5 VCC

V

Input Levels

0.9 VCC

0.1 VCC

0.5 VCC

Input and Output Timing

Reference Levels

Note:

1. Output Hi-Z is defined as the point where data out is no longer driven.

W25Q40EW

Figure 38. AC Measurement I/O Waveform

- 68 -

8.6 AC Electrical Characteristics:

DESCRIPTION

SYMBOL

ALT

SPEC

UNIT

MIN

TYP

MAX

Clock frequency for all instructions
except for Read Data (03h)

FR

fC

D.C. 104

MHz

Clock frequency for Read Data instruction (03h)

fR

D.C. 50

MHz

Clock High, Low Time for all instructions
except Read Data (03h)

tCLH1,

tCLL1

(1)

4

ns

Clock High, Low Time
for Read Data (03h) instruction

tCRLH,

tCRLL

(1)

8

ns

Clock Rise Time peak to peak

tCLCH

(2)

0.1

V/ns

Clock Fall Time peak to peak

tCHCL

(2)

0.1

V/ns

/CS Active Setup Time relative to CLK

tSLCH

tCSS 5 ns

/CS Not Active Hold Time relative to CLK

tCHSL

5 ns

Data In Setup Time

tDVCH

tDSU 2 ns

Data In Hold Time

tCHDX

tDH 5 ns

/CS Active Hold Time relative to CLK

tCHSH

5 ns

/CS Not Active Setup Time relative to CLK

tSHCH

5 ns

/CS Deselect Time (for Array Read  Array Read)

tSHSL1

tCSH

10

ns

/CS Deselect Time (for Erase/Program  Read SR)
Volatile Status Register Write Time

tSHSL2

tCSH

50

ns

Output Disable Time

tSHQZ

(2)

tDIS 7 ns

Clock Low to Output Valid

tCLQV1

tV1 6 ns

W25Q40EW

Continued – next page

Publication Release Date: August 18, 2018

- 69 - Preliminary-Revision J

AC Electrical Characteristics (cont’d)

DESCRIPTION

SYMBOL

ALT

SPEC

UNIT

MIN

TYP

MAX

Output Hold Time

tCLQX

tHO 0 ns

/HOLD Active Setup Time relative to CLK

tHLCH

5 ns

/HOLD Active Hold Time relative to CLK

tCHHH

5 ns

/HOLD Not Active Setup Time relative to CLK

tHHCH

5 ns

/HOLD Not Active Hold Time relative to CLK

tCHHL

5 ns

/HOLD to Output Low-Z

tHHQX

(2)

tLZ 7 ns

/HOLD to Output High-Z

tHLQZ

(2)

tHZ

12

ns

Write Protect Setup Time Before /CS Low

tWHSL

(3)

20

ns

Write Protect Hold Time After /CS High

tSHWL

(3)

100

ns

/CS High to Power-down Mode

tDP

(2)

3 µs

/CS High to Standby Mode without ID Read

tRES1

(2)

3 µs

/CS High to Standby Mode with ID Read

tRES2

(2)

1.8

µs

/CS High to next Instruction after Suspend

tSUS

(2)

20

µs

Write Status Register Time

tW

1

15

ms

Byte Program Time (First Byte)

(4)

t

BP1

15

30

µs

Additional Byte Program Time (After First Byte)

(4)

t

BP2

2.5 5 µs

Page Program Time

tPP

0.4

0.8

(5)

ms

Sector Erase Time (4KB)

tSE

45

400

ms

Block Erase Time (32KB)

tBE1

150

800

ms

Block Erase Time (64KB)

tBE2

180

1,000

ms

Chip Erase Time

tce

1 4 s

W25Q40EW

Notes:

1. Clock high + Clock low must be less than or equal to 1/fc.

2. Value guaranteed by design and/or characterization, not 100% tested in production.

3. Only applicable as a constraint for a Write Status Register instruction when SRP bit is set to 1.

4. For multiple bytes after first byte within a page, tBPN = tBP1 + tBP2 * N (typical) and tBPN = tBP1 + tBP2 * N (max), where N

= number of bytes programmed.

5. Maximum tPP value is specified with Page Program and 4KB Sector Erase(P/E) cycling condition.

- 70 -

8.7 Serial Output Timing

/CS

CLK

IO

output

tCLQX

tCLQV

tCLQX

tCLQV tSHQZtCLL

LSB OUT

tCLH

MSB OUT

/CS

CLK

IO

input

tCHSL

MSB IN

tSLCH

tDVCH tCHDX

tSHCHtCHSH

tCLCH tCHCL

LSB IN

tSHSL

/CS

CLK

IO

output

/HOLD

tCHHL

tHLCH

tCHHH

tHHCH

tHLQZ tHHQX

IO

input

/CS

CLK

/WP

tWHSL tSHWL

IO

input

Write Status Register is allowed Write Status Register is not allowed

8.8 Serial Input Timing

8.9 /HOLD Timing

W25Q40EW

8.10 /WP Timing

Publication Release Date: August 18, 2018

- 71 - Preliminary-Revision J

9. PACKAGE SPECIFICATION

L

O

c

D

A1

Aeb

SEATING P LANE

Y

0.25

GAUGE P LANE

E

H

E

1

8

5

4

SYMBOL

MILLIMETERS

INCHES

Min

Nom

Max

Min

Nom

Max

A

1.35

1.60

1.75

0.053

0.062

0.069

A1

0.10

0.15

0.25

0.004

0.006

0.010

b

0.33

0.41

0.51

0.013

0.016

0.020

C

0.19

0.20

0.25

0.0075

0.0078

0.0098

D

4.80

4.85

5.00

0.188

0.190

0.197

E

3.80

3.90

4.00

0.150

0.153

0.157

HE

5.80

6.00

6.20

0.228

0.236

0.244 e 1.27BSC

0.050BSC

L

0.40

0.71

1.27

0.016

0.027

0.050

y

---

---

0.10

---

---

0.004

∘

0°

---

10°

0°

---

10°

9.1 8-Pin SOIC 150-mil (Package Code SN)

W25Q40EW

- 72 -

9.2 8-Pin VSOP 150-mil (Package Code SV)

Symbol

Millimeters

Inches

Min

Nom

Max

Min

Nom

Max

A

---

---

0.90

---

---

0.035

A1

0.01

0.05

---

0.0004

0.002

---

A2

---

0.80

---

---

0.031

--- Q 0.19

0.20

0.21

0.007

0.008

0.008

b

0.33

---

0.51

0.013

---

0.020 c 0.125 BSC

0.005 BSC

D

4.80

4.90

5.00

0.189

0.193

0.197

E

5.80

6.00

6.20

0.228

0.236

0.244

E1

3.80

3.90

4.00

0.150

0.154

0.157 e 1.27 BSC

0.050 BSC

L

0.40

0.71

1.27

0.016

0.028

0.050 θ 0°

---

10°

0°

---

10°

W25Q40EW

Notes:

1. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusions and gate burrs shall not exceed

0.15mm per side.

2. Dimension “E1” does not include inter-lead flash or protrusions. Inter-lead flash and protrusions shall not exceed 0.25mm per

side.

Publication Release Date: August 18, 2018

- 73 - Preliminary-Revision J

9.3 8-Pad WSON 6x5-mm (Package Code ZP)

Symbol

Millimeters

Inches

Min

Nom

Max

Min

Nom

Max

A

0.70

0.75

0.80

0.028

0.030

0.031

A1

0.00

0.02

0.05

0.000

0.001

0.002

b

0.35

0.40

0.48

0.014

0.016

0.019

C

---

0.20 REF

---

---

0.008 REF

--- D 5.90

6.00

6.10

0.232

0.236

0.240

D2

3.35

3.40

3.45

0.132

0.134

0.136

E

4.90

5.00

5.10

0.193

0.197

0.201

E2

4.25

4.30

4.35

0.167

0.169

0.171

e

1.27 BSC

0.050 BSC

L

0.55

0.60

0.65

0.022

0.024

0.026

y

0.00

---

0.075

0.000

---

0.003

W25Q40EW

Note:

The metal pad area on the bottom center of the package is not connected to any internal electrical signals. It can be
left floating or connected to the device ground (GND pin). Avoid placement of exposed PCB vias under the pad.

- 74 -

W25Q40EW

9.4 8-Pad USON 2x3-mm (Package Code UXIE)

Notes:

1. Advanced Packaging Information; please contact Winbond for the latest minimum and maximum specifications.

2. BSC = Basic lead spacing between centers.

3. Dimensions D and E do not include mold flash protrusions and should be measured from the bottom of the package.

4. The metal pad area on the bottom center of the package is connected to the device ground (GND pin). Avoid placement of

exposed PCB vias under the pad.

Publication Release Date: August 18, 2018

- 75 - Preliminary-Revision J

Symbol

Millimeters

Inches

Min

Nom

Max

Min

Nom

Max

A

0.50

0.55

0.60

0.020

0.022

0.024

A1

0.00

0.02

0.05

0.000

0.001

0.002

A3

---

0.15

---

---

0.006

--- b 0.25

0.30

0.35

0.010

0.012

0.014

D

3.90

4.00

4.10

0.153

0.157

0.161

D1

0.70

0.80

0.90

0.027

0.031

0.035

D2

0.70

0.80

0.90

0.027

0.031

0.035

E

2.90

3.00

3.10

0.114

0.118

0.122

E1

0.10

0.20

0.30

0.004

0.008

0.012

e

0.80 BSC

0.031 BSC

L

0.55

0.60

0.65

0.022

0.024

0.026

W25Q40EW

9.5 8-Pad USON 4x3-mm (Package Code UU)

Note:

The metal pad area on the bottom center of the package is not connected to any internal electrical signals. It can be
left floating or connected to the device ground (GND pin). Avoid placement of exposed PCB vias under the pad.

- 76 -

9.6 8-Ball WLCSP (Package Code BY)

Symbol

Millimeters

Inches

Min

Nom

Max

Min

Nom

Max

A

0.270

0.300

0.330

0.0106

0.0118

0.0130

A1

0.048

0.068

0.088

0.0019

0.0027

0.0035

c

0.222

0.232

0.242

0.0087

0.0091

0.0095

D

1.300

1.340

1.380

0.0512

0.0528

0.0543

E

1.592

1.632

1.672

0.0627

0.0643

0.0658

D1

---

0.470

---

---

0.0185

---

E1

---

0.216

---

---

0.0085

---

eD

---

0.400

---

---

0.0157

---

eE

---

0.400

---

---

0.0157

---

b

0.220

0.250

0.280

0.0087

0.0098

0.0110

aaa

0.100

0.0040

bbb

0.100

0.0040

ccc

0.030

0.0012

ddd

0.150

0.0060

W25Q40EW

Notes:

1. Dimension b is measured at the maximum solder bump diameter, parallel to primary datum C.

Publication Release Date: August 18, 2018

- 77 - Preliminary-Revision J

W25Q40EW

W

(1)

25Q 40E W xx

(2)

W = Winbond

25Q = SpiFlash Serial Flash Memory with 4KB sectors, Dual/Quad I/O

40E = 4M-bit

W = 1.65V to 1.95V

SN = 8-pin SOIC 150-mil SV = 8-pin VSOP 150-mil ZP = 8-pad WSON 6x5mm
UX = 8-Pad USON 2x3mm UU = 8-Pad USON 4x3mm BY = 8-ball WLCSP

I = Industrial (-40°C to +85°C)

G = Green Package (Lead-free, RoHS Compliant, Halogen-free (TBBA), Antimony-Oxide-free Sb2O3)|
E = Green Package with Extended Pad

(2,3)

9.7 Ordering Information

Notes:

1. The “W” prefix is not included on the part marking.

2. Standard bulk shipments are in Tube (shape E). Please specify alternate packing method, such as Tape and

Reel (shape T) or Tray (shape S), when placing orders.

3. For shipments with OTP feature enabled, please contact Winbond

- 78 -

W25Q40EW

PACKAGE TYPE

DENSITY

PRODUCT NUMBER

TOP SIDE MARKING

SN

SOIC-8 150mil

4M-bit

W25Q40EWSNIG

25Q40EWNIG

SV

(1)

VSOP-8 150mil

4M-bit

W25Q40EWSVIG

25Q40EWVIG

ZP

(1)

WSON-8 6x5mm

4M-bit

W25Q40EWZPIG

25Q40EWIG

UX

USON 2x3mm

4M-bit

W25Q40EWUXIE

4Lyww

(3)

0Exxxx

(4)

UU

USON-8 4x3mm

4M-bit

W25Q40EWUUIG

Q40EWUUIG

BY

(2)

8-ball WLCSP

4M-bit

W25Q40EWBYIG

2AE

● yw

(3)

9.8 Valid Part Numbers and Top Side Marking

The following table provides the valid part numbers for the W25Q40EW SpiFlash Memory. Please contact
Winbond for specific availability by density and package type. Winbond SpiFlash memories use an 12-digit
Product Number for ordering. However, due to limited space, the Top Side Marking on all packages use
an abbreviated 5-10 digit number.

Notes:

1. These package types are special order only, please contact Winbond for more information.

2. WLCSP package type BY has special top marking due to size limitation.

3. “yw” is date code

Publication Release Date: August 18, 2018

- 79 - Preliminary-Revision J

10. REVISION J1ISTORY

VERSION

DATE

PAGE

DESCRIPTION

A

08/15/2014

All

New Create Preliminary

B

05/25/2015

All

Removed “Preliminary”

C

07/09/2015

10
65

Updated Operation Diagram
Removed note of 4 byte address alignment

D

07/28/2015

71

Added Mom value of SOIC8-150mm

E

09/01/2015

5-6,74,77-78

Added USON 4X3-mm Package

F

10/27/2015

5-6,73,77-78

Added WSON 6X5-mm Package

G

11/25/2015

7

5,20,56-59

Removed reset pin infroamtion
Updated SFDP infroamtion

H

01/16/2017

21
68

Updated instruncion table2
Updated AC mearusmnet codition

I

08/22/2017

72

Updated SOP-150mil HE value

J

07/18/2018

13

13-15

Modify notice
Added volatile description

W25Q40EW

Trademarks

Winbond and SpiFlash are trademarks of Winbond Electronics Corporation.
All other marks are the property of their respective owner.

Important Notice

Winbond products are not designed, intended, authorized or warranted for use as components in systems
or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship
instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for
other applications intended to support or sustain life. Furthermore, Winbond products are not intended for
applications wherein failure of Winbond products could result or lead to a situation wherein personal injury,
death or severe property or environmental damage could occur. Winbond customers using or selling these
products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any
damages resulting from such improper use or sales.

Information in this document is provided solely in connection with Winbond products. Winbond
reserves the right to make changes, corrections, modifications or improvements to this document
and the products and services described herein at any time, without notice.

- 80 -