Datasheet W25Q32FV Datasheet (Winbond) [ru]

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3V 32M-BIT SERIAL FLASH MEMORY WITH DUAL/QUAD SPI & QPI

W25Q32FV

Publication Release Date: Sept 16, 2013

Revision H

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W25Q32FV

Table of Contents

GENERAL DESCRIPTIONS ............................................................................................................. 5

FEATURES ....................................................................................................................................... 5

PACKAGE TYPES AND PIN CONFIGURATIONS ........................................................................... 6

3.1 Pin Configuration SOIC 208-mil / VSOP 208-mil .................................................................. 6

3.2 Pad Configuration WSON 6x5-mm / 8x6-mm ...................................................................... 6

3.3 Pin Description SOIC / VSOP 208-mil, WSON 6x5-mm / 8x6-mm ...................................... 6

3.4 Pin Configuration SOIC 300-mil ........................................................................................... 7

3.5 Pin Description SOIC 300-mil ............................................................................................... 7

3.6 Ball Configuration TFBGA 8x6-mm (5x5 or 6x4 Ball Array) ................................................. 8

3.7 Ball Description TFBGA 8x6-mm ......................................................................................... 8

3.8 Pin Configuration PDIP 300-mil ............................................................................................ 9

3.9 Pin Description PDIP 300-mil ............................................................................................... 9

PIN DESCRIPTIONS ...................................................................................................................... 10

4.1 Chip Select (/CS) ................................................................................................................ 10

4.2 Serial Data Input, Output and IOs (DI, DO and IO0, IO1, IO2, IO3) ................................... 10

4.3 Write Protect (/WP) ............................................................................................................ 10

4.4 HOLD (/HOLD) ................................................................................................................... 10

4.5 Serial Clock (CLK) .............................................................................................................. 10

4.6 Reset (/RESET) .................................................................................................................. 10

BLOCK DIAGRAM .......................................................................................................................... 11

FUNCTIONAL DESCRIPTIONS ..................................................................................................... 12

6.1 SPI / QPI Operations .......................................................................................................... 12

6.1.1 Standard SPI Instructions .................................................................................................... 12

6.1.2 Dual SPI Instructions ............................................................................................................ 12

6.1.3 Quad SPI Instructions .......................................................................................................... 13

6.1.4 QPI Instructions .................................................................................................................... 13

6.1.5 Hold Function ....................................................................................................................... 13

6.1.6 Software Reset & Hardware /RESET pin ............................................................................. 14

6.2 Write Protection .................................................................................................................. 15

6.2.1 Write Protect Features ......................................................................................................... 15

STATUS AND CONFIGURATION REGISTERS ............................................................................ 16

7.1 Status Registers ................................................................................................................. 16

7.1.1 Erase/Write In Progress (BUSY) – Status Only ................................................................... 16

7.1.2 Write Enable Latch (WEL) – Status Only ............................................................................. 16

7.1.3 Block Protect Bits (BP2, BP1, BP0) – Volatile/Non-Volatile Writable ................................... 16

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W25Q32FV

7.1.4 Top/Bottom Block Protect (TB) – Volatile/Non-Volatile Writable .......................................... 17

7.1.5 Sector/Block Protect Bit (SEC) – Volatile/Non-Volatile Writable .......................................... 17

7.1.6 Complement Protect (CMP) – Volatile/Non-Volatile Writable ............................................... 17

7.1.7 Status Register Protect (SRP1, SRP0) – Volatile/Non-Volatile Writable .............................. 17

7.1.8 Erase/Program Suspend Status (SUS) – Status Only ......................................................... 18

7.1.9 Security Register Lock Bits (LB3, LB2, LB1) – Volatile/Non-Volatile OTP Writable ............. 18

7.1.10 Quad Enable (QE) – Volatile/Non-Volatile Writable ........................................................... 18

7.1.11 Write Protect Selection (WPS) – Volatile/Non-Volatile Writable ........................................ 19

7.1.12 Output Driver Strength (DRV1, DRV0) – Volatile/Non-Volatile Writable ............................ 19

7.1.13 HOLD or /RESET Pin Function (HOLD/RST) – Volatile/Non-Volatile Writable .................. 19

7.1.14 Reserved Bits – Non Functional ......................................................................................... 20

7.1.15 W25Q32FV Status Register Memory Protection (WPS = 0, CMP = 0) .............................. 21

7.1.16 W25Q32FV Status Register Memory Protection (WPS = 0, CMP = 1) .............................. 22

7.1.17 W25Q32FV Individual Block Memory Protection (WPS=1) ............................................... 23

INSTRUCTIONS ............................................................................................................................. 24

8.1 Device ID and Instruction Set Tables ................................................................................. 24

8.1.1 Manufacturer and Device Identification ................................................................................ 24

8.1.2 Instruction Set Table 1 (Standard/Dual/Quad SPI Instructions)

8.1.3 Instruction Set Table 2 (Standard/Dual/Quad SPI Instructions)

8.1.4 Instruction Set Table 3 (QPI Instructions)

8.2 Instruction Descriptions ...................................................................................................... 29

8.2.1 Write Enable (06h) ............................................................................................................... 29

8.2.2 Write Enable for Volatile Status Register (50h) ................................................................... 29

8.2.3 Write Disable (04h) .............................................................................................................. 30

8.2.4 Read Status Register-1 (05h), Status Register-2 (35h) & Status Register-3 (15h) .............. 30

8.2.5 Write Status Register-1 (01h), Status Register-2 (31h) & Status Register-3 (11h) .............. 31

8.2.6 Read Data (03h) ................................................................................................................... 34

8.2.7 Fast Read (0Bh) ................................................................................................................... 35

8.2.8 Fast Read Dual Output (3Bh) ............................................................................................... 37

8.2.9 Fast Read Quad Output (6Bh) ............................................................................................. 38

8.2.10 Fast Read Dual I/O (BBh) .................................................................................................. 39

8.2.11 Fast Read Quad I/O (EBh) ................................................................................................. 41

8.2.12 Word Read Quad I/O (E7h) ................................................................................................ 44

8.2.13 Octal Word Read Quad I/O (E3h) ...................................................................................... 46

8.2.14 Set Burst with Wrap (77h) .................................................................................................. 48

8.2.15 Page Program (02h) ........................................................................................................... 49

8.2.16 Quad Input Page Program (32h) ........................................................................................ 51

8.2.17 Sector Erase (20h) ............................................................................................................. 52

8.2.18 32KB Block Erase (52h) ..................................................................................................... 53

8.2.19 64KB Block Erase (D8h) .................................................................................................... 54

8.2.20 Chip Erase (C7h / 60h) ...................................................................................................... 55

(14)

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(1)

........................................ 25

(1)

........................................ 26

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8.2.21 Erase / Program Suspend (75h) ........................................................................................ 56

8.2.22 Erase / Program Resume (7Ah) ......................................................................................... 58

8.2.23 Power-down (B9h) .............................................................................................................. 59

8.2.24 Release Power-down / Device ID (ABh)............................................................................. 60

8.2.25 Read Manufacturer / Device ID (90h) ................................................................................. 62

8.2.26 Read Manufacturer / Device ID Dual I/O (92h) .................................................................. 63

8.2.27 Read Manufacturer / Device ID Quad I/O (94h) ................................................................. 64

8.2.28 Read Unique ID Number (4Bh) .......................................................................................... 65

8.2.29 Read JEDEC ID (9Fh) ........................................................................................................ 66

8.2.30 Read SFDP Register (5Ah) ................................................................................................ 67

8.2.31 Erase Security Registers (44h) .......................................................................................... 68

8.2.32 Program Security Registers (42h) ...................................................................................... 69

8.2.33 Read Security Registers (48h) ........................................................................................... 70

8.2.34 Set Read Parameters (C0h) ............................................................................................... 71

8.2.35 Burst Read with Wrap (0Ch) .............................................................................................. 72

8.2.36 Enter QPI Mode (38h) ........................................................................................................ 73

8.2.37 Exit QPI Mode (FFh) .......................................................................................................... 74

8.2.38 Individual Block/Sector Lock (36h) ..................................................................................... 75

8.2.39 Individual Block/Sector Unlock (39h) ................................................................................. 76

8.2.40 Read Block/Sector Lock (3Dh) ........................................................................................... 77

8.2.41 Global Block/Sector Lock (7Eh) ......................................................................................... 78

8.2.42 Global Block/Sector Unlock (98h) ...................................................................................... 78

8.2.43 Enable Reset (66h) and Reset Device (99h)...................................................................... 79

ELECTRICAL CHARACTERISTICS ............................................................................................... 80

9.1 Absolute Maximum Ratings

9.2 Operating Ranges............................................................................................................... 80

9.3 Power-Up Power-Down Timing and Requirements

9.4 DC Electrical Characteristics

9.5 AC Measurement Conditions

9.6 AC Electrical Characteristics

9.7 Serial Output Timing ........................................................................................................... 86

9.8 Serial Input Timing .............................................................................................................. 86

9.9 HOLD Timing ...................................................................................................................... 86

9.10 WP Timing .......................................................................................................................... 86

10. PACKAGE SPECIFICATIONS ........................................................................................................ 87

10.1 8-Pin SOIC 208-mil (Package Code SS) ............................................................................ 87

10.2 8-Pin VSOP 208-mil (Package Code ST) ........................................................................... 88

10.3 8-Pad WSON 6x5-mm (Package Code ZP) ....................................................................... 89

10.4 8-Pad WSON 8x6-mm (Package Code ZE) ....................................................................... 90

(1)(2)

................................................................................... 80

(1)

....................................................... 81

(1)

.......................................................................................... 82

(1)

......................................................................................... 83

(6)

........................................................................................... 84

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W25Q32FV

10.5 16-Pin SOIC 300-mil (Package Code SF) .......................................................................... 91

10.6 8-Pin PDIP 300-mil (Package Code DA) ............................................................................ 92

10.7 24-Ball TFBGA 8x6-mm (Package Code TB, 5x5-1 ball array) .......................................... 93

10.8 24-Ball TFBGA 8x6-mm (Package Code TC, 6x4 ball array) ............................................. 94

11. ORDERING INFORMATION .......................................................................................................... 95

11.1 Valid Part Numbers and Top Side Marking ........................................................................ 96

12. REVISION HISTORY ...................................................................................................................... 97

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W25Q32FV

1. GENERAL DESCRIPTIONS

The W25Q32FV (32M-bit) Serial Flash memory provides a storage solution for systems with limited space, pins and power. The 25Q series offers flexibility and performance well beyond ordinary Serial Flash devices. They are ideal for code shadowing to RAM, executing code directly from Dual/Quad SPI (XIP) and storing voice, text and data. The device operates on a single 2.7V to 3.6V power supply with current consumption as low as 4mA active and 1µA for power-down. All devices are offered in space-saving packages.

The W25Q32FV array is organized into 16,384 programmable pages of 256-bytes each. Up to 256 bytes can be programmed at a time. Pages can be erased in groups of 16 (4KB sector erase), groups of 128 (32KB block erase), groups of 256 (64KB block erase) or the entire chip (chip erase). The W25Q32FV has 1,024 erasable sectors and 64 erasable blocks respectively. The small 4KB sectors allow for greater flexibility in applications that require data and parameter storage. (See Figure 2.)

The W25Q32FV support the standard Serial Peripheral Interface (SPI), Dual/Quad I/O SPI as well as 2clocks instruction cycle Quad Peripheral Interface (QPI): Serial Clock, Chip Select, Serial Data I/O0 (DI), I/O1 (DO), I/O2 (/WP), and I/O3 (/HOLD). SPI clock frequencies of up to 104MHz are supported allowing equivalent clock rates of 208MHz (104MHz x 2) for Dual I/O and 416MHz (104MHz x 4) for Quad I/O when using the Fast Read Dual/Quad I/O and QPI instructions. These transfer rates can outperform standard Asynchronous 8 and 16-bit Parallel Flash memories. The Continuous Read Mode allows for efficient memory access with as few as 8-clocks of instruction-overhead to read a 24-bit address, allowing true XIP (execute in place) operation.

A Hold pin, Write Protect pin and programmable write protection, with top or bottom array control, provide further control flexibility. Additionally, the device supports JEDEC standard manufacturer and device ID and SFDP Register, a 64-bit Unique Serial Number and three 256-bytes Security Registers.

2. FEATURES

• New Family of SpiFlash Memories – W25Q32FV: 32M-bit / 4M-byte – Standard SPI: CLK, /CS, DI, DO, /WP, /Hold – Dual SPI: CLK, /CS, IO0, IO1, /WP, /Hold – Quad SPI: CLK, /CS, IO0, IO1, IO2, IO – QPI: CLK, /CS, IO0, IO1, IO2, IO3 – Software & Hardware Reset

• Highest Performance Serial Flash – 104MHz Single, Dual/Quad SPI clocks – 208/416MHz equivalent Dual/Quad SPI – 50MB/S continuous data transfer rate – More than 100,000 erase/program cycles – More than 20-year data retention

• Efficient “Continuous Read” and QPI Mode – Continuous Read with 8/16/32/64-Byte Wrap – As few as 8 clocks to address memory – Quad Peripheral Interface (QPI) reduces

instruction overhead – Allows true XIP (execute in place) operation – Outperforms X16 Parallel Flash

• Low Power, Wide Temperature Range – Single 2.7 to 3.6V supply

– 4mA active current, <1µA Power-down (typ.) – -40°C to +85°C operating range

• Flexible Architecture with 4KB sectors – Uniform Sector/Block Erase (4K/32K/64K-Byte) – Program 1 to 256 byte per programmable page – Erase/Program Suspend & Resume

• Advanced Security Features – Software and Hardware Write-Protect – Power Supply Lock-Down and OTP protection – Top/Bottom, Complement array protection – Individual Block/Sector array protection – 64-Bit Unique ID for each device – Discoverable Parameters (SFDP) Register – 3X256-Bytes Security Registers with OTP locks – Volatile & Non-volatile Status Register Bits

• Space Efficient Packaging

– 8-pin SOIC 208-mil / VSOP 208-mil – 8-pad WSON 6x5-mm / 8x6-mm – 16-pin SOIC 300-mil (additional /RESET pin) – 8-pin PDIP 300-mil – 24-ball TFBGA 8x6-mm (6x4/5x5 ball array) – Contact Winbond for KGD and other options

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3. PACKAGE TYPES AND PIN CONFIGURATIONS

3.1 Pin Configuration SOIC 208-mil / VSOP 208-mil

Figure 1a. W25Q32FV Pin Assignments, 8-pin SOIC / VSOP 208-mil (Package Code SS / ST)

3.2 Pad Configuration WSON 6x5-mm / 8x6-mm

W25Q32FV

Figure 1b. W25Q32FV Pad Assignments, 8-pad WSON 6x5-mm / 8x6-mm (Package Code ZP / ZE)

3.3 Pin Description SOIC / VSOP 208-mil, WSON 6x5-mm / 8x6-mm

PIN NO. PIN NAME I/O FUNCTION

1 /CS I Chip Select Input 2 DO (IO1) I/O 3 /WP (IO2) I/O 4 GND Ground 5 DI (IO0) I/O 6 CLK I Serial Clock Input

7 8 VCC Power Supply

Notes:

1. IO0 and IO1 are used for Standard and Dual SPI instructions

2. IO0 – IO3 are used for Quad SPI instructions, /WP & /HOLD (or /RESET) functions are only available for Standard/Dual SPI.

/HOLD or /RESET

(IO3)

I/O

Data Output (Data Input Output 1) Write Protect Input ( Data Input Output 2)

Data Input (Data Input Output 0)

Hold or Reset Input (Data Input Output 3)

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(1)

(2)

(1)

(2)

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W25Q32FV

3.4 Pin Configuration SOIC 300-mil

Figure 1c. W25Q32FV Pin Assignments, 16-pin SOIC 300-mil (Package Code SF)

3.5 Pin Description SOIC 300-mil

PIN NO. PIN NAME I/O FUNCTION

1 /HOLD (IO3) I/O Hold Input (Data Input Output 3) 2 VCC Power Supply 3 /RESET I Reset Input

(3)

4 N/C No Connect 5 N/C No Connect 6 N/C No Connect 7 /CS I Chip Select Input 8 DO (IO1) I/O Data Output (Data Input Output 1)

9 /WP (IO2) I/O Write Protect Input (Data Input Output 2) 10 GND Ground 11 N/C No Connect 12 N/C No Connect 13 N/C No Connect 14 N/C No Connect 15 DI (IO0) I/O Data Input (Data Input Output 0) 16 CLK I Serial Clock Input

Notes:

1. IO0 and IO1 are used for Standard and Dual SPI instructions

2. IO0 – IO3 are used for Quad SPI instructions, /WP & /HOLD (or /RESET) functions are only available for Standard/Dual SPI.

3. The /RESET pin on SOIC-16 package is independent of the HOLD/RST bit and QE bit settings in the Status Register. This pin can be left floating, if Rest function is not needed.

(2)

(1)

(2)

(1)

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3.6 Ball Configuration TFBGA 8x6-mm (5x5 or 6x4 Ball Array)

Figure 1d. W25Q32FV Ball Assignments, 24-ball TFBGA 8x6-mm (Package Code TB & TC)

W25Q32FV

3.7 Ball Description TFBGA 8x6-mm

BALL NO.

B2 CLK I Serial Clock Input B3 GND Ground

B4 VCC Power Supply C2 /CS I Chip Select Input C4 /WP (IO2) I/O Write Protect Input (Data Input Output 2) D2 DO (IO1) I/O Data Output (Data Input Output 1) D3 DI (IO0) I/O Data Input (Data Input Output 0)

Multiple NC No Connect

Notes:

1. IO0 and IO1 are used for Standard and Dual SPI instructions

2. IO0 – IO3 are used for Quad SPI instructions, /WP & /HOLD (or /RESET) functions are only available for Standard/Dual SPI.

PIN NAME I/O FUNCTION

/HOLD or /RESET

(IO3)

I/O Hold or Reset Input (Data Input Output 3)

(2)

(1)

(2)

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W25Q32FV

3.8 Pin Configuration PDIP 300-mil

Figure 1e. W25Q32FV Pin Assignments, 8-pin PDIP (Package Code DA)

3.9 Pin Description PDIP 300-mil

PIN NO. PIN NAME I/O FUNCTION

1 /CS I Chip Select Input 2 DO (IO1) I/O 3 /WP (IO2) I/O 4 GND Ground 5 DI (IO0) I/O 6 CLK I Serial Clock Input

7 8 VCC Power Supply

Notes:

1. IO0 and IO1 are used for Standard and Dual SPI instructions

2. IO0 – IO3 are used for Quad SPI instructions, /WP & /HOLD (or /RESET) functions are only available for Standard/Dual SPI.

/HOLD or /RESET

(IO3)

I/O

Data Output (Data Input Output 1) Write Protect Input ( Data Input Output 2)

Data Input (Data Input Output 0)

Hold or Reset Input (Data Input Output 3)

(1)

(2)

(1)

(2)

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W25Q32FV

4. PIN DESCRIPTIONS

4.1 Chip Select (/CS)

The SPI Chip Select (/CS) pin enables and disables device operation. When /CS is high the device is deselected and the Serial Data Output (DO, or IO0, IO1, IO2, IO3) pins are at high impedance. When deselected, the devices power consumption will be at standby levels unless an internal erase, program or write status register cycle is in progress. When /CS is brought low the device will be selected, power consumption will increase to active levels and instructions can be written to and data read from the device. After power-up, /CS must transition from high to low before a new instruction will be accepted. The /CS input must track the VCC supply level at power-up and power-down (see “Write Protection” and Figure

58). If needed a pull-up resister on the /CS pin can be used to accomplish this.

4.2 Serial Data Input, Output and IOs (DI, DO and IO0, IO1, IO2, IO3)

The W25Q32FV supports standard SPI, Dual SPI and Quad SPI operation. Standard SPI instructions use the unidirectional DI (input) pin to serially write instructions, addresses or data to the device on the rising edge of the Serial Clock (CLK) input pin. Standard SPI also uses the unidirectional DO (output) to read data or status from the device on the falling edge of CLK.

Dual and Quad SPI instructions use the bidirectional IO pins to serially write instructions, addresses or data to the device on the rising edge of CLK and read data or status from the device on the falling edge of CLK. Quad SPI instructions require the non-volatile Quad Enable bit (QE) in Status Register-2 to be set. When QE=1, the /WP pin becomes IO2 and /HOLD pin becomes IO3.

4.3 Write Protect (/WP)

The Write Protect (/WP) pin can be used to prevent the Status Register from being written. Used in conjunction with the Status Register’s Block Protect (CMP, SEC, TB, BP2, BP1 and BP0) bits and Status Register Protect (SRP) bits, a portion as small as a 4KB sector or the entire memory array can be hardware protected. The /WP pin is active low. When the QE bit of Status Register-2 is set for Quad I/O, the /WP pin function is not available since this pin is used for IO2. See Figure 1a-c for the pin configuration of Quad I/O operation.

4.4 HOLD (/HOLD)

The /HOLD pin allows the device to be paused while it is actively selected. When /HOLD is brought low, while /CS is low, the DO pin will be at high impedance and signals on the DI and CLK pins will be ignored (don’t care). When /HOLD is brought high, device operation can resume. The /HOLD function can be useful when multiple devices are sharing the same SPI signals. The /HOLD pin is active low. When the QE bit of Status Register-2 is set for Quad I/O, the /HOLD pin function is not available since this pin is used for IO3. See Figure 1a-e for the pin configuration of Quad I/O operation.

4.5 Serial Clock (CLK)

The SPI Serial Clock Input (CLK) pin provides the timing for serial input and output operations. ("See SPI Operations")

4.6 Reset (/RESET)

The /RESET pin allows the device to be reset by the controller. For 8-pin packages, when QE=0, the IO3 pin can be configured either as a /HOLD pin or as a /RESET pin depending on Status Register setting. When QE=1, the /HOLD or /RESET function is not available for 8-pin configuration. On the 16-pin SOIC package, a dedicated /RESET pin is provided and it is independent of QE bit setting.

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5. BLOCK DIAGRAM

W25Q32FV

/WP (IO2)

/HOLD (IO3) or

/RESET (IO3)

CLK

/CS

DI (IO0)

DO (IO1)

SFDP Register

000000h 0000FFh

Block Segmentation

xxFF00h xxFFFFh

• Sector 15 (4KB) •

xxF000h xxF0FFh

xxEF00h xxEFFFh

• Sector 14 (4KB) •

xxE000h xxE0FFh xxDF00h xxDFFFh

• Sector 13 (4KB) •

xxD000h xxD0FFh

•

xx2F00h xx2FFFh

• Sector 2 (4KB) •

xx2000h xx20FFh xx1F00h xx1FFFh

• Sector 1 (4KB) •

xx1000h xx10FFh xx0F00h xx0FFFh

• Sector 0 (4KB) •

xx0000h xx00FFh

Write Control

Logic

Status

SPI

Command &

Control Logic

High Voltage

Generators

Page Address

Latch / Counter

Data

Byte Address

Latch / Counter

Security Register 1 - 3

003000h 0030FFh 002000h 0020FFh 001000h 0010FFh

3FFF00h 3FFFFFh

• Block 63 (64KB) •

3F0000h 3F00FFh

•

20FF00h 20FFFFh

• Block 32 (64KB) •

200000h 2000FFh

1FFF00h 1FFFFFh

• Block 31 (64KB) •

1F0000h 1F00FFh

Write Protect Logic and Row Decode

10FF00h 10FFFFh

• Block 16 (64KB) •

100000h 1000FFh

0FFF00h 0FFFFFh

• Block 15 (64KB) •

0F0000h 0F00FFh

00FF00h 00FFFFh

• Block 0 (64KB) •

000000h 0000FFh

Beginning

Page Address

And 256-Byte Page Buffer

•

Column Decode

Ending Page Address

W25Q32FV

Figure 2. W25Q32FV Serial Flash Memory Block Diagram

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6. FUNCTIONAL DESCRIPTIONS

6.1 SPI / QPI Operations

W25Q32FV

Figure 3. W25Q32FV Serial Flash Memory Operation Diagram

6.1.1 Standard SPI Instructions

The W25Q32FV is accessed through an SPI compatible bus consisting of four signals: Serial Clock (CLK), Chip Select (/CS), Serial Data Input (DI) and Serial Data Output (DO). Standard SPI instructions use the DI input pin to serially write instructions, addresses or data to the device on the rising edge of CLK. The DO output pin is used to read data or status from the device on the falling edge of CLK.

SPI bus operation Mode 0 (0,0) and 3 (1,1) are supported. The primary difference between Mode 0 and Mode 3 concerns the normal state of the CLK signal when the SPI bus master is in standby and data is not being transferred to the Serial Flash. For Mode 0, the CLK signal is normally low on the falling and rising edges of /CS. For Mode 3, the CLK signal is normally high on the falling and rising edges of /CS.

6.1.2 Dual SPI Instructions

The W25Q32FV supports Dual SPI operation when using instructions such as “Fast Read Dual Output (3Bh)” and “Fast Read Dual I/O (BBh)”. These instructions allow data to be transferred to or from the device at two to three times the rate of ordinary Serial Flash devices. The Dual SPI Read instructions are ideal for quickly downloading code to RAM upon power-up (code-shadowing) or for executing non-speedcritical code directly from the SPI bus (XIP). When using Dual SPI instructions, the DI and DO pins become bidirectional I/O pins: IO0 and IO1.

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W25Q32FV

6.1.3 Quad SPI Instructions

The W25Q32FV supports Quad SPI operation when using instructions such as “Fast Read Quad Output (6Bh)”, “Fast Read Quad I/O (EBh)”, “Word Read Quad I/O (E7h)” and “Octal Word Read Quad I/O (E3h)”. These instructions allow data to be transferred to or from the device four to six times the rate of ordinary Serial Flash. The Quad Read instructions offer a significant improvement in continuous and random access transfer rates allowing fast code-shadowing to RAM or execution directly from the SPI bus (XIP). When using Quad SPI instructions the DI and DO pins become bidirectional IO0 and IO1, and the /WP and /HOLD pins become IO2 and IO3 respectively. Quad SPI instructions require the nonvolatile Quad Enable bit (QE) in Status Register-2 to be set.

6.1.4 QPI Instructions

The W25Q32FV supports Quad Peripheral Interface (QPI) operations only when the device is switched from Standard/Dual/Quad SPI mode to QPI mode using the “Enter QPI (38h)” instruction. The typical SPI protocol requires that the byte-long instruction code being shifted into the device only via DI pin in eight serial clocks. The QPI mode utilizes all four IO pins to input the instruction code, thus only two serial clocks are required. This can significantly reduce the SPI instruction overhead and improve system performance in an XIP environment. Standard/Dual/Quad SPI mode and QPI mode are exclusive. Only one mode can be active at any given time. “Enter QPI (38h)” and “Exit QPI (FFh)” instructions are used to switch between these two modes. Upon power-up or after a software reset using “Reset (99h)” instruction, the default state of the device is Standard/Dual/Quad SPI mode. To enable QPI mode, the non-volatile Quad Enable bit (QE) in Status Register-2 is required to be set. When using QPI instructions, the DI and DO pins become bidirectional IO0 and IO1, and the /WP and /HOLD pins become IO2 and IO3 respectively. See Figure 3 for the device operation modes.

6.1.5 Hold Function

For Standard SPI and Dual SPI operations, the /HOLD signal allows the W25Q32FV operation to be paused while it is actively selected (when /CS is low). The /HOLD function may be useful in cases where the SPI data and clock signals are shared with other devices. For example, consider if the page buffer was only partially written when a priority interrupt requires use of the SPI bus. In this case the /HOLD function can save the state of the instruction and the data in the buffer so programming can resume where it left off once the bus is available again. The /HOLD function is only available for standard SPI and Dual SPI operation, not during Quad SPI or QPI. The Quad Enable Bit QE in Status Register-2 is used to determine if the pin is used as /HOLD pin or data I/O pin. When QE=0 (factory default), the pin is /HOLD, when QE=1, the pin will become an I/O pin, /HOLD function is no longer available.

To initiate a /HOLD condition, the device must be selected with /CS low. A /HOLD condition will activate on the falling edge of the /HOLD signal if the CLK signal is already low. If the CLK is not already low the /HOLD condition will activate after the next falling edge of CLK. The /HOLD condition will terminate on the rising edge of the /HOLD signal if the CLK signal is already low. If the CLK is not already low the /HOLD condition will terminate after the next falling edge of CLK. During a /HOLD condition, the Serial Data Output (DO) is high impedance, and Serial Data Input (DI) and Serial Clock (CLK) are ignored. The Chip Select (/CS) signal should be kept active (low) for the full duration of the /HOLD operation to avoid resetting the internal logic state of the device.

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W25Q32FV

6.1.6 Software Reset & Hardware /RESET pin

The W25Q32FV can be reset to the initial power-on state by a software Reset sequence, either in SPI mode or QPI mode. This sequence must include two consecutive commands: Enable Reset (66h) & Reset (99h). If the command sequence is successfully accepted, the device will take approximately 30uS (

RST

)

to reset. No command will be accepted during the reset period.

For the WSON-8 and TFBGA package types, W25Q32FV can also be configured to utilize a hardware /RESET pin. The HOLD/RST bit in the Status Register-3 is the configuration bit for /HOLD pin function or RESET pin function. When HOLD/RST=0 (factory default), the pin acts as a /HOLD pin as described above; when HOLD/RST=1, the pin acts as a /RESET pin. Drive the /RESET pin low for a minimum period of ~1us (tRESET*) will reset the device to its initial power-on state. Any on-going Program/Erase operation will be interrupted and data corruption may happen. While /RESET is low, the device will not accept any command input.

If QE bit is set to 1, the /HOLD or /RESET function will be disabled, the pin will become one of the four data I/O pins.

For the SOIC-16 package, W25Q32FV provides a dedicated /RESET pin in addition to the /HOLD (IO3) pin as illustrated in Figure 1b. Drive the /RESET pin low for a minimum period of ~1us (tRESET*) will reset the device to its initial power-on state. The HOLD/RST bit or QE bit in the Status Register will not affect the function of this dedicated /RESET pin.

Hardware /RESET pin has the highest priority among all the input signals. Drive /RESET low for a minimum period of ~1us (tRESET*) will interrupt any on-going external/internal operations, regardless the status of other SPI signals (/CS, CLK, IOs, /WP and/or /HOLD).

Note:

1.While a faster /RESET pulse (as short as a few hundred nanoseconds) will often reset the device, a 1us minimum is recommended to ensure reliable operation.

2.There is an internal pull-up resistor for the dedicated /RESET pin on the SOIC-16 package. If the reset function is not needed, this pin can be left floating in the system.

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6.2 Write Protection

Applications that use non-volatile memory must take into consideration the possibility of noise and other adverse system conditions that may compromise data integrity. To address this concern, the W25Q32FV provides several means to protect the data from inadvertent writes.

6.2.1 Write Protect Features

• Device resets when VCC is below threshold

• Time delay write disable after Power-up

• Write enable/disable instructions and automatic write disable after erase or program

• Software and Hardware (/WP pin) write protection using Status Registers

• Additional Individual Block/Sector Locks for array protection

• Write Protection using Power-down instruction

• Lock Down write protection for Status Register until the next power-up

• One Time Program (OTP) write protection for array and Security Registers using Status Register*

* Note: This feature is available upon special order. Please contact Winbond for details.

Upon power-up or at power-down, the W25Q32FV will maintain a reset condition while VCC is below the threshold value of VWI, (See Power-up Timing and Voltage Levels and Figure 43). While reset, all operations are disabled and no instructions are recognized. During power-up and after the VCC voltage exceeds VWI, all program and erase related instructions are further disabled for a time delay of t includes the Write Enable, Page Program, Sector Erase, Block Erase, Chip Erase and the Write Status Register instructions. Note that the chip select pin (/CS) must track the VCC supply level at power-up until the VCC-min level and t down to prevent adverse command sequence. If needed a pull-up resister on /CS can be used to accomplish this.

After power-up the device is automatically placed in a write-disabled state with the Status Register Write Enable Latch (WEL) set to a 0. A Write Enable instruction must be issued before a Page Program, Sector Erase, Block Erase, Chip Erase or Write Status Register instruction will be accepted. After completing a program, erase or write instruction the Write Enable Latch (WEL) is automatically cleared to a writedisabled state of 0.

Software controlled write protection is facilitated using the Write Status Register instruction and setting the Status Register Protect (SRP0, SRP1) and Block Protect (CMP, SEC, TB, BP[2:0]) bits. These settings allow a portion or the entire memory array to be configured as read only. Used in conjunction with the Write Protect (/WP) pin, changes to the Status Register can be enabled or disabled under hardware control. See Status Register section for further information. Additionally, the Power-down instruction offers an extra level of write protection as all instructions are ignored except for the Release Power-down instruction.

The W25Q32FV also provides another Write Protect method using the Individual Block Locks. Each 64KB block (except the top and bottom blocks, total of 510 blocks) and each 4KB sector within the top/bottom blocks (total of 32 sectors) are equipped with an Individual Block Lock bit. When the lock bit is 0, the corresponding sector or block can be erased or programmed; when the lock bit is set to 1, Erase or Program commands issued to the corresponding sector or block will be ignored. When the device is powered on, all Individual Block Lock bits will be 1, so the entire memory array is protected from Erase/Program. An “Individual Block Unlock (39h)” instruction must be issued to unlock any specific sector or block.

The WPS bit in Status Register-3 is used to decide which Write Protect scheme should be used. When WPS=0 (factory default), the device will only utilize CMP, SEC, TB, BP[2:0] bits to protect specific areas of the array; when WPS=1, the device will utilize the Individual Block Locks for write protection.

VSL

time delay is reached, and it must also track the VCC supply level at power-

PUW

. This

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W25Q32FV

7. STATUS AND CONFIGURATION REGISTERS

Three Status and Configuration Registers are provided for W25Q32FV. The Read Status Register-1/2/3 instructions can be used to provide status on the availability of the flash memory array, whether the device is write enabled or disabled, the state of write protection, Quad SPI setting, Security Register lock status, Erase/Program Suspend status, output driver strength, power-up and current Address Mode. The Write Status Register instruction can be used to configure the device write protection features, Quad SPI setting, Security Register OTP locks, Hold/Reset functions, output driver strength and power-up Address Mode. Write access to the Status Register is controlled by the state of the non-volatile Status Register Protect bits (SRP0, SRP1), the Write Enable instruction, and during Standard/Dual SPI operations, the /WP pin.

7.1 Status Registers

Figure 4a. Status Register-1

7.1.1 Erase/Write In Progress (BUSY) – Status Only

BUSY is a read only bit in the status register (S0) that is set to a 1 state when the device is executing a Page Program, Quad Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register or Erase/Program Security Register instruction. During this time the device will ignore further instructions except for the Read Status Register and Erase/Program Suspend instruction (see tW, tPP, tSE, tBE, and tCE in AC Characteristics). When the program, erase or write status/security register instruction has completed, the BUSY bit will be cleared to a 0 state indicating the device is ready for further instructions.

7.1.2 Write Enable Latch (WEL) – Status Only

Write Enable Latch (WEL) is a read only bit in the status register (S1) that is set to 1 after executing a Write Enable Instruction. The WEL status bit is cleared to 0 when the device is write disabled. A write disable state occurs upon power-up or after any of the following instructions: Write Disable, Page Program, Quad Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register, Erase Security Register and Program Security Register.

7.1.3 Block Protect Bits (BP2, BP1, BP0) – Volatile/Non-Volatile Writable

The Block Protect Bits (BP2, BP1, BP0) are non-volatile read/write bits in the status register (S4, S3, and S2) that provide Write Protection control and status. Block Protect bits can be set using the Write Status Register Instruction (see tW in AC characteristics). All, none or a portion of the memory array can be protected from Program and Erase instructions (see Status Register Memory Protection table). The factory default setting for the Block Protection Bits is 0, none of the array protected.

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7.1.4 Top/Bottom Block Protect (TB) – Volatile/Non-Volatile Writable

The non-volatile Top/Bottom bit (TB) controls if the Block Protect Bits (BP2, BP1, BP0) protect from the Top (TB=0) or the Bottom (TB=1) of the array as shown in the Status Register Memory Protection table. The factory default setting is TB=0. The TB bit can be set with the Write Status Register Instruction depending on the state of the SRP0, SRP1 and WEL bits.

7.1.5 Sector/Block Protect Bit (SEC) – Volatile/Non-Volatile Writable

The non-volatile Sector/Block Protect bit (SEC) controls if the Block Protect Bits (BP2, BP1, BP0) protect either 4KB Sectors (SEC=1) or 64KB Blocks (SEC=0) in the Top (TB=0) or the Bottom (TB=1) of the array as shown in the Status Register Memory Protection table. The default setting is SEC=0.

7.1.6 Complement Protect (CMP) – Volatile/Non-Volatile Writable

The Complement Protect bit (CMP) is a non-volatile read/write bit in the status register (S14). It is used in conjunction with SEC, TB, BP2, BP1 and BP0 bits to provide more flexibility for the array protection. Once CMP is set to 1, previous array protection set by SEC, TB, BP2, BP1 and BP0 will be reversed. For instance, when CMP=0, a top 64KB block can be protected while the rest of the array is not; when CMP=1, the top 64KB block will become unprotected while the rest of the array become read-only. Please refer to the Status Register Memory Protection table for details. The default setting is CMP=0.

7.1.7 Status Register Protect (SRP1, SRP0) – Volatile/Non-Volatile Writable

The Status Register Protect bits (SRP1 and SRP0) are non-volatile read/write bits in the status register (S8 and S7). The SRP bits control the method of write protection: software protection, hardware protection, power supply lock-down or one time programmable (OTP) protection.

SRP1 SRP0 /WP

Status

Description

0 0 X

0 1 0

0 1 1

1 0 X

1 1 X

Notes:

1. When SRP1, SRP0 = (1, 0), a power-down, power-up cycle will change SRP1, SRP0 to (0, 0) state.

2. This feature is available upon special order. Please contact Winbond for details.

Software

Protection

Hardware Protected

Hardware

Unprotected

Power Supply

Lock-Down

One Time

Program

/WP pin has no control. The Status register can be written to after a Write Enable instruction, WEL=1. [Factory Default]

When /WP pin is low the Status Register locked and cannot be written to.

When /WP pin is high the Status register is unlocked and can be written to after a Write Enable instruction, WEL=1.

Status Register is protected and cannot be written to again until the next power-down, power-up cycle.

Status Register is permanently protected and cannot be

(2)

written to.

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W25Q32FV

Figure 4b. Status Register-2

7.1.8 Erase/Program Suspend Status (SUS) – Status Only

The Suspend Status bit is a read only bit in the status register (S15) that is set to 1 after executing a Erase/Program Suspend (75h) instruction. The SUS status bit is cleared to 0 by Erase/Program Resume (7Ah) instruction as well as a power-down, power-up cycle.

7.1.9 Security Register Lock Bits (LB3, LB2, LB1) – Volatile/Non-Volatile OTP Writable

The Security Register Lock Bits (LB3, LB2, LB1) are non-volatile One Time Program (OTP) bits in Status Register (S13, S12, S11) that provide the write protect control and status to the Security Registers. The default state of LB3-1 is 0, Security Registers are unlocked. LB3-1 can be set to 1 individually using the Write Status Register instruction. LB3-1 are One Time Programmable (OTP), once it’s set to 1, the corresponding 256-Byte Security Register will become read-only permanently.

7.1.10 Quad Enable (QE) – Volatile/Non-Volatile Writable

The Quad Enable (QE) bit is a non-volatile read/write bit in the status register (S9) that allows Quad SPI and QPI operation. When the QE bit is set to a 0 state (factory default for part numbers with ordering options “IG”, “IP” and “IF”), the /WP pin and /HOLD are enabled. When the QE bit is set to a 1(factory default for Quad Enabled part numbers with ordering option “IQ”),, the Quad IO2 and IO3 pins are enabled, and /WP and /HOLD functions are disabled.

QE bit is required to be set to a 1 before issuing an “Enter QPI (38h)” to switch the device from Standard/Dual/Quad SPI to QPI, otherwise the command will be ignored. When the device is in QPI mode, QE bit will remain to be 1. A “Write Status Register” command in QPI mode cannot change QE bit from a “1” to a “0”.

WARNING: If the /WP or /HOLD pins are tied directly to the power supply or ground during standard SPI or Dual SPI operation, the QE bit should never be set to a 1.

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Figure 4c. Status Register-3

7.1.11 Write Protect Selection (WPS) – Volatile/Non-Volatile Writable

The WPS bit is used to select which Write Protect scheme should be used. When WPS=0, the device will use the combination of CMP, SEC, TB, BP[2:0] bits to protect a specific area of the memory array. When WPS=1, the device will utilize the Individual Block Locks to protect any individual sector or blocks. The default value for all Individual Block Lock bits is 1 upon device power on or after reset.

7.1.12 Output Driver Strength (DRV1, DRV0) – Volatile/Non-Volatile Writable

The DRV1 & DRV0 bits are used to determine the output driver strength for the Read operations.

DRV1, DRV0 Driver Strength

0, 0 100% 0, 1 75% 1, 0 50% 1, 1 25% (default)

7.1.13 /HOLD or /RESET Pin Function (HOLD/RST) – Volatile/Non-Volatile Writable

The HOLD/RST bit is used to determine whether /HOLD or /RESET function should be implemented on the hardware pin for 8-pin packages. When HOLD/RST=0 (factory default), the pin acts as /HOLD; when HOLD/RST=1, the pin acts as /RESET. However, /HOLD or /RESET functions are only available when QE=0. If QE is set to 1, the /HOLD and /RESET functions are disabled, the pin acts as a dedicated data I/O pin.

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7.1.14 Reserved Bits – Non Functional

There are a few reserved Status Register bits that may be read out as a “0” or “1”. It is recommended to ignore the values of those bits. During a “Write Status Register” instruction, the Reserved Bits can be written as “0”, but there will not be any effects.

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7.1.15 W25Q32FV Status Register Memory Protection (WPS = 0, CMP = 0)

STATUS REGISTER

SEC TB BP2 BP1 BP0

(1)

W25Q32FV (32M-BIT) MEMORY PROTECTION

PROTECTED

BLOCK(S)

PROTECTED ADDRESSES

PROTECTED

DENSITY

(3)

PROTECTED

PORTION

X X 0 0 0 NONE NONE NONE NONE

0 0 0 0 1 63 3F0000h – 3FFFFFh 0 0 0 1 0 62 and 63 3E0000h – 3FFFFFh 0 0 0 1 1 60 thru 63 3C0000h – 3FFFFFh 0 0 1 0 0 56 thru 63 380000h – 3FFFFFh 0 0 1 0 1 48 thru 63 300000h – 3FFFFFh 0 0 1 1 0 32 thru 63 200000h – 3FFFFFh

0 1 0 0 1 0 000000h – 00FFFFh 0 1 0 1 0 0 and 1 000000h – 01FFFFh 0 1 0 1 1 0 thru 3 000000h – 03FFFFh 0 1 1 0 0 0 thru 7 000000h – 07FFFFh 0 1 1 0 1 0 thru 15 000000h – 0FFFFFh

64KB Upper 1/64 128KB Upper 1/32 256KB Upper 1/16 512KB Upper 1/8

1MB Upper 1/4 2MB Upper 1/2

64KB Lower 1/64 128KB Lower 1/32 256KB Lower 1/16 512KB Lower 1/8

1MB Lower 1/4

(2)

0 1 1 1 0 0 thru 31 000000h – 1FFFFFh

X X 1 1 1 0 thru 63 000000h – 3FFFFFh

1 0 0 0 1 63 3FF000h – 3FFFFFh 1 0 0 1 0 63 3FE000h – 3FFFFFh 1 0 0 1 1 63 3FC000h – 3FFFFFh 1 0 1 0 X 63 3F8000h – 3FFFFFh 1 1 0 0 1 0 000000h – 000FFFh 1 1 0 1 0 0 000000h – 001FFFh 1 1 0 1 1 0 000000h – 003FFFh 1 1 1 0 X 0 000000h – 007FFFh

Notes:

1. X = don’t care

2. L = Lower; U = Upper

3. If any Erase or Program command specifies a memory region that contains protected data portion, this command will be ignored

2MB Lower 1/2 4MB ALL

4KB U - 1/1024

8KB U - 1/512 16KB U - 1/256 32KB U - 1/128

4KB L - 1/1024

8KB L - 1/512 16KB L - 1/256 32KB L - 1/128

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7.1.16 W25Q32FV Status Register Memory Protection (WPS = 0, CMP = 1)

STATUS REGISTER

SEC TB BP2 BP1 BP0

X X 0 0 0 0 thru 63 000000h – 3FFFFFh

0 0 0 0 1 0 thru 62 000000h – 3EFFFFh 0 0 0 1 0 0 and 61 000000h – 3DFFFFh 0 0 0 1 1 0 thru 59 000000h – 3BFFFFh 0 0 1 0 0 0 thru 55 000000h – 37FFFFh 0 0 1 0 1 0 thru 47 000000h – 2FFFFFh 0 0 1 1 0 0 thru 31 000000h – 1FFFFFh

0 1 0 0 1 1 thru 63 010000h – 3FFFFFh 0 1 0 1 0 2 and 63 020000h – 3FFFFFh 0 1 0 1 1 4 thru 63 040000h – 3FFFFFh 0 1 1 0 0 8 thru 63 080000h – 3FFFFFh 0 1 1 0 1 16 thru 63 100000h – 3FFFFFh

(1)

W25Q32FV (32M-BIT) MEMORY PROTECTION

PROTECTED

BLOCK(S)

PROTECTED ADDRESSES

PROTECTED

DENSITY

4MB ALL 4,032KB Lower 63/64 3,968KB Lower 31/32 3,840KB Lower 15/16 3,584KB Lower 7/8

3MB Lower 3/4

2MB Lower 1/2 4,032KB Upper 63/64

3,968KB Upper 31/32 3,840KB Upper 15/16 3,584KB Upper 7/8

3MB Upper 3/4

(3)

PROTECTED

PORTION

(2)

0 1 1 1 0 32 thru 63 200000h – 3FFFFFh

2MB Upper 1/2

X X 1 1 1 NONE NONE NONE NONE

1 0 0 0 1 0 thru 63 000000h – 3FEFFFh 1 0 0 1 0 0 thru 63 000000h – 3FDFFFh 1 0 0 1 1 0 thru 63 000000h – 3FBFFFh 1 0 1 0 X 0 thru 63 000000h – 3F7FFFh 1 1 0 0 1 0 thru 63 001000h – 3FFFFFh 1 1 0 1 0 0 thru 63 002000h – 3FFFFFh 1 1 0 1 1 0 thru 63 004000h – 3FFFFFh 1 1 1 0 X 0 thru 63 008000h – 3FFFFFh

Notes:

4. X = don’t care

5. L = Lower; U = Upper

6. If any Erase or Program command specifies a memory region that contains protected data portion, this command will be ignored

4,092KB L - 1023/1024 4,088KB L - 511/512 4,080KB L - 255/256 4,064KB L - 127/128 4,092KB U - 1023/1024 4,088KB U - 511/512 4,080KB U - 255/256 4,064KB U - 127/128

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7.1.17 W25Q32FV Individual Block Memory Protection (WPS=1)

Figure 4d. Individual Block/Sector Locks

Notes:

1. Individual Block/Sector protection is only valid when WPS=1.

2. All individual block/sector lock bits are set to 1 by default after power up, all memory array is protected.

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8. INSTRUCTIONS

The Standard/Dual/Quad SPI instruction set of the W25Q32FV consists of 45 basic instructions that are fully controlled through the SPI bus (see Instruction Set Table1-2). Instructions are initiated with the falling edge of Chip Select (/CS). The first byte of data clocked into the DI input provides the instruction code. Data on the DI input is sampled on the rising edge of clock with most significant bit (MSB) first.

The QPI instruction set of the W25Q32FV consists of 32 basic instructions that are fully controlled through the SPI bus (see Instruction Set Table 3). Instructions are initiated with the falling edge of Chip Select (/CS). The first byte of data clocked through IO[3:0] pins provides the instruction code. Data on all four IO pins are sampled on the rising edge of clock with most significant bit (MSB) first. All QPI instructions, addresses, data and dummy bytes are using all four IO pins to transfer every byte of data with every two serial clocks (CLK).

Instructions vary in length from a single byte to several bytes and may be followed by address bytes, data bytes, dummy bytes (don’t care), and in some cases, a combination. Instructions are completed with the rising edge of edge /CS. Clock relative timing diagrams for each instruction are included in Figures 5 through 57. All read instructions can be completed after any clocked bit. However, all instructions that Write, Program or Erase must complete on a byte boundary (/CS driven high after a full 8-bits have been clocked) otherwise the instruction will be ignored. This feature further protects the device from inadvertent writes. Additionally, while the memory is being programmed or erased, or when the Status Register is being written, all instructions except for Read Status Register will be ignored until the program or erase cycle has completed.

8.1 Device ID and Instruction Set Tables

8.1.1 Manufacturer and Device Identification

MANUFACTURER ID (MF7 - MF0)

Winbond Serial Flash

Device ID (ID7 - ID0) Instruction ABh, 90h, 92h, 94h

W25Q32FV (SPI Mode) 15h 4016h W25Q32FV (QPI Mode) 15h 6016h

EFh

(ID15 - ID0) 9Fh

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8.1.2 Instruction Set Table 1 (Standard/Dual/Quad SPI Instructions)

Data Input Output Byte 1

Clock Number (0 – 7)

(4)

01h (S7-S0)

Byte 2 Byte 3 Byte 4 Byte 5 Byte 6 Byte 7

(8 – 15) (16 – 23) (24 – 31) (32 – 39) (40 – 47) (48 – 55)

(2)

(4)

(2)

(1)

(2)

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8.1.3 Instruction Set Table 2 (Standard/Dual/Quad SPI Instructions)

Data Input Output Byte 1

Clock Number (0 – 7)

Read Unique ID 4Bh Dummy Dummy Dummy Dummy (UID63-UID0) Page Program 02h A23-A16 A15-A8 A7-A0 D7-D0 D7-D0 Quad Page Program 32h A23-A16 A15-A8 A7-A0 D7-D0, … Sector Erase (4KB) 20h A23-A16 A15-A8 A7-A0 Block Erase (32KB) 52h A23-A16 A15-A8 A7-A0 Block Erase (64KB) D8h A23-A16 A15-A8 A7-A0 Read Data 03h A23-A16 A15-A8 A7-A0 (D7-D0) Fast Read 0Bh A23-A16 A15-A8 A7-A0 Dummy (D7-D0) Fast Read Dual Output 3Bh A23-A16 A15-A8 A7-A0 Dummy (D7-D0, …) Fast Read Quad Output 6Bh A23-A16 A15-A8 A7-A0 Dummy (D7-D0, …) Read SFDP Register 5Ah A23-A16 A15-A8 A7-A0 Dummy (D7-D0) Erase Security Register Program Security Register Read Security Register Individual Block Lock 36h A23-A16 A15-A8 A7-A0 Individual Block Unlock 39h A23-A16 A15-A8 A7-A0 Read Block Lock 3Dh A23-A16 A15-A8 A7-A0 (L7-L0)

Data Input Output Byte 1

Clock Number (0 – 7)

Fast Read Dual I/O BBh A23-A16 A15-A8 A7-A0 Dummy (D7-D0) Mftr./Device ID Dual I/O 92h A23-A16 A15-A8 A7-A0 Dummy (MF7-MF0) (ID7-ID0)

Data Input Output Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Byte 6

Clock Number (0 – 7) (8, 9) (10, 11) (12, 13) (14, 15) (16, 17) (18, 19) (20, 21) (22, 23)

Set Burst with Wrap 77h Dummy Dummy Dummy W8-W0 Fast Read Quad I/O EBh A23-A16 A15-A8 A7-A0 M7-M0 Dummy Dummy (D7-D0) (D7-D0) Word Read Quad I/O Octal Word Read Quad I/O Mftr./Device ID Quad I/O 94h A23-A16 A15-A8 A7-A0 M7-M0 Dummy Dummy (MF7-MF0) (ID7-ID0)

(5)

44h A23-A16 A15-A8 A7-A0

(5)

42h A23-A16 A15-A8 A7-A0 D7-D0 D7-D0

(5)

48h A23-A16 A15-A8 A7-A0 Dummy (D7-D0)

(12)

E7h A23-A16 A15-A8 A7-A0 M7-M0 Dummy (D7-D0) (D7-D0) (D7-D0)

(13)

E3h A23-A16 A15-A8 A7-A0 M7-M0 (D7-D0) (D7-D0) (D7-D0) (D7-D0)

Byte 2 Byte 3 Byte 4 Byte 5 Byte 6

(8 – 15) (16 – 23) (24 – 31) (32 – 39) (40 – 47)

Byte 2 Byte 3 Byte 4 Byte 5 Byte 6

(8 – 11) (12 – 15) (16 – 19) (20 – 23) (24 – 27) (28 – 31)

(1)

Byte 7

(9)

D7-D0, …

Byte 7

Byte 8 Byte 9

(3)

(7)

(9)

(3)

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8.1.4 Instruction Set Table 3 (QPI Instructions)

Data Input Output Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Byte 6

Clock Number (0, 1) (2, 3) (4, 5) (6, 7) (8, 9) (10, 11)

Write Enable 06h Volatile SR Write Enable 50h Write Disable 04h Read Status Register-1 05h (S7-S0) Write Status Register-1 Read Status Register-2 35h (S15-S8) Write Status Register-2 31h (S15-S8) Read Status Register-3 15h (S23-S16) Write Status Register-3 11h (S23-S16) Chip Erase C7h/60h Erase / Program Suspend 75h Erase / Program Resume 7Ah Power-down B9h Set Read Parameters C0h P7-P0 Release Powerdown / ID ABh Dummy Dummy Dummy (ID7-ID0) Manufacturer/Device ID 90h Dummy Dummy 00h (MF7-MF0) (ID7-ID0) JEDEC ID 9Fh (MF7-MF0) (ID15-ID8) (ID7-ID0) Global Block Lock 7Eh Global Block Unlock 98h Exit QPI Mode FFh Enable Reset 66h Reset Device 99h Page Program 02h A23-A16 A15-A8 A7-A0 D7-D0 Sector Erase (4KB) 20h A23-A16 A15-A8 A7-A0 Block Erase (32KB) 52h A23-A16 A15-A8 A7-A0 Block Erase (64KB) D8h A23-A16 A15-A8 A7-A0 Fast Read 0Bh A23-A16 A15-A8 A7-A0 Dummy Burst Read with Wrap Fast Read Quad I/O EBh A23-A16 A15-A8 A7-A0 M7-M0 Individual Block Lock 36h A23-A16 A15-A8 A7-A0 Individual Block Unlock 39h A23-A16 A15-A8 A7-A0 Read Block Lock 3Dh A23-A16 A15-A8 A7-A0 (L7-L0)

(4)

01h (S7-S0)

(16)

0Ch A23-A16 A15-A8 A7-A0 Dummy

(2)

(4)

(2)

(14)

(2)

(9)

D7-D0

(15)

(D7-D0)

(15)

(D7-D0)

(15)

(D7-D0)

(3)

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W25Q32FV

Notes:

1. Data bytes are shifted with Most Significant Bit first. Byte fields with data in parenthesis “( )” indicate data output from the device on either 1, 2 or 4 IO pins.

2. The Status Register contents and Device ID will repeat continuously until /CS terminates the instruction.

3. At least one byte of data input is required for Page Program, Quad Page Program and Program Security Registers, up to 256 bytes of data input. If more than 256 bytes of data are sent to the device, the addressing will wrap to the beginning of the page and overwrite previously sent data.

4. Write Status Register-1 (01h) can also be used to program Status Register-1&2, see section 8.2.5.

5. Security Register Address: Security Register 1: A23-16 = 00h; A15-8 = 10h; A7-0 = byte address Security Register 2: A23-16 = 00h; A15-8 = 20h; A7-0 = byte address Security Register 3: A23-16 = 00h; A15-8 = 30h; A7-0 = byte address

6. Dual SPI address input format: IO0 = A22, A20, A18, A16, A14, A12, A10, A8 A6, A4, A2, A0, M6, M4, M2, M0 IO1 = A23, A21, A19, A17, A15, A13, A11, A9 A7, A5, A3, A1, M7, M5, M3, M1

7. Dual SPI data output format: IO0 = (D6, D4, D2, D0) IO1 = (D7, D5, D3, D1)

8. Quad SPI address input format: Set Burst with Wrap input format: IO0 = A20, A16, A12, A8, A4, A0, M4, M0 IO0 = x, x, x, x, x, x, W4, x IO1 = A21, A17, A13, A9, A5, A1, M5, M1 IO1 = x, x, x, x, x, x, W5, x IO2 = A22, A18, A14, A10, A6, A2, M6, M2 IO2 = x, x, x, x, x, x, W6, x IO3 = A23, A19, A15, A11, A7, A3, M7, M3 IO3 = x, x, x, x, x, x, x, x

9. Quad SPI data input/output format: IO0 = (D4, D0, …..) IO1 = (D5, D1, …..) IO2 = (D6, D2, …..) IO3 = (D7, D3, …..)

10. Fast Read Quad I/O data output format: IO0 = (x, x, x, x, D4, D0, D4, D0) IO1 = (x, x, x, x, D5, D1, D5, D1) IO2 = (x, x, x, x, D6, D2, D6, D2) IO3 = (x, x, x, x, D7, D3, D7, D3)

11. Word Read Quad I/O data output format: IO0 = (x, x, D4, D0, D4, D0, D4, D0) IO1 = (x, x, D5, D1, D5, D1, D5, D1) IO2 = (x, x, D6, D2, D6, D2, D6, D2) IO3 = (x, x, D7, D3, D7, D3, D7, D3)

12. For Word Read Quad I/O, the lowest address bit must be 0. (A0 = 0)

13. For Octal Word Read Quad I/O, the lowest four address bits must be 0. (A3, A2, A1, A0 = 0)

14. QPI Command, Address, Data input/output format: CLK # 0 1 2 3 4 5 6 7 8 9 10 11 IO0 = C4, C0, A20, A16, A12, A8, A4, A0, D4, D0, D4, D0 IO1 = C5, C1, A21, A17, A13, A9, A5, A1, D5, D1, D5, D1 IO2 = C6, C2, A22, A18, A14, A10, A6, A2, D6, D2, D6, D2 IO3 = C7, C3, A23, A19, A15, A11, A7, A3, D7, D3, D7, D3

15. The number of dummy clocks for QPI Fast Read, QPI Fast Read Quad I/O & QPI Burst Read with Wrap is controlled by read parameter P7 – P4.

16. The wrap around length for QPI Burst Read with Wrap is controlled by read parameter P3 – P0.

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8.2 Instruction Descriptions

8.2.1 Write Enable (06h)

The Write Enable instruction (Figure 5) sets the Write Enable Latch (WEL) bit in the Status Register to a

1. The WEL bit must be set prior to every Page Program, Quad Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register and Erase/Program Security Registers instruction. The Write Enable instruction is entered by driving /CS low, shifting the instruction code “06h” into the Data Input (DI) pin on the rising edge of CLK, and then driving /CS high.

/CS

Mode 3 0 1 2 3 4 5 6 7

CLK

(IO0)

Mode 0

Instruction (06h)

/CS

Mode 3 Mode 0

CLK

Mode 3 0 1 Mode 0

Instruction

06h

Mode 3 Mode 0

(IO1)

High Impedance

Figure 5. Write Enable Instruction for SPI Mode (left) or QPI Mode (right)

8.2.2 Write Enable for Volatile Status Register (50h)

The non-volatile Status Register bits described in section 7.1 can also be written to as volatile bits. This gives more flexibility to change the system configuration and memory protection schemes quickly without waiting for the typical non-volatile bit write cycles or affecting the endurance of the Status Register nonvolatile bits. To write the volatile values into the Status Register bits, the Write Enable for Volatile Status Register (50h) instruction must be issued prior to a Write Status Register (01h) instruction. Write Enable for Volatile Status Register instruction (Figure 6) will not set the Write Enable Latch (WEL) bit, it is only valid for the Write Status Register instruction to change the volatile Status Register bit values.

/CS

CLK

(IO0)

(IO1)

Mode 3 0 1

CLK

Mode 3 0 1 2 3 4 5 6 7 Mode 0

Instruction (50h)

High Impedance

Mode 3 Mode 0

Mode 0

Instruction

50h

Figure 6. Write Enable for Volatile Status Register Instruction for SPI Mode (left) or QPI Mode (right)

Mode 3 Mode 0

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8.2.3 Write Disable (04h)

The Write Disable instruction (Figure 7) resets the Write Enable Latch (WEL) bit in the Status Register to a 0. The Write Disable instruction is entered by driving /CS low, shifting the instruction code “04h” into the DI pin and then driving /CS high. Note that the WEL bit is automatically reset after Power-up and upon completion of the Write Status Register, Erase/Program Security Registers, Page Program, Quad Page Program, Sector Erase, Block Erase, Chip Erase and Reset instructions.

/CS

CLK

(IO0)

(IO1)

Mode 3 0 1 2 3 4 5 6 7 Mode 0

Instruction (04h)

High Impedance

Mode 3 Mode 0

Mode 3 0 1

CLK

Mode 0

Instruction

04h

Mode 3 Mode 0

Figure 7. Write Disable Instruction for SPI Mode (left) or QPI Mode (right)

8.2.4 Read Status Register-1 (05h), Status Register-2 (35h) & Status Register-3 (15h)

The Read Status Register instructions allow the 8-bit Status Registers to be read. The instruction is entered by driving /CS low and shifting the instruction code “05h” for Status Register-1, “35h” for Status Register-2 or “15h” for Status Register-3 into the DI pin on the rising edge of CLK. The status register bits are then shifted out on the DO pin at the falling edge of CLK with most significant bit (MSB) first as shown in Figure 8. Refer to section 7.1 for Status Register descriptions.

The Read Status Register instruction may be used at any time, even while a Program, Erase or Write Status Register cycle is in progress. This allows the BUSY status bit to be checked to determine when the cycle is complete and if the device can accept another instruction. The Status Register can be read continuously, as shown in Figure 8. The instruction is completed by driving /CS high.

Figure 8a. Read Status Register Instruction (SPI Mode)

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Figure 8b. Read Status Register Instruction (QPI Mode)

8.2.5 Write Status Register-1 (01h), Status Register-2 (31h) & Status Register-3 (11h)

The Write Status Register instruction allows the Status Registers to be written. The writable Status Register bits include: SRP0, SEC, TB, BP[2:0] in Status Register-1; CMP, LB[3:1], QE, SRP1 in Status Register-2; HOLD/RST, DRV1, DRV0, WPS & ADP in Status Register-3. All other Status Register bit locations are read-only and will not be affected by the Write Status Register instruction. LB[3:1] are nonvolatile OTP bits, once it is set to 1, it cannot be cleared to 0.

To write non-volatile Status Register bits, a standard Write Enable (06h) instruction must previously have been executed for the device to accept the Write Status Register instruction (Status Register bit WEL must equal 1). Once write enabled, the instruction is entered by driving /CS low, sending the instruction code “01h/31h/11h”, and then writing the status register data byte as illustrated in Figure 9a & 9b.

To write volatile Status Register bits, a Write Enable for Volatile Status Register (50h) instruction must have been executed prior to the Write Status Register instruction (Status Register bit WEL remains 0). However, SRP1 and LB[3:1] cannot be changed from “1” to “0” because of the OTP protection for these bits. Upon power off or the execution of a Software/Hardware Reset, the volatile Status Register bit values will be lost, and the non-volatile Status Register bit values will be restored.

During non-volatile Status Register write operation (06h combined with 01h/31h/11h), after /CS is driven high, the self-timed Write Status Register cycle will commence for a time duration of tW (See AC Characteristics). While the Write Status Register cycle is in progress, the Read Status Register instruction may still be accessed to check the status of the BUSY bit. The BUSY bit is a 1 during the Write Status Register cycle and a 0 when the cycle is finished and ready to accept other instructions again. After the Write Status Register cycle has finished, the Write Enable Latch (WEL) bit in the Status Register will be cleared to 0.

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During volatile Status Register write operation (50h combined with 01h/31h/11h), after /CS is driven high, the Status Register bits will be refreshed to the new values within the time period of t

SHSL2

(See AC

Characteristics). BUSY bit will remain 0 during the Status Register bit refresh period. The Write Status Register instruction can be used in both SPI mode and QPI mode. However, the QE bit

cannot be written to when the device is in the QPI mode, because QE=1 is required for the device to enter and operate in the QPI mode.

Refer to section 7.1 for Status Register descriptions.

Figure 9a. Write Status Register-1/2/3 Instruction (SPI Mode)

Figure 9b. Write Status Register-1/2/3 Instruction (QPI Mode)

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The W25Q32FV is also backward compatible to Winbond’s previous generations of serial flash memories, in which the Status Register-1&2 can be written using a single “Write Status Register-1 (01h)” command. To complete the Write Status Register-1&2 instruction, the /CS pin must be driven high after the sixteenth bit of data that is clocked in as shown in Figure 9c & 9d. If /CS is driven high after the eighth clock, the Write Status Register-1 (01h) instruction will only program the Status Register-1, the Status Register-2 not be affected (Previous generations will clear CMP and QE bits).

/CS

Mode 3 0 1 2 3 4 5 6 7

CLK

Mode 0

Instruction (01h)

(IO0)

(IO1)

= MSB

Figure 9c. Write Status Register-1/2 Instruction (SPI Mode)

/CS

Mode 3 0 1

CLK

Mode 0

8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

Status Register 1 in Status Register 2 in

7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8

* *

High Impedance

Instruction

01h

2 3 4 5

SR1 in SR2 in

4 0 12 8

Mode 3 Mode 0

5 1

6 2

7 3

13 9

14 10

15 11

Figure 9d. Write Status Register-1/2 Instruction (QPI Mode)

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8.2.6 Read Data (03h)

The Read Data instruction allows one or more data bytes to be sequentially read from the memory. The instruction is initiated by driving the /CS pin low and then shifting the instruction code “03h” followed by a 24-bit address (A23-A0) into the DI pin. The code and address bits are latched on the rising edge of the CLK pin. After the address is received, the data byte of the addressed memory location will be shifted out on the DO pin at the falling edge of CLK with most significant bit (MSB) first. The address is automatically incremented to the next higher address after each byte of data is shifted out allowing for a continuous stream of data. This means that the entire memory can be accessed with a single instruction as long as the clock continues. The instruction is completed by driving /CS high.

The Read Data instruction sequence is shown in Figure 14. If a Read Data instruction is issued while an Erase, Program or Write cycle is in process (BUSY=1) the instruction is ignored and will not have any effects on the current cycle. The Read Data instruction allows clock rates from D.C. to a maximum of fR (see AC Electrical Characteristics).

The Read Data (03h) instruction is only supported in Standard SPI mode.

/CS

Mode 3 0 1 2 3 4 5 6 7

CLK

Mode 0

Instruction (03h)

(IO0)

(IO1)

= MSB

High Impedance

8 9 10 28 29 30 31 32 33 34 35 36 37 38 39

24-Bit Address

23 22 21 3 2 1 0

Data Out 1

7 6 5 4 3 2 1 0 7

Figure 14. Read Data Instruction (SPI Mode only)

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8.2.7 Fast Read (0Bh)

The Fast Read instruction is similar to the Read Data instruction except that it can operate at the highest possible frequency of FR (see AC Electrical Characteristics). This is accomplished by adding eight “dummy” clocks after the 24-bit address as shown in Figure 16. The dummy clocks allow the devices internal circuits additional time for setting up the initial address. During the dummy clocks the data value on the DO pin is a “don’t care”.

/CS

Mode 3 0 1 2 3 4 5 6 7

CLK

Mode 0

Instruction (0Bh)

(IO0)

8 9 10 28 29 30 31

24-Bit Address

23 22 21 3 2 1 0

(IO1)

/CS

CLK

(IO0)

(IO1)

= MSB

32 33 34 35 36 37 38 39

Dummy Clocks

High Impedance

40 41 42 44 45 46 47 48 49 50 51 52 53 54 55

7 6 5 4 3 2 1 0

4331

Data Out 1

Data Out 2

7 6 5 4 3 2 1 0 7

Figure 16a. Fast Read Instruction (SPI Mode)

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Fast Read (0Bh) in QPI Mode

The Fast Read instruction is also supported in QPI mode. When QPI mode is enabled, the number of dummy clocks is configured by the “Set Read Parameters (C0h)” instruction to accommodate a wide range of applications with different needs for either maximum Fast Read frequency or minimum data access latency. Depending on the Read Parameter Bits P[5:4] setting, the number of dummy clocks can be configured as either 2, 4, 6 or 8. The default number of dummy clocks upon power up or after a Reset instruction is 2.

/CS

CLK

Mode 3 0 1 Mode 0

Instruction

0Bh

2 3 4 5

A23-16

20 16 12 8

21 17

22 18

A15-8 A7-0

13 9

14 10

6 7 8 9

Dummy*

4 0

5 1

6 2

4 0

5 1

6 2

10 11 12 13

IOs switch from Input to Output

4 0

5 1

6 2

4 0

5 1

6 2

23 19

15 11

7 3

Byte 1 Byte 2

7 3

* "Set Read Parameters" instruction (C0h) can set

the number of dummy clocks.

Figure 16b. Fast Read Instruction (QPI Mode)

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8.2.8 Fast Read Dual Output (3Bh)

The Fast Read Dual Output (3Bh) instruction is similar to the standard Fast Read (0Bh) instruction except that data is output on two pins; IO0 and IO1. This allows data to be transferred at twice the rate of standard SPI devices. The Fast Read Dual Output instruction is ideal for quickly downloading code from Flash to RAM upon power-up or for applications that cache code-segments to RAM for execution.

Similar to the Fast Read instruction, the Fast Read Dual Output instruction can operate at the highest possible frequency of FR (see AC Electrical Characteristics). This is accomplished by adding eight “dummy” clocks after the 24-bit address as shown in Figure 18. The dummy clocks allow the device's internal circuits additional time for setting up the initial address. The input data during the dummy clocks is “don’t care”. However, the IO0 pin should be high-impedance prior to the falling edge of the first data out clock.

/CS

CLK

(IO0)

Mode 3 0 1 2 3 4 5 6 7 Mode 0

Instruction (3Bh)

8 9 10 28 29 30

24-Bit Address

23 22 21 3 2 1 0

(IO1)

/CS

CLK

(IO0)

= MSB

32 33 34 35 36 37 38 39

Dummy Clocks

High Impedance

40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55

6 4 2 0

IO0 switches from Input to Output

6 4 2 0

(IO1)

High Impedance

Figure 18. Fast Read Dual Output Instruction (SPI Mode only)

7 5 3 1

Data Out 1

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7 5 3 1

Data Out 2

7 5 3 1

Data Out 3

7 5 3 1

Data Out 4

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8.2.9 Fast Read Quad Output (6Bh)

The Fast Read Quad Output (6Bh) instruction is similar to the Fast Read Dual Output (3Bh) instruction except that data is output on four pins, IO0, IO1, IO2, and IO3. The Quad Enable (QE) bit in Status Register-2 must be set to 1 before the device will accept the Fast Read Quad Output Instruction. The Fast Read Quad Output Instruction allows data to be transferred at four times the rate of standard SPI devices. The Fast Read Quad Output instruction can operate at the highest possible frequency of FR (see AC Electrical Characteristics). This is accomplished by adding eight “dummy” clocks after the 24-bit address as shown in Figure 20. The dummy clocks allow the device's internal circuits additional time for setting up the initial address. The input data during the dummy clocks is “don’t care”. However, the IO pins should be high-impedance prior to the falling edge of the first data out clock.

/CS

CLK

/CS

CLK

Mode 3 0 1 2 3 4 5 6 7 Mode 0

Instruction (6Bh)

High Impedance

= MSB

32 33 34 35 36 37 38 39

Dummy Clocks

High Impedance

8 9 10 28 29 30

24-Bit Address

23 22 21 3 2 1 0

40 41 42 43 44 45 46 47

IO0 switches from Input to Output

4 0

5 1

6 2

7 3

Byte 1

4 0

5 1

6 2

7 3

4 0

5 1

6 2

7 3

4 0

5 1

6 2

7 3

Byte 2 Byte 3 Byte 4

Figure 20. Fast Read Quad Output Instruction (SPI Mode only)

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8.2.10 Fast Read Dual I/O (BBh)

The Fast Read Dual I/O (BBh) instruction allows for improved random access while maintaining two IO pins, IO0 and IO1. It is similar to the Fast Read Dual Output (3Bh) instruction but with the capability to input the Address bits (A23-0) two bits per clock. This reduced instruction overhead may allow for code execution (XIP) directly from the Dual SPI in some applications.

Fast Read Dual I/O with “Continuous Read Mode”

The Fast Read Dual I/O instruction can further reduce instruction overhead through setting the “Continuous Read Mode” bits (M7-0) after the input Address bits (A23-0), as shown in Figure 22a. The upper nibble of the (M7-4) controls the length of the next Fast Read Dual I/O instruction through the inclusion or exclusion of the first byte instruction code. The lower nibble bits of the (M3-0) are don’t care (“x”). However, the IO pins should be high-impedance prior to the falling edge of the first data out clock.

If the “Continuous Read Mode” bits M5-4 = (1,0), then the next Fast Read Dual I/O instruction (after /CS is raised and then lowered) does not require the BBh instruction code, as shown in Figure 22b. This reduces the instruction sequence by eight clocks and allows the Read address to be immediately entered after /CS is asserted low. If the “Continuous Read Mode” bits M5-4 do not equal to (1,0), the next instruction (after /CS is raised and then lowered) requires the first byte instruction code, thus returning to normal operation. It is recommended to input FFFFh on IO0 for the next instruction (16 clocks), to ensure M4 = 1 and return the device to normal operation.

/CS

Mode 3 0 1 2 3 4 5 6 7

CLK

Mode 0

Instruction (BBh)

(IO0)

8 9 10 12 13 14

A23-16 A15-8 A7-0 M7-0

22 20 18 16

11 15 16 17 18 20 21 2219 23

14 12 10 8

6 4 2 0

(IO1)

/CS

CLK

(IO0)

(IO1)

= MSB

24 25 26 27 28 29 30 31

IOs switch from Input to Output

6 4 2 0

7 5 3 1

Byte 1 Byte 2 Byte 3 Byte 4

6 4 2 0

7 5 3 1

* *

23 21 19 17

32 33 34 35 36 37 38 39

6 4 2 0

7 5 3 1

15 13 11 9

6 4 2 0

7 5 3 1

Figure 22a. Fast Read Dual I/O Instruction (Initial instruction or previous M5-4 ≠ 10, SPI Mode only)

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/CS

CLK

(IO0)

(IO1)

/CS

CLK

(IO0)

(IO1)

Mode 3 8 9 10 12 13 14 Mode 0

0 1 2 3 4 5 6 7

A23-16 A15-8 A7-0 M7-0

22 20 18 16

23 21 19 17

= MSB

16 17 18 20 21 2219 23

IOs switch from Input to Output

6 4 2 0

7 5 3 1

Byte 1 Byte 2 Byte 3 Byte 4

14 12 10 8

15 13 11 9

6 4 2 0

7 5 3 1

* *

6 4 2 0

7 5 3 1

24 25 26 27 28 29 30 31

6 4 2 0

7 5 3 1

11 15

6 4 2 0

7 5 3 1

6 4 2 0

7 5 3 1

Figure 22b. Fast Read Dual I/O Instruction (Previous instruction set M5-4 = 10, SPI Mode only)

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8.2.11 Fast Read Quad I/O (EBh)

The Fast Read Quad I/O (EBh) instruction is similar to the Fast Read Dual I/O (BBh) instruction except that address and data bits are input and output through four pins IO0, IO1, IO2 and IO3 and four Dummy clocks are required in SPI mode prior to the data output. The Quad I/O dramatically reduces instruction overhead allowing faster random access for code execution (XIP) directly from the Quad SPI. The Quad Enable bit (QE) of Status Register-2 must be set to enable the Fast Read Quad I/O Instruction.

Fast Read Quad I/O with “Continuous Read Mode”

The Fast Read Quad I/O instruction can further reduce instruction overhead through setting the “Continuous Read Mode” bits (M7-0) after the input Address bits (A23-0), as shown in Figure 24a. The upper nibble of the (M7-4) controls the length of the next Fast Read Quad I/O instruction through the inclusion or exclusion of the first byte instruction code. The lower nibble bits of the (M3-0) are don’t care (“x”). However, the IO pins should be high-impedance prior to the falling edge of the first data out clock.

If the “Continuous Read Mode” bits M5-4 = (1,0), then the next Fast Read Quad I/O instruction (after /CS is raised and then lowered) does not require the EBh instruction code, as shown in Figure 24b. This reduces the instruction sequence by eight clocks and allows the Read address to be immediately entered after /CS is asserted low. If the “Continuous Read Mode” bits M5-4 do not equal to (1,0), the next instruction (after /CS is raised and then lowered) requires the first byte instruction code, thus returning to normal operation. It is recommended to input FFh on IO0 for the next instruction (8 clocks), to ensure M4 = 1 and return the device to normal operation.

/CS

CLK

Mode 3 0 1 Mode 0

2 3 4 5

Instruction (EBh)

6 7 8 9

A23-16

20 16 12 8

21 17

22 18

23 19

10 11 12 13 14

A15-8 A7-0

4 0

13 9

14 10

15 11

5 1

6 2

7 3

15 16 17 18 19 20 21 22 23

M7-0

Dummy Dummy

4 0

5 1

6 2

7 3

Figure 24a. Fast Read Quad I/O Instruction (Initial instruction or previous M5-4≠10, SPI Mode)

IOs switch from Input to Output

4 0

5 1

6 2

7 3

Byte 1 Byte 2

Byte 3

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/CS

CLK

Mode 3 0 1 Mode 0

A23-16

20 16 12 8

2 3 4 5

A15-8 A7-0

4 0

6 7 8 9

M7-0

4 0

Dummy Dummy

10 11 12 13 14

IOs switch from Input to Output

4 0

21 17

22 18

23 19

13 9

14 10

15 11

5 1

6 2

7 3

5 1

6 2

7 3

5 1

6 2

7 3

Byte 1 Byte 2

5 1

6 2

7 3

Byte 3

Figure 24b. Fast Read Quad I/O Instruction (Previous instruction set M5-4 = 10, SPI Mode)

Fast Read Quad I/O with “8/16/32/64-Byte Wrap Around” in Standard SPI mode

The Fast Read Quad I/O instruction can also be used to access a specific portion within a page by issuing a “Set Burst with Wrap” (77h) command prior to EBh. The “Set Burst with Wrap” (77h) command can either enable or disable the “Wrap Around” feature for the following EBh commands. When “Wrap Around” is enabled, the data being accessed can be limited to either an 8, 16, 32 or 64-byte section of a 256-byte page. The output data starts at the initial address specified in the instruction, once it reaches the ending boundary of the 8/16/32/64-byte section, the output will wrap around to the beginning boundary automatically until /CS is pulled high to terminate the command.

The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and then fill the cache afterwards within a fixed length (8/16/32/64-byte) of data without issuing multiple read commands.

The “Set Burst with Wrap” instruction allows three “Wrap Bits”, W6-4 to be set. The W4 bit is used to enable or disable the “Wrap Around” operation while W6-5 are used to specify the length of the wrap around section within a page. Refer to section 8.2.24 for detail descriptions.

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Fast Read Quad I/O (EBh) in QPI Mode

The Fast Read Quad I/O instruction is also supported in QPI mode, as shown in Figure 19c. When QPI mode is enabled, the number of dummy clocks is configured by the “Set Read Parameters (C0h)” instruction to accommodate a wide range of applications with different needs for either maximum Fast Read frequency or minimum data access latency. Depending on the Read Parameter Bits P[5:4] setting, the number of dummy clocks can be configured as either 2, 4, 6 or 8. The default number of dummy clocks upon power up or after a Reset instruction is 2. In QPI mode, the “Continuous Read Mode” bits M7-0 are also considered as dummy clocks. In the default setting, the data output will follow the Continuous Read Mode bits immediately.

“Continuous Read Mode” feature is also available in QPI mode for Fast Read Quad I/O instruction. Please refer to the description on previous pages.

“Wrap Around” feature is not available in QPI mode for Fast Read Quad I/O instruction. To perform a read operation with fixed data length wrap around in QPI mode, a dedicated “Burst Read with Wrap” (0Ch) instruction must be used. Please refer to 8.2.45 for details.

/CS

CLK

Mode 3 0 1 Mode 0

Instruction

EBh

2 3 4 5

A23-16

20 16 12 8

A15-8 A7-0

6 7 8 9

M7-0

4 0

10 11 12 13 14

4 0

IOs switch from Input to Output

4 0

"Set Read Parameters" instruction (C0h) can

set the number of dummy clocks.

21 17

22 18

23 19

13 9

14 10

15 11

5 1

6 2

7 3

5 1

6 2

7 3

5 1

6 2

7 3

Byte 1 Byte 2

5 1

6 2

7 3

Figure 24c. Fast Read Quad I/O Instruction (Initial instruction or previous M5-4≠10, QPI Mode)

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8.2.12 Word Read Quad I/O (E7h)

The Word Read Quad I/O (E7h) instruction is similar to the Fast Read Quad I/O (EBh) instruction except that the lowest Address bit (A0) must equal 0 and only two Dummy clocks are required prior to the data output. The Quad I/O dramatically reduces instruction overhead allowing faster random access for code execution (XIP) directly from the Quad SPI. The Quad Enable bit (QE) of Status Register-2 must be set to enable the Word Read Quad I/O Instruction.

Word Read Quad I/O with “Continuous Read Mode”

The Word Read Quad I/O instruction can further reduce instruction overhead through setting the “Continuous Read Mode” bits (M7-0) after the input Address bits (A23-0), as shown in Figure 26a. The upper nibble of the (M7-4) controls the length of the next Fast Read Quad I/O instruction through the inclusion or exclusion of the first byte instruction code. The lower nibble bits of the (M3-0) are don’t care (“x”). However, the IO pins should be high-impedance prior to the falling edge of the first data out clock.

If the “Continuous Read Mode” bits M5-4 = (1,0), then the next Fast Read Quad I/O instruction (after /CS is raised and then lowered) does not require the E7h instruction code, as shown in Figure 26b. This reduces the instruction sequence by eight clocks and allows the Read address to be immediately entered after /CS is asserted low. If the “Continuous Read Mode” bits M5-4 do not equal to (1,0), the next instruction (after /CS is raised and then lowered) requires the first byte instruction code, thus returning to normal operation. It is recommended to input FFh on IO0 for the next instruction (8 clocks), to ensure M4 = 1 and return the device to normal operation.

/CS

CLK

Mode 3 0 1 Mode 0

2 3 4 5

Instruction (E7h)

6 7 8 9

A23-16

20 16 12 8

21 17

22 18

23 19

10 11 12 13 14

A15-8 A7-0

4 0

13 9

14 10

15 11

5 1

6 2

7 3

15 16 17 18 19 20 21

M7-0

Dummy

4 0

5 1

6 2

7 3

4 0

5 1

6 2

7 3

Byte 1 Byte 2

Figure 26a. Word Read Quad I/O Instruction (Initial instruction or previous M5-4 ≠ 10, SPI Mode only)

IOs switch from Input to Output

4 0

5 1

6 2

7 3

Byte 3

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/CS

Mode 3 0 1

CLK

Mode 0

2 3 4 5

A23-16

20 16 12 8

21 17

22 18

23 19

A15-8 A7-0

13 9

14 10

15 11

4 0

5 1

6 2

7 3

6 7

M7-0

4 0

5 1

6 2

7 3

8 9 10 11 12 13

Dummy

4 0

5 1

6 2

7 3

Byte 1 Byte 2

IOs switch from Input to Output

4 0

5 1

6 2

7 3

Byte 3

Figure 26b. Word Read Quad I/O Instruction (Previous instruction set M5-4 = 10, SPI Mode only)

Word Read Quad I/O with “8/16/32/64-Byte Wrap Around” in Standard SPI mode

The Word Read Quad I/O instruction can also be used to access a specific portion within a page by issuing a “Set Burst with Wrap” (77h) command prior to E7h. The “Set Burst with Wrap” (77h) command can either enable or disable the “Wrap Around” feature for the following E7h commands. When “Wrap Around” is enabled, the data being accessed can be limited to either an 8, 16, 32 or 64-byte section of a 256-byte page. The output data starts at the initial address specified in the instruction, once it reaches the ending boundary of the 8/16/32/64-byte section, the output will wrap around to the beginning boundary automatically until /CS is pulled high to terminate the command.

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8.2.13 Octal Word Read Quad I/O (E3h)

The Octal Word Read Quad I/O (E3h) instruction is similar to the Fast Read Quad I/O (EBh) instruction except that the lower four Address bits (A0, A1, A2, A3) must equal 0. As a result, the dummy clocks are not required, which further reduces the instruction overhead allowing even faster random access for code execution (XIP). The Quad Enable bit (QE) of Status Register-2 must be set to enable the Octal Word Read Quad I/O Instruction.

Octal Word Read Quad I/O with “Continuous Read Mode”

The Octal Word Read Quad I/O instruction can further reduce instruction overhead through setting the “Continuous Read Mode” bits (M7-0) after the input Address bits (A23-0), as shown in Figure 27a. The upper nibble of the (M7-4) controls the length of the next Octal Word Read Quad I/O instruction through the inclusion or exclusion of the first byte instruction code. The lower nibble bits of the (M3-0) are don’t care (“x”). However, the IO pins should be high-impedance prior to the falling edge of the first data out clock.

If the “Continuous Read Mode” bits M5-4 = (1,0), then the next Fast Read Quad I/O instruction (after /CS is raised and then lowered) does not require the E3h instruction code, as shown in Figure 27b. This reduces the instruction sequence by eight clocks and allows the Read address to be immediately entered after /CS is asserted low. If the “Continuous Read Mode” bits M5-4 do not equal to (1,0), the next instruction (after /CS is raised and then lowered) requires the first byte instruction code, thus returning to normal operation. It is recommended to input FFh on IO0 for the next instruction (8 clocks), to ensure M4 = 1 and return the device to normal operation.

/CS

CLK

Mode 3 0 1 Mode 0

2 3 4 5

Instruction (E3h)

6 7 8 9

A23-16

20 16 12 8

21 17

22 18

23 19

10 11 12 13 14

A15-8 A7-0

4 0

13 9

14 10

15 11

5 1

6 2

7 3

15 16 17 18 19 20 21

M7-0

4 0

5 1

6 2

7 3

IOs switch from Input to Output

4 0

5 1

6 2

7 3

Byte 1 Byte 2

4 0

5 1

6 2

7 3

4 0

5 1

6 2

7 3

Byte 3

Byte 4

Figure 27a. Octal Word Read Quad I/O Instruction (Initial instruction or previous M5-4 ≠ 10, SPI Mode only)

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/CS

CLK

Mode 3 0 1 Mode 0

A23-16

20 16 12 8

21 17

22 18

23 19

2 3 4 5

A15-8 A7-0

4 0

13 9

14 10

15 11

5 1

6 2

7 3

6 7

M7-0

4 0

5 1

6 2

7 3

8 9 10 11 12 13

IOs switch from Input to Output

4 0

5 1

6 2

7 3

Byte 1 Byte 2

4 0

5 1

6 2

7 3

4 0

5 1

6 2

7 3

Byte 3

Byte 4

Figure 27b. Octal Word Read Quad I/O Instruction (Previous instruction set M5-4 = 10, SPI Mode only)

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0 1

8.2.14 Set Burst with Wrap (77h)

In Standard SPI mode, the Set Burst with Wrap (77h) instruction is used in conjunction with “Fast Read Quad I/O” and “Word Read Quad I/O” instructions to access a fixed length of 8/16/32/64-byte section within a 256-byte page. Certain applications can benefit from this feature and improve the overall system code execution performance.

Similar to a Quad I/O instruction, the Set Burst with Wrap instruction is initiated by driving the /CS pin low and then shifting the instruction code “77h” followed by 24 dummy bits and 8 “Wrap Bits”, W7-0. The instruction sequence is shown in Figure 28. Wrap bit W7 and the lower nibble W3-0 are not used.

W6, W5

0 0

Wrap Around Wrap Length Wrap Around Wrap Length

Yes 8-byte No N/A Yes 16-byte No N/A

1 0 Yes 32-byte No N/A 1 1 Yes 64-byte No N/A

W4 = 0 W4 =1 (DEFAULT)

Once W6-4 is set by a Set Burst with Wrap instruction, all the following “Fast Read Quad I/O” and “Word Read Quad I/O” instructions will use the W6-4 setting to access the 8/16/32/64-byte section within any page. To exit the “Wrap Around” function and return to normal read operation, another Set Burst with Wrap instruction should be issued to set W4 = 1. The default value of W4 upon power on or after a software/hardware reset is 1.

In QPI mode, the “Burst Read with Wrap (0Ch)” instruction should be used to perform the Read operation with “Wrap Around” feature. The Wrap Length set by W5-4 in Standard SPI mode is still valid in QPI mode and can also be re-configured by “Set Read Parameters (C0h)” instruction. Refer to 8.2.44 and 8.2.45 for details.

/CS

Mode 3 0 1

CLK

Mode 0

2 3 4 5

Instruction (77h)

Figure 28. Set Burst with Wrap Instruction (SPI Mode only)

6 7 8 9

don't

care

X X

10 11 12 13 14 15

don't

care

X X

don't

care

X X

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Mode 3 Mode 0

Wrap Bit

w4 X

w5 X

w6 X

X X

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8.2.15 Page Program (02h)

The Page Program instruction allows from one byte to 256 bytes (a page) of data to be programmed at previously erased (FFh) memory locations. A Write Enable instruction must be executed before the device will accept the Page Program Instruction (Status Register bit WEL= 1). The instruction is initiated by driving the /CS pin low then shifting the instruction code “02h” followed by a 24-bit address (A23-A0) and at least one data byte, into the DI pin. The /CS pin must be held low for the entire length of the instruction while data is being sent to the device. The Page Program instruction sequence is shown in Figure 29.

If an entire 256 byte page is to be programmed, the last address byte (the 8 least significant address bits) should be set to 0. If the last address byte is not zero, and the number of clocks exceeds the remaining page length, the addressing will wrap to the beginning of the page. In some cases, less than 256 bytes (a partial page) can be programmed without having any effect on other bytes within the same page. One condition to perform a partial page program is that the number of clocks cannot exceed the remaining page length. If more than 256 bytes are sent to the device the addressing will wrap to the beginning of the page and overwrite previously sent data.

As with the write and erase instructions, the /CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not done the Page Program instruction will not be executed. After /CS is driven high, the self-timed Page Program instruction will commence for a time duration of tpp (See AC Characteristics). While the Page Program cycle is in progress, the Read Status Register instruction may still be accessed for checking the status of the BUSY bit. The BUSY bit is a 1 during the Page Program cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions again. After the Page Program cycle has finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Page Program instruction will not be executed if the addressed page is protected by the Block Protect (CMP, SEC, TB, BP2, BP1, and BP0) bits or the Individual Block/Sector Locks.

/CS

Mode 3 0 1 2 3 4 5 6 7

CLK

Mode 0

Instruction (02h)

(IO0)

= MSB

/CS

CLK

(IO0)

40 41 42 43 44 45 46 47

Data Byte 2

7 6 5 4 3 2 1 0

Figure 29a. Page Program Instruction (SPI Mode)

8 9 10 28 29 30 39

24-Bit Address

23 22 21 3 2 1

48 49 50 52 53 54 55

7 6 5 4 3 2 1 0

5139

Data Byte 3

31032 33 34 35 36 37 38

Data Byte 1

7 6 5 4 3 2 1

2072

2073

2074

2075

Data Byte 256

7 6 5 4 3 2 1 0

2076

2077

Mode 3

2078

2079

Mode 0

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W25Q32FV

CLK

Mode 3 0 1 Mode 0

Instruction

02h

2 3 4 5

A23-16

20 16 12 8

21 17

22 18

23 19

A15-8 A7-0 Byte1 Byte 2 Byte 3

13 9

14 10

15 11

6 7 8 9

4 0

5 1

6 2

7 3

4 0

5 1

6 2

7 3

10 11 12 13

4 0

5 1

6 2

7 3

Figure 29b. Page Program Instruction (QPI Mode)

4 0

5 1

6 2

7 3

516

517

518

Byte 255 Byte 256

4 0

5 1

6 2

7 3

4 0

5 1

6 2

7 3

Mode 3

519

Mode 0

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8.2.16 Quad Input Page Program (32h)

The Quad Page Program instruction allows up to 256 bytes of data to be programmed at previously erased (FFh) memory locations using four pins: IO0, IO1, IO2, and IO3. The Quad Page Program can improve performance for PROM Programmer and applications that have slow clock speeds <5MHz. Systems with faster clock speed will not realize much benefit for the Quad Page Program instruction since the inherent page program time is much greater than the time it take to clock-in the data.

To use Quad Page Program the Quad Enable (QE) bit in Status Register-2 must be set to 1. A Write Enable instruction must be executed before the device will accept the Quad Page Program instruction (Status Register-1, WEL=1). The instruction is initiated by driving the /CS pin low then shifting the instruction code “32h” followed by a 24-bit address (A23-A0) and at least one data byte, into the IO pins. The /CS pin must be held low for the entire length of the instruction while data is being sent to the device. All other functions of Quad Page Program are identical to standard Page Program. The Quad Page Program instruction sequence is shown in Figure 30.

/CS

Mode 3 0 1 2 3 4 5 6 7

CLK

Mode 0

Instruction (32h)

8 9 10 28 29 30

24-Bit Address

23 22 21 3 2 1 0

= MSB

/CS

536

537

538

539

540

541

542

Byte

256

4 0

5 1

6 2

7 3

543

Mode 3 Mode 0

CLK

32 33 34 35 36 37

Byte 1

0 4 0

5 1

6 2

7 3

Byte 2 Byte 3

4 0

5 1

6 2

7 3

4 0

5 1

6 2

7 3

Byte

253

4 0

5 1

6 2

7 3

Byte

254

4 0

5 1

6 2

7 3

* * * * * * *

Byte

255

4 0

5 1

6 2

7 3

Figure 30. Quad Input Page Program Instruction (SPI Mode only)

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8.2.17 Sector Erase (20h)

The Sector Erase instruction sets all memory within a specified sector (4K-bytes) to the erased state of all 1s (FFh). A Write Enable instruction must be executed before the device will accept the Sector Erase Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and shifting the instruction code “20h” followed a 24-bit sector address (A23-A0). The Sector Erase instruction sequence is shown in Figure 31a & 31b.

The /CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not done the Sector Erase instruction will not be executed. After /CS is driven high, the self-timed Sector Erase instruction will commence for a time duration of tSE (See AC Characteristics). While the Sector Erase cycle is in progress, the Read Status Register instruction may still be accessed for checking the status of the BUSY bit. The BUSY bit is a 1 during the Sector Erase cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions again. After the Sector Erase cycle has finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Sector Erase instruction will not be executed if the addressed page is protected by the Block Protect (CMP, SEC, TB, BP2, BP1, and BP0) bits or the Individual Block/Sector Locks.

/CS

Mode 3 0 1 2 3 4 5 6 7

CLK

Mode 0

Instruction (20h)

(IO0)

8 9 29 30 31

24-Bit Address

23 22 2 1 0

Mode 3 Mode 0

(IO1)

= MSB

Figure 31a. Sector Erase Instruction (SPI Mode)

High Impedance

/CS

CLK

Mode 3 0 1 Mode 0

Instruction

20h

Figure 31b. Sector Erase Instruction (QPI Mode)

2 3 4 5

A23-16

20 16 12 8

21 17

22 18

23 19

A15-8 A7-0

13 9

14 10

15 11

6 7

4 0

5 1

6 2

7 3

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8.2.18 32KB Block Erase (52h)

The Block Erase instruction sets all memory within a specified block (32K-bytes) to the erased state of all 1s (FFh). A Write Enable instruction must be executed before the device will accept the Block Erase Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and shifting the instruction code “52h” followed a 24-bit block address (A23-A0). The Block Erase instruction sequence is shown in Figure 32a & 32b.

The /CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not done the Block Erase instruction will not be executed. After /CS is driven high, the self-timed Block Erase instruction will commence for a time duration of tBE1 (See AC Characteristics). While the Block Erase cycle is in progress, the Read Status Register instruction may still be accessed for checking the status of the BUSY bit. The BUSY bit is a 1 during the Block Erase cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions again. After the Block Erase cycle has finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Block Erase instruction will not be executed if the addressed page is protected by the Block Protect (CMP, SEC, TB, BP2, BP1, and BP0) bits or the Individual Block/Sector Locks.

/CS

Mode 3 0 1 2 3 4 5 6 7

CLK

Mode 0

Instruction (52h)

(IO0)

8 9 29 30 31

24-Bit Address

23 22 2 1 0

Mode 3 Mode 0

(IO1)

= MSB

Figure 32a. 32KB Block Erase Instruction (SPI Mode)

High Impedance

/CS

Mode 3 0 1

CLK

Mode 0

Instruction

52h

Figure 32b. 32KB Block Erase Instruction (QPI Mode)

2 3 4 5

A23-16

20 16 12 8

21 17

22 18

23 19

A15-8 A7-0

13 9

14 10

15 11

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4 0

5 1

6 2

7 3

Mode 3 Mode 0

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8.2.19 64KB Block Erase (D8h)

The Block Erase instruction sets all memory within a specified block (64K-bytes) to the erased state of all 1s (FFh). A Write Enable instruction must be executed before the device will accept the Block Erase Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and shifting the instruction code “D8h” followed a 24-bit block address (A23-A0). The Block Erase instruction sequence is shown in Figure 33a & 33b.

The /CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not done the Block Erase instruction will not be executed. After /CS is driven high, the self-timed Block Erase instruction will commence for a time duration of tBE (See AC Characteristics). While the Block Erase cycle is in progress, the Read Status Register instruction may still be accessed for checking the status of the BUSY bit. The BUSY bit is a 1 during the Block Erase cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions again. After the Block Erase cycle has finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Block Erase instruction will not be executed if the addressed page is protected by the Block Protect (CMP, SEC, TB, BP2, BP1, and BP0) bits or the Individual Block/Sector Locks.

/CS

Mode 3 0 1 2 3 4 5 6 7

CLK

Mode 0

(IO0)

Instruction (D8h)

8 9 29 30 31

24-Bit Address

23 22 2 1 0

Mode 3 Mode 0

(IO1)

= MSB

Figure 33a. 64KB Block Erase Instruction (SPI Mode)

High Impedance

/CS

Mode 3 0 1

CLK

Mode 0

Instruction

D8h

Figure 33b. 64KB Block Erase Instruction (QPI Mode)

2 3 4 5

A23-16

20 16 12 8

21 17

22 18

23 19

A15-8 A7-0

13 9

14 10

15 11

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6 7

4 0

5 1

6 2

7 3

Mode 3 Mode 0

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8.2.20 Chip Erase (C7h / 60h)

The Chip Erase instruction sets all memory within the device to the erased state of all 1s (FFh). A Write Enable instruction must be executed before the device will accept the Chip Erase Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and shifting the instruction code “C7h” or “60h”. The Chip Erase instruction sequence is shown in Figure 34.

The /CS pin must be driven high after the eighth bit has been latched. If this is not done the Chip Erase instruction will not be executed. After /CS is driven high, the self-timed Chip Erase instruction will commence for a time duration of tCE (See AC Characteristics). While the Chip Erase cycle is in progress, the Read Status Register instruction may still be accessed to check the status of the BUSY bit. The BUSY bit is a 1 during the Chip Erase cycle and becomes a 0 when finished and the device is ready to accept other instructions again. After the Chip Erase cycle has finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Chip Erase instruction will not be executed if any memory region is protected by the Block Protect (CMP, SEC, TB, BP2, BP1, and BP0) bits or the Individual Block/Sector Locks.

/CS

Mode 3 0 1 2 3 4 5 6 7

CLK

(IO0)

Mode 0

Instruction (C7h/60h)

Mode 3 Mode 0

/CS

CLK

Mode 3 0 1 Mode 0

Mode 3 Mode 0

Instruction

C7h/60h

(IO1)

High Impedance

Figure 34. Chip Erase Instruction for SPI Mode (left) or QPI Mode (right)

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8.2.21 Erase / Program Suspend (75h)

The Erase/Program Suspend instruction “75h”, allows the system to interrupt a Sector or Block Erase operation or a Page Program operation and then read from or program/erase data to, any other sectors or blocks. The Erase/Program Suspend instruction sequence is shown in Figure 35a & 35b.

The Write Status Register instruction (01h) and Erase instructions (20h, 52h, D8h, C7h, 60h, 44h) are not allowed during Erase Suspend. Erase Suspend is valid only during the Sector or Block erase operation. If written during the Chip Erase operation, the Erase Suspend instruction is ignored. The Write Status Register instruction (01h) and Program instructions (02h, 32h, 42h) are not allowed during Program Suspend. Program Suspend is valid only during the Page Program or Quad Page Program operation.

The Erase/Program Suspend instruction “75h” will be accepted by the device only if the SUS bit in the Status Register equals to 0 and the BUSY bit equals to 1 while a Sector or Block Erase or a Page Program operation is on-going. If the SUS bit equals to 1 or the BUSY bit equals to 0, the Suspend instruction will be ignored by the device. A maximum of time of “t

” (See AC Characteristics) is required

SUS

to suspend the erase or program operation. The BUSY bit in the Status Register will be cleared from 1 to 0 within “t

” and the SUS bit in the Status Register will be set from 0 to 1 immediately after

SUS

Erase/Program Suspend. For a previously resumed Erase/Program operation, it is also required that the Suspend instruction “75h” is not issued earlier than a minimum of time of “t

” following the preceding

SUS

Resume instruction “7Ah”.

Unexpected power off during the Erase/Program suspend state will reset the device and release the suspend state. SUS bit in the Status Register will also reset to 0. The data within the page, sector or block that was being suspended may become corrupted. It is recommended for the user to implement system design techniques against the accidental power interruption and preserve data integrity during erase/program suspend state.

/CS

CLK

(IO0)

(IO1)

Mode 3 0 1 2 3 4 5 6 7 Mode 0

Instruction (75h)

High Impedance

Figure 35a. Erase/Program Suspend Instruction (SPI Mode)

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tSUS

Mode 3 Mode 0

Accept instructions

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/CS

tSUS

Mode 3 Mode 0

Accept instructions

CLK

Mode 3 0 1 Mode 0

Instruction

75h

Figure 35b. Erase/Program Suspend Instruction (QPI Mode)

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8.2.22 Erase / Program Resume (7Ah)

The Erase/Program Resume instruction “7Ah” must be written to resume the Sector or Block Erase operation or the Page Program operation after an Erase/Program Suspend. The Resume instruction “7Ah” will be accepted by the device only if the SUS bit in the Status Register equals to 1 and the BUSY bit equals to 0. After issued the SUS bit will be cleared from 1 to 0 immediately, the BUSY bit will be set from 0 to 1 within 200ns and the Sector or Block will complete the erase operation or the page will complete the program operation. If the SUS bit equals to 0 or the BUSY bit equals to 1, the Resume instruction “7Ah” will be ignored by the device. The Erase/Program Resume instruction sequence is shown in Figure 36a & 36b.

Resume instruction is ignored if the previous Erase/Program Suspend operation was interrupted by unexpected power off. It is also required that a subsequent Erase/Program Suspend instruction not to be issued within a minimum of time of “t

/CS

Mode 3 0 1 2 3 4 5 6 7

CLK

(IO0)

Mode 0

Figure 36a. Erase/Program Resume Instruction (SPI Mode)

” following a previous Resume instruction.

SUS

Instruction (7Ah)

Resume previously suspended Program or Erase

Mode 3 Mode 0

/CS

Mode 3 0 1

CLK

Mode 0

Instruction

7Ah

Figure 36b. Erase/Program Resume Instruction (QPI Mode)

Mode 3 Mode 0

Resume previously suspended Program or Erase

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8.2.23 Power-down (B9h)

Although the standby current during normal operation is relatively low, standby current can be further reduced with the Power-down instruction. The lower power consumption makes the Power-down instruction especially useful for battery powered applications (See ICC1 and ICC2 in AC Characteristics). The instruction is initiated by driving the /CS pin low and shifting the instruction code “B9h” as shown in Figure 37a & 37b.

The /CS pin must be driven high after the eighth bit has been latched. If this is not done the Power-down instruction will not be executed. After /CS is driven high, the power-down state will entered within the time duration of tDP (See AC Characteristics). While in the power-down state only the Release Power-down / Device ID (ABh) instruction, which restores the device to normal operation, will be recognized. All other instructions are ignored. This includes the Read Status Register instruction, which is always available during normal operation. Ignoring all but one instruction makes the Power Down state a useful condition for securing maximum write protection. The device always powers-up in the normal operation with the standby current of ICC1.

/CS

tDP

Mode 3 Mode 0

CLK

(IO0)

Mode 3 0 1 2 3 4 5 6 7 Mode 0

Instruction (B9h)

Power-down currentStand-by current

Figure 37a. Deep Power-down Instruction (SPI Mode)

/CS

Mode 3 0 1

CLK

Mode 0

Instruction

B9h

Figure 37b. Deep Power-down Instruction (QPI Mode)

tDP

Mode 3 Mode 0

Power-down currentStand-by current

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8.2.24 Release Power-down / Device ID (ABh)

The Release from Power-down / Device ID instruction is a multi-purpose instruction. It can be used to release the device from the power-down state, or obtain the devices electronic identification (ID) number.

To release the device from the power-down state, the instruction is issued by driving the /CS pin low, shifting the instruction code “ABh” and driving /CS high as shown in Figure 38a & 38b. Release from power-down will take the time duration of t normal operation and other instructions are accepted. The /CS pin must remain high during the t

RES1

(See AC Characteristics) before the device will resume

RES1

time

duration. When used only to obtain the Device ID while not in the power-down state, the instruction is initiated by

driving the /CS pin low and shifting the instruction code “ABh” followed by 3-dummy bytes. The Device ID bits are then shifted out on the falling edge of CLK with most significant bit (MSB) first. The Device ID value for the W25Q32FV is listed in Manufacturer and Device Identification table. The Device ID can be read continuously. The instruction is completed by driving /CS high.

When used to release the device from the power-down state and obtain the Device ID, the instruction is the same as previously described, and shown in Figure 38c & 38d, except that after /CS is driven high it must remain high for a time duration of t

RES2

(See AC Characteristics). After this time duration the device will resume normal operation and other instructions will be accepted. If the Release from Power-down / Device ID instruction is issued while an Erase, Program or Write cycle is in process (when BUSY equals

1) the instruction is ignored and will not have any effects on the current cycle.

/CS

tRES1

CLK

(IO0)

Mode 3 0 1 2 3 4 5 6 7 Mode 0

Instruction (ABh)

Mode 3 Mode 0

Power-down current Stand-by current

Figure 38a. Release Power-down Instruction (SPI Mode)

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/CS

CLK

Mode 3 0 1 Mode 0

Instruction

ABh

tRES1

W25Q32FV

Mode 3 Mode 0

/CS

Mode 3 0 1 2 3 4 5 6 7

CLK

Mode 0

(IO0)

(IO1)

= MSB

Instruction (ABh)

Figure 38c. Release Power-down / Device ID Instruction (SPI Mode)

/CS

Mode 3 0 1

CLK

Mode 0

Power-down current Stand-by current

Figure 38b. Release Power-down Instruction (QPI Mode)

High Impedance

8 9 29 30 31

3 Dummy Bytes

23 22 2 1 0

32 33 34 35 36 37 38

Device ID

7 6 5 4 3 2 1 0

6 7 8

X X

4 0

5 1

IOs switch from Input to Output

Instruction

ABh

2 3 4 5

3 Dummy Bytes

X X

Mode 3 Mode 0

tRES2

Power-down current Stand-by current

tRES2

Mode 3 Mode 0

X X

6 2

7 3

Device ID

Power-down current Stand-by current

Figure 38d. Release Power-down / Device ID Instruction (QPI Mode)

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8.2.25 Read Manufacturer / Device ID (90h)

The Read Manufacturer/Device ID instruction is an alternative to the Release from Power-down / Device ID instruction that provides both the JEDEC assigned manufacturer ID and the specific device ID.

The Read Manufacturer/Device ID instruction is very similar to the Release from Power-down / Device ID instruction. The instruction is initiated by driving the /CS pin low and shifting the instruction code “90h” followed by a 24-bit address (A23-A0) of 000000h. After which, the Manufacturer ID for Winbond (EFh) and the Device ID are shifted out on the falling edge of CLK with most significant bit (MSB) first as shown in Figure 39. The Device ID values for the W25Q32FV are listed in Manufacturer and Device Identification table. The instruction is completed by driving /CS high.

/CS

Mode 3 0 1 2 3 4 5 6 7

CLK

(IO0)

Mode 0

Instruction (90h)

8 9 10 28 29 30 31

Address (000000h)

23 22 21 3 2 1 0

(IO1)

/CS

CLK

= MSB

32 33 34 35 36 37 38 39

High Impedance

40 41 42 44 45 46

4331

Mode 3 Mode 0

(IO0)

(IO1)

7 6 5 4 3 2 1 0

Manufacturer ID (EFh)

Figure 39. Read Manufacturer / Device ID Instruction (SPI Mode)

Device ID

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8.2.26 Read Manufacturer / Device ID Dual I/O (92h)

The Read Manufacturer / Device ID Dual I/O instruction is an alternative to the Read Manufacturer / Device ID instruction that provides both the JEDEC assigned manufacturer ID and the specific device ID at 2x speed.

The Read Manufacturer / Device ID Dual I/O instruction is similar to the Fast Read Dual I/O instruction. The instruction is initiated by driving the /CS pin low and shifting the instruction code “92h” followed by a 24-bit address (A23-A0) of 000000h, but with the capability to input the Address bits two bits per clock. After which, the Manufacturer ID for Winbond (EFh) and the Device ID are shifted out 2 bits per clock on the falling edge of CLK with most significant bits (MSB) first as shown in Figure 40. The Device ID values for the W25Q32FV are listed in Manufacturer and Device Identification table.The Manufacturer and Device IDs can be read continuously, alternating from one to the other. The instruction is completed by

= MSB

Instruction (92h)

High Impedance

8 9 10 11 12 13 14 15 16 17 18 19 20 21 22

A23-16 A15-8 A7-0 (00h) M7-0

6 4 2 0

7 5 3 1

* *

6 4 2 0

7 5 3 1

6 4 2 0

7 5 3 1

* *

6 4 2 0

7 5 3 1

driving /CS high.

/CS

Mode 3 0 1 2 3 4 5 6 7

CLK

Mode 0

(IO0)

(IO1)

/CS

CLK

(IO0)

(IO1)

24 25 26 27 28 29 30 31 32 33 34 36 37 383523

IOs switch from Input to Output

6 4 2 0

7 5 3 1

* ** *

MFR ID Device ID

6 4 2 0

7 5 3 1

6 4 2 0

7 5 3 1

MFR ID

(repeat)

6 4 210

7 5 3

Device ID

(repeat)

Mode 3 Mode 0

Figure 40. Read Manufacturer / Device ID Dual I/O Instruction (SPI Mode only)

Note: The “Continuous Read Mode” bits M(7-0) must be set to Fxh to be compatible with Fast Read Dual I/O instruction.

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8.2.27 Read Manufacturer / Device ID Quad I/O (94h)

The Read Manufacturer / Device ID Quad I/O instruction is an alternative to the Read Manufacturer / Device ID instruction that provides both the JEDEC assigned manufacturer ID and the specific device ID at 4x speed.

The Read Manufacturer / Device ID Quad I/O instruction is similar to the Fast Read Quad I/O instruction. The instruction is initiated by driving the /CS pin low and shifting the instruction code “94h” followed by a four clock dummy cycles and then a 24-bit address (A23-A0) of 000000h, but with the capability to input the Address bits four bits per clock. After which, the Manufacturer ID for Winbond (EFh) and the Device ID are shifted out four bits per clock on the falling edge of CLK with most significant bit (MSB) first as shown in Figure 41. The Device ID values for the W25Q32FV are listed in Manufacturer and Device Identification table. The Manufacturer and Device IDs can be read continuously, alternating from one to

4 0

5 1

6 2

7 3

A7-0

(00h)

4 0

5 1

6 2

7 3

M7-0

4 0

5 1

6 2

7 3

Dummy Dummy

IOs switch from Input to Output

4 0

5 1

6 2

7 3

MFR ID Device ID

4 0

5 1

6 2

7 3

the other. The instruction is completed by driving /CS high.

/CS

Mode 3 0 1 2 3 4 5 6 7

CLK

Mode 0

Instruction (94h)

High Impedance

8 9 10 11 12 13 14 15 16 17 18 19 20 21 22

A23-16 A15-8

4 0

5 1

6 2

7 3

/CS

CLK

24 25 26 27 28 29 30

4 0

5 1

6 2

7 3 MFR ID

(repeat)

4 0

5 1

6 2

7 3

Device ID

(repeat)

4 0

5 1

6 2

7 3

MFR ID (repeat)

4 0

5 1

6 2

7 3

Device ID

(repeat)

Mode 3 Mode 0

Figure 41. Read Manufacturer / Device ID Quad I/O Instruction (SPI Mode only)

Note

The “Continuous Read Mode” bits M(7-0) must be set to Fxh to be compatible with Fast Read Quad I/O instruction.

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8.2.28 Read Unique ID Number (4Bh)

The Read Unique ID Number instruction accesses a factory-set read-only 64-bit number that is unique to each W25Q32FV device. The ID number can be used in conjunction with user software methods to help prevent copying or cloning of a system. The Read Unique ID instruction is initiated by driving the /CS pin low and shifting the instruction code “4Bh” followed by a four bytes of dummy clocks. After which, the 64bit ID is shifted out on the falling edge of CLK as shown in Figure 42.

/CS

Mode 3 0 1 2 3 4 5 6 7

CLK

Mode 0

Instruction (4Bh)

(IO0)

(IO1)

/CS

CLK

(IO0)

24 25 26 27 28 29 30 31 32 33 34 36 37 383523

Dummy Byte 3 Dummy Byte 4

8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

Dummy Byte 1 Dummy Byte 2

High Impedance

39 40 41 42

100

101

102

Mode 3 Mode 0

(IO1)

= MSB

High Impedance

63 62 61 2 1 0

64-bit Unique Serial Number

Figure 42. Read Unique ID Number Instruction (SPI Mode only)

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8.2.29 Read JEDEC ID (9Fh)

For compatibility reasons, the W25Q32FV provides several instructions to electronically determine the identity of the device. The Read JEDEC ID instruction is compatible with the JEDEC standard for SPI compatible serial memories that was adopted in 2003. The instruction is initiated by driving the /CS pin low and shifting the instruction code “9Fh”. The JEDEC assigned Manufacturer ID byte for Winbond (EFh) and two Device ID bytes, Memory Type (ID15-ID8) and Capacity (ID7-ID0) are then shifted out on the falling edge of CLK with most significant bit (MSB) first as shown in Figure 43a & 43b. For memory type and capacity values refer to Manufacturer and Device Identification table.

/CS

Mode 3 0 1 2 3 4 5 6 7

CLK

Mode 0

Instruction (9Fh)

(IO0)

(IO1)

/CS

CLK

= MSB

16 17 18 19 20 21 22 23

High Impedance

8 9 10 12 13 14 15

24 25 26 28 29 30

Manufacturer ID (EFh)

2715

Mode 3 Mode 0

(IO0)

(IO1)

Memory Type ID15-8

7 6 5 4 3 2 1 0

Figure 43a. Read JEDEC ID Instruction (SPI Mode)

/CS

Mode 3 0 1

CLK

Mode 0

Figure 43b. Read JEDEC ID Instruction (QPI Mode)

Instruction

9Fh

Capacity ID7-0

7 6 5 4 3 2 1 0

2 3 4 5

IOs switch from Input to Output

12 8

13 9

14 10

15 11

EFh

ID15-8 ID7-0

4 0

5 1

6 2

7 3

Mode 3 Mode 0

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8.2.30 Read SFDP Register (5Ah)

The W25Q32FV features a 256-Byte Serial Flash Discoverable Parameter (SFDP) register that contains information about device configurations, available instructions and other features. The SFDP parameters are stored in one or more Parameter Identification (PID) tables. Currently only one PID table is specified, but more may be added in the future. The Read SFDP Register instruction is compatible with the SFDP standard initially established in 2010 for PC and other applications, as well as the JEDEC standard JESD216 that is published in 2011. Most Winbond SpiFlash Memories shipped after June 2011 (date code 1124 and beyond) support the SFDP feature as specified in the applicable datasheet.

The Read SFDP instruction is initiated by driving the /CS pin low and shifting the instruction code “5Ah” followed by a 24-bit address (A23-A0)

(1)

into the DI pin. Eight “dummy” clocks are also required before the SFDP register contents are shifted out on the falling edge of the 40th CLK with most significant bit (MSB) first as shown in Figure 34. For SFDP register values and descriptions, please refer to the Winbond Application Note for SFDP Definition Table.

Note 1: A23-A8 = 0; A7-A0 are used to define the starting byte address for the 256-Byte SFDP Register.

/CS

Mode 3 0 1 2 3 4 5 6 7

CLK

Mode 0

Instruction (5Ah)

(IO0)

8 9 10 28 29 30 31

24-Bit Address

23 22 21 3 2 1 0

(IO1)

High Impedance

/CS

CLK

(IO0)

(IO1)

32 33 34 35 36 37 38 39

Dummy Byte

7 6 5 4 3 2 1 0

High Impedance

= MSB

Figure 34. Read SFDP Register Instruction Sequence Diagram

40 41 42 44 45 46 47 48 49 50 51 52 53 54 55

7 6 5 4 3 2 1 0

4331

Data Out 1

Data Out 2

7 6 5 4 3 2 1 0 7

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8.2.31 Erase Security Registers (44h)

The W25Q32FV offers three 256-byte Security Registers which can be erased and programmed individually. These registers may be used by the system manufacturers to store security and other important information separately from the main memory array.

The Erase Security Register instruction is similar to the Sector Erase instruction. A Write Enable instruction must be executed before the device will accept the Erase Security Register Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and shifting the instruction code “44h” followed by a 24-bit address (A23-A0) to erase one of the three security registers.

ADDRESS A23-16 A15-12 A11-8 A7-0

Security Register #1 00h 0 0 0 1 0 0 0 0 Don’t Care Security Register #2 00h 0 0 1 0 0 0 0 0 Don’t Care Security Register #3 00h 0 0 1 1 0 0 0 0 Don’t Care

The Erase Security Register instruction sequence is shown in Figure 45. The /CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not done the instruction will not be executed. After /CS is driven high, the self-timed Erase Security Register operation will commence for a time duration of tSE (See AC Characteristics). While the Erase Security Register cycle is in progress, the Read Status Register instruction may still be accessed for checking the status of the BUSY bit. The BUSY bit is a 1 during the erase cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions again. After the Erase Security Register cycle has finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Security Register Lock Bits (LB3-1) in the Status Register-2 can be used to OTP protect the security registers. Once a lock bit is set to 1, the corresponding security register will be permanently locked, Erase Security Register instruction to that register will be ignored (Refer to section 7.1.8 for detail descriptions).

/CS

CLK

(IO0)

(IO1)

Mode 3 0 1 2 3 4 5 6 7 Mode 0

Instruction (44h)

High Impedance

= MSB

Figure 45. Erase Security Registers Instruction (SPI Mode only)

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8 9 29 30 31

24-Bit Address

23 22 2 1 0

Mode 3 Mode 0

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8.2.32 Program Security Registers (42h)

The Program Security Register instruction is similar to the Page Program instruction. It allows from one byte to 256 bytes of security register data to be programmed at previously erased (FFh) memory locations. A Write Enable instruction must be executed before the device will accept the Program Security Register Instruction (Status Register bit WEL= 1). The instruction is initiated by driving the /CS pin low then shifting the instruction code “42h” followed by a 24-bit address (A23-A0) and at least one data byte, into the DI pin. The /CS pin must be held low for the entire length of the instruction while data is being sent to the device.

ADDRESS A23-16 A15-12 A11-8 A7-0

Security Register #1 00h 0 0 0 1 0 0 0 0 Byte Address Security Register #2 00h 0 0 1 0 0 0 0 0 Byte Address Security Register #3 00h 0 0 1 1 0 0 0 0 Byte Address

The Program Security Register instruction sequence is shown in Figure 46. The Security Register Lock Bits (LB3-1) in the Status Register-2 can be used to OTP protect the security registers. Once a lock bit is set to 1, the corresponding security register will be permanently locked, Program Security Register instruction to that register will be ignored (See 7.1.8, 8.2.25 for detail descriptions).

/CS

Mode 3 0 1 2 3 4 5 6 7

CLK

Mode 0

Instruction (42h)

(IO0)

= MSB

/CS

8 9 10 28 29 30 39

24-Bit Address

23 22 21 3 2 1

31032 33 34 35 36 37 38

7 6 5 4 3 2 1

Data Byte 1

CLK

(IO0)

40 41 42 43 44 45 46 47

Data Byte 2

7 6 5 4 3 2 1 0

Figure 46. Program Security Registers Instruction (SPI Mode only)

48 49 50 52 53 54 55

7 6 5 4 3 2 1 0

5139

Data Byte 3

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2072

2073

2074

2075

2076

2077

2078

Data Byte 256

7 6 5 4 3 2 1 0

Mode 3

2079

Mode 0

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8.2.33 Read Security Registers (48h)

The Read Security Register instruction is similar to the Fast Read instruction and allows one or more data bytes to be sequentially read from one of the four security registers. The instruction is initiated by driving the /CS pin low and then shifting the instruction code “48h” followed by a 24-bit address (A23-A0) and eight “dummy” clocks into the DI pin. The code and address bits are latched on the rising edge of the CLK pin. After the address is received, the data byte of the addressed memory location will be shifted out on the DO pin at the falling edge of CLK with most significant bit (MSB) first. The byte address is automatically incremented to the next byte address after each byte of data is shifted out. Once the byte address reaches the last byte of the register (byte address FFh), it will reset to address 00h, the first byte of the register, and continue to increment. The instruction is completed by driving /CS high. The Read Security Register instruction sequence is shown in Figure 47. If a Read Security Register instruction is issued while an Erase, Program or Write cycle is in process (BUSY=1) the instruction is ignored and will not have any effects on the current cycle. The Read Security Register instruction allows clock rates from D.C. to a maximum of FR (see AC Electrical Characteristics).

ADDRESS A23-16 A15-12 A11-8 A7-0

Security Register #1 00h 0 0 0 1 0 0 0 0 Byte Address Security Register #2 00h 0 0 1 0 0 0 0 0 Byte Address Security Register #3 00h 0 0 1 1 0 0 0 0 Byte Address

/CS

Mode 3 0 1 2 3 4 5 6 7

CLK

Mode 0

Instruction (48h)

(IO0)

8 9 10 28 29 30 31

24-Bit Address

23 22 21 3 2 1 0

(IO1)

/CS

CLK

(IO0)

(IO1)

= MSB

32 33 34 35 36 37 38 39

Dummy Byte

7 6 5 4 3 2 1 0

High Impedance

40 41 42 44 45 46 47 48 49 50 51 52 53 54 55

7 6 5 4 3 2 1 0

4331

Data Out 1

Data Out 2

7 6 5 4 3 2 1 0 7

Figure 47. Read Security Registers Instruction (SPI Mode only)

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0 1

1 1

8.2.34 Set Read Parameters (C0h)

In QPI mode, to accommodate a wide range of applications with different needs for either maximum read frequency or minimum data access latency, “Set Read Parameters (C0h)” instruction can be used to configure the number of dummy clocks for “Fast Read (0Bh)”, “Fast Read Quad I/O (EBh)” & “Burst Read with Wrap (0Ch)” instructions, and to configure the number of bytes of “Wrap Length” for the “Burst Read with Wrap (0Ch)” instruction.

In Standard SPI mode, the “Set Read Parameters (C0h)” instruction is not accepted. The dummy clocks for various Fast Read instructions in Standard/Dual/Quad SPI mode are fixed, please refer to the Instruction Table 1-2 for details. The “Wrap Length” is set by W5-4 bit in the “Set Burst with Wrap (77h)” instruction. This setting will remain unchanged when the device is switched from Standard SPI mode to QPI mode.

The default “Wrap Length” after a power up or a Reset instruction is 8 bytes, the default number of dummy clocks is 2. The number of dummy clocks is only programmable for “Fast Read (0Bh)”, “Fast Read Quad I/O (EBh)” & “Burst Read with Wrap (0Ch)” instructions in the QPI mode. Whenever the device is switched from SPI mode to QPI mode, the number of dummy clocks should be set again, prior to any 0Bh, EBh or 0Ch instructions.

MAXIMUM

READ FREQ.

(A[1:0]=0,0)

P1 – P0

0 0

WRAP

LENGTH

8-byte

16-byte

1 0 32-byte

64-byte

P5 – P4

0 0

DUMMY

CLOCKS

2 33MHz 33MHz

MAXIMUM

READ FREQ.

4 55MHz 80MHz

1 0 6 80MHz 104MHz

8 104MHz 104MHz

/CS

CLK

Mode 3 0 1

Mode 0

Instruction

C0h

2 3

Read

Parameters

P4 P0

P5 P1

P6 P2

P7 P3

Mode 3 Mode 0

Figure 48. Set Read Parameters Instruction (QPI Mode only)

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8.2.35 Burst Read with Wrap (0Ch)

The “Burst Read with Wrap (0Ch)” instruction provides an alternative way to perform the read operation with “Wrap Around” in QPI mode. The instruction is similar to the “Fast Read (0Bh)” instruction in QPI mode, except the addressing of the read operation will “Wrap Around” to the beginning boundary of the “Wrap Length” once the ending boundary is reached.

The “Wrap Length” and the number of dummy clocks can be configured by the “Set Read Parameters (C0h)” instruction.

/CS

CLK

Mode 3 0 1 Mode 0

Instruction

0Ch

"Set Read Parameters" instruction (C0h) can

set the number of dummy clocks.

2 3 4 5

A23-16

20 16 12 8

21 17

22 18

23 19

A15-8 A7-0

13 9

14 10

15 11

6 7 8 9

Dummy

4 0

5 1

6 2

7 3

10 11 12 13 14

4 0

5 1

6 2

7 3

Byte 1 Byte 2

IOs switch from Input to Output

4 0

5 1

6 2

7 3

Byte 3

Figure 49. Burst Read with Wrap Instruction (QPI Mode only)

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8.2.36 Enter QPI Mode (38h)

The W25Q32FV support both Standard/Dual/Quad Serial Peripheral Interface (SPI) and Quad Peripheral Interface (QPI). However, SPI mode and QPI mode cannot be used at the same time. “Enter QPI (38h)” instruction is the only way to switch the device from SPI mode to QPI mode.

Upon power-up, the default state of the device upon is Standard/Dual/Quad SPI mode. This provides full backward compatibility with earlier generations of Winbond serial flash memories. See Instruction Set Table 1-3 for all supported SPI commands. In order to switch the device to QPI mode, the Quad Enable (QE) bit in Status Register-2 must be set to 1 first, and an “Enter QPI (38h)” instruction must be issued. If the Quad Enable (QE) bit is 0, the “Enter QPI (38h)” instruction will be ignored and the device will remain in SPI mode.

See Instruction Set Table 3 for all the commands supported in QPI mode. When the device is switched from SPI mode to QPI mode, the existing Write Enable and Program/Erase

Suspend status, and the Wrap Length setting will remain unchanged.

/CS

CLK

(IO0)

Mode 3 0 1 2 3 4 5 6 7 Mode 0

Instruction (38h)

Mode 3 Mode 0

(IO1)

Figure 50. Enter QPI Instruction (SPI Mode only)

High Impedance

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8.2.37 Exit QPI Mode (FFh)

In order to exit the QPI mode and return to the Standard/Dual/Quad SPI mode, an “Exit QPI (FFh)” instruction must be issued.

When the device is switched from QPI mode to SPI mode, the existing Write Enable Latch (WEL) and Program/Erase Suspend status, and the Wrap Length setting will remain unchanged.

/CS

CLK

Mode 3 0 1 Mode 0

Instruction

FFh

Mode 3 Mode 0

Figure 51. Exit QPI Instruction (QPI Mode only)

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8.2.38 Individual Block/Sector Lock (36h)

The Individual Block/Sector Lock provides an alternative way to protect the memory array from adverse Erase/Program. In order to use the Individual Block/Sector Locks, the WPS bit in Status Register-3 must be set to 1. If WPS=0, the write protection will be determined by the combination of CMP, SEC, TB, BP[2:0] bits in the Status Registers. The Individual Block/Sector Lock bits are volatile bits. The default values after device power up or after a Reset are 1, so the entire memory array is being protected.

To lock a specific block or sector as illustrated in Figure 4d, an Individual Block/Sector Lock command must be issued by driving /CS low, shifting the instruction code “36h” into the Data Input (DI) pin on the rising edge of CLK, followed by a 24-bit address and then driving /CS high. A Write Enable instruction must be executed before the device will accept the Individual Block/Sector Lock Instruction (Status Register bit WEL= 1).

Figure 52a. Individual Block/Sector Lock Instruction (SPI Mode)

Figure 52b. Individual Block/Sector Lock Instruction (QPI Mode)

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8.2.39 Individual Block/Sector Unlock (39h)

To unlock a specific block or sector as illustrated in Figure 4d, an Individual Block/Sector Unlock command must be issued by driving /CS low, shifting the instruction code “39h” into the Data Input (DI) pin on the rising edge of CLK, followed by a 24-bit address and then driving /CS high. A Write Enable instruction must be executed before the device will accept the Individual Block/Sector Unlock Instruction (Status Register bit WEL= 1).

Figure 53a. Individual Block Unlock Instruction (SPI Mode)

Figure 53b. Individual Block Unlock Instruction (QPI Mode)

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8.2.40 Read Block/Sector Lock (3Dh)

To read out the lock bit value of a specific block or sector as illustrated in Figure 4d, a Read Block/Sector Lock command must be issued by driving /CS low, shifting the instruction code “3Dh” into the Data Input (DI) pin on the rising edge of CLK, followed by a 24-bit address. The Block/Sector Lock bit value will be shifted out on the DO pin at the falling edge of CLK with most significant bit (MSB) first as shown in Figure 54. If the least significant bit (LSB) is 1, the corresponding block/sector is locked; if LSB=0, the corresponding block/sector is unlocked, Erase/Program operation can be performed.

Figure 54a. Read Block Lock Instruction (SPI Mode)

Figure 54b. Read Block Lock Instruction (QPI Mode)

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8.2.41 Global Block/Sector Lock (7Eh)

All Block/Sector Lock bits can be set to 1 by the Global Block/Sector Lock instruction. The command must be issued by driving /CS low, shifting the instruction code “7Eh” into the Data Input (DI) pin on the rising edge of CLK, and then driving /CS high. A Write Enable instruction must be executed before the device will accept the Global Block/Sector Lock Instruction (Status Register bit WEL= 1).

Figure 55. Global Block Lock Instruction for SPI Mode (left) or QPI Mode (right)

8.2.42 Global Block/Sector Unlock (98h)

All Block/Sector Lock bits can be set to 0 by the Global Block/Sector Unlock instruction. The command must be issued by driving /CS low, shifting the instruction code “98h” into the Data Input (DI) pin on the rising edge of CLK, and then driving /CS high. A Write Enable instruction must be executed before the device will accept the Global Block/Sector Unlock Instruction (Status Register bit WEL= 1).

Figure 56. Global Block Unlock Instruction for SPI Mode (left) or QPI Mode (right)

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8.2.43 Enable Reset (66h) and Reset Device (99h)

Because of the small package and the limitation on the number of pins, the W25Q32FV provide a software Reset instruction instead of a dedicated RESET pin. Once the Reset instruction is accepted, any on-going internal operations will be terminated and the device will return to its default power-on state and lose all the current volatile settings, such as Volatile Status Register bits, Write Enable Latch (WEL) status, Program/Erase Suspend status, Read parameter setting (P7-P0), Continuous Read Mode bit setting (M7-M0) and Wrap Bit setting (W6-W4).

“Enable Reset (66h)” and “Reset (99h)” instructions can be issued in either SPI mode or QPI mode. To avoid accidental reset, both instructions must be issued in sequence. Any other commands other than “Reset (99h)” after the “Enable Reset (66h)” command will disable the “Reset Enable” state. A new sequence of “Enable Reset (66h)” and “Reset (99h)” is needed to reset the device. Once the Reset command is accepted by the device, the device will take approximately tRST=30us to reset. During this period, no command will be accepted.

Data corruption may happen if there is an on-going or suspended internal Erase or Program operation when Reset command sequence is accepted by the device. It is recommended to check the BUSY bit and the SUS bit in Status Register before issuing the Reset command sequence.

/CS

Mode 3 0 1 2 3 4 5 6 7

CLK

Mode 0

Instruction (66h)

(IO0)

Mode 3 0 1 2 3 4 5 6 7 Mode 0

Instruction (99h)

Mode 3 Mode 0

(IO1)

High Impedance

Figure 57a. Enable Reset and Reset Instruction Sequence (SPI Mode)

/CS

CLK

Mode 3 0 1 Mode 0

Instruction

66h

Mode 3 0 1 Mode 0

Instruction

99h

Mode 3 Mode 0

Figure 57b. Enable Reset and Reset Instruction Sequence (QPI Mode)

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Page 81

9. ELECTRICAL CHARACTERISTICS

W25Q32FV

9.1 Absolute Maximum Ratings

(1)(2)

PARAMETERS SYMBOL CONDITIONS RANGE UNIT

Supply Voltage VCC –0.6 to 4.6 V Voltage Applied to Any Pin VIO Relative to Ground –0.6 to VCC+0.4 V

Transient Voltage on any Pin V Storage Temperature T

Lead Temperature T Electrostatic Discharge Voltage V

Notes:

1.This device has been designed and tested for the specified operation ranges. Proper operation outside of these levels is not

guaranteed. Exposure to absolute maximum ratings may affect device reliability. Exposure beyond absolute maximum ratings may cause permanent damage.

2.JEDEC Std JESD22-A114A (C1=100pF, R1=1500 ohms, R2=500 ohms).

3.Compliant with JEDEC Standard J-STD-20C for small body Sn-Pb or Pb-free (Green) assembly and the European directive on

restrictions on hazardous substances (RoHS) 2002/95/EU.

IOT

STG

–65 to +150 °C

LEAD

(2)

ESD

<20nS Transient Relative to Ground

(3)

See Note

Human Body Model

–2.0V to VCC+2.0V V

–2000 to +2000 V

(3)

°C

9.2 Operating Ranges

PARAMETER SYMBOL CONDITIONS

Supply Voltage VCC Ambient Temperature,

Operating

Note:

1.VCC voltage during Read can operate across the min and max range but should not exceed ±10% of the programming

(erase/write) voltage.

(1)

FR = 104MHz, fR = 50MHz 2.7 3.6 V

Industrial

SPEC

UNIT

MIN MAX

–40 +85 °C

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W25Q32FV

9.3 Power-Up Power-Down Timing and Requirements

(1)

SPEC

PARAMETER SYMBOL

MIN MAX

VCC (min) to /CS Low t Time Delay Before Write Instruction t

VSL

20 µs

PUW

5 ms

Write Inhibit Threshold Voltage VWI 1.0 2.0 V

Note

1. These parameters are characterized only.

VCC

(max)

(min)

Reset

State

Program, Erase and Write Instructions are ignored /CS must track VCC

tVSL

tPUW

Read Instructions

Allowed

Device is fully

Accessible

UNIT

Time

Figure 58a. Power-up Timing and Voltage Levels

/CS must track VCC

during VCC Ramp Up/Down

VCC

/CS

Time

Figure 58b. Power-up, Power-Down Requirement

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Page 83

9.4 DC Electrical Characteristics

W25Q32FV

PARAMETER SYMBOL CONDITIONS

SPEC

UNIT

MIN TYP MAX

Input Capacitance C Output Capacitance Cout Input Leakage ILI I/O Leakage ILO

Standby Current ICC1

Power-down Current ICC2 Current Read Data /

Dual /Quad 50MHz Current Read Data /

Dual /Quad 80MHz Current Read Data /

Dual Output Read/Quad Output Read 104MHz

Current Write Status Register

Current Page Program ICC5 /CS = VCC Current Sector/Block

Erase Current Chip Erase ICC7 /CS = VCC Input Low Voltage VIL Input High Voltage VIH Output Low Voltage VOL IOL = 100 µA Output High Voltage VOH IOH = –100 µA

Notes:

1. Tested on sample basis and specified through design and characterization data. TA = 25° C, VCC = 3.0V, 25% driver strength

2. Checker Board Pattern.

(1)

/CS = VCC, VIN = GND or VCC

(2)

ICC3

(2)

ICC3

(2)

ICC3

ICC4 /CS = VCC

ICC6 /CS = VCC

C = 0.1 VCC / 0.9 VCC DO = Open

IN OUT

= 0V

6 pF 8 pF ±2 µA ±2 µA

10 50 µA

1 20 µA

15 mA

18 mA

20 mA

8 12 mA 20 25 mA 20 25 mA 20 25 mA

–0.5 VCC x 0.3

VCC x 0.7

VCC + 0.4

V V

0.2 V

VCC – 0.2

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Page 84

W25Q32FV

9.5 AC Measurement Conditions

PARAMETER SYMBOL

(1)

SPEC

UNIT

MIN MAX

Load Capacitance CL 30 pF Input Rise and Fall Times TR, TF 5 ns Input Pulse Voltages VIN 0.1 VCC to 0.9 VCC V Input Timing Reference Voltages

0.3 VCC to 0.7 VCC V

Output Timing Reference Voltages OUT 0.5 VCC to 0.5 VCC V

Note:

1. Output Hi-Z is defined as the point where data out is no longer driven.

Input Levels

0.9 VCC

0.1 VCC

Input and Output

Timing Reference Levels

0.5 VCC

Figure 59. AC Measurement I/O Waveform

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Page 85

W25Q32FV

except

Read data instructions

(03h)

9.6 AC Electrical Characteristics

DESCRIPTION SYMBOL ALT

(6)

Clock frequency for all other instructions

2.7V-3.6V VCC & Industrial Temperature.

FR fC1 D.C.

Clock frequency for Read Data instruction (03h) fR fC2 D.C. Clock High, Low Time

for all instructions except for Read Data (03h) Clock High, Low Time

for Read Data (03h) instruction Clock Rise Time peak to peak t Clock Fall Time peak to peak t /CS Active Setup Time relative to CLK t /CS Not Active Hold Time relative to CLK t Data In Setup Time t Data In Hold Time t

CLH

(1)

CLL

CRLH

(1)

CRLL

(2)

CLCH

(2)

CHCL

SLCH

CHSL

5 ns

DVCH

CHDX

0.1 V/ns

CSS

DSU

SPEC

UNIT

MIN TYP MAX

104 MHz

50 MHz

4 ns

8 ns

5 ns

2 ns

3 ns /CS Active Hold Time relative to CLK t /CS Not Active Setup Time relative to CLK t /CS Deselect Time t Output Disable Time t Clock Low to Output Valid t Output Hold Time t /HOLD Active Setup Time relative to CLK t /HOLD Active Hold Time relative to CLK t /HOLD Not Active Setup Time relative to CLK t /HOLD Not Active Hold Time relative to CLK t

CHSH

3 ns

SHCH

3 ns

SHSL

CSH

(2)

SHQZ

DIS

CLQV

tV 7 ns

CLQX

HLCH

5 ns

CHHH

5 ns

HHCH

5 ns

CHHL

5 ns

Continued – next page AC Electrical Characteristics (

50 ns

7 ns

2 ns

cont’d)

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W25Q32FV

W25Q

FVxxI

W25Q

FVxxI

AC Electrical Characteristics (cont’d)

SPEC

DESCRIPTION SYMBOL ALT

MIN TYP MAX

/HOLD to Output Low-Z t /HOLD to Output High-Z t Write Protect Setup Time Before /CS Low t Write Protect Hold Time After /CS High t /CS High to Power-down Mode t

/CS High to Standby Mode without ID Read /CS High to Standby Mode with ID Read t

/CS High to next Instruction after Suspend t /CS High to next Instruction after Reset t /RESET pin Low period to reset the device t

(2)

HHQX

tLZ 7 ns

(2)

HLQZ

tHZ 12 ns

(3)

WHSL

20 ns

(3)

SHWL

100 ns

(2)

3 µs

RES

SUS

RST

SUS

(2)

(5)

(2)

3 µs

1.8 µs

20 µs

30 µs

1 µs Write Status Register Time tW 10 15 ms Byte Program Time (First Byte) t Additional Byte Program Time (After First Byte) t

(4)

30 50 µs

BP1

(4)

2.5 12 µs

BP2

UNIT

Page Program Time tPP 0.7 3 ms

W25Q32FVxxIG

Sector Erase Time (4KB)

W25Q32FVxxIQ

Block Erase Time (32KB) t Block Erase Time (64KB) t

tSE

120 1,600 ms

150 2,000 ms

100

400 ms

Chip Erase Time tCE 10 50 s

Notes:

1.Clock high + Clock low must be less than or equal to 1/fC.

2.Value guaranteed by design and/or characterization, not 100% tested in production.

3.Only applicable as a constraint for a Write Status Register instruction when SRP[1:0]=(0,1).

4.For multiple bytes after first byte within a page, t of bytes programmed.

5.It’s possible to reset the device with shorter t reliable operation.

6.4-bytes address alignment for QPI/Quad Read

BPN

= t

BP1

+ t

BP2

* N (typical) and t

RESET

(as short as a few hundred ns), a 1us minimum is recommended to ensure

BPN

= t

BP1

+ t

BP2

* N (max), where N = number

- 85 -

Page 87

9.7 Serial Output Timing

/CS

CLK

tCLQV

tCLQX

MSB OUT

output

tCLQX

9.8 Serial Input Timing

W25Q32FV

tCLH

tCLQV tSHQZtCLL

LSB OUT

/CS

tCHSL

CLK

tDVCH tCHDX

input

9.9 /HOLD Timing

/CS

CLK

/HOLD

output

input

9.10 /WP Timing

/CS

tWHSL tSHWL

/WP

tSLCH

MSB IN

tCHHL

tCLCH tCHCL

LSB IN

tHLCH

tCHHH

tHLQZ tHHQX

tHHCH

tSHSL tSHCHtCHSH

CLK

input

Write Status Register is allowed Write Status Register is not allowed

Publication Release Date: Sept 16,, 2013

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Page 88

10. PACKAGE SPECIFICATIONS

A 1.75 1.95 2.16 0.069 0.077 0.

085

A2 1.70 1.80 1.91 0.067 0.071 0.075

D 5.18 5.28 5.38 0.204 0.208 0.212

E1 5.13 5.23 5.33 0.202 0.206 0.210

L 0.50 0.65 0.80 0.020 0.026 0.031

10.1 8-Pin SOIC 208-mil (Package Code SS)

W25Q32FV

Millimeters Inches

Symbol

Min Nom Max Min Nom Max

A1 0.05 0.15 0.25 0.002 0.006 0.010

b 0.35 0.42 0.48 0.014 0.017 0.019 C 0.19 0.20 0.25 0.007 0.008 0.010

D1 5.13 5.23 5.33 0.202 0.206 0.210

E 5.18 5.28 5.38 0.204 0.208 0.212

e 1.27 BSC 0.050 BSC H 7.70 7.90 8.10 0.303 0.311 0.319

y --- --- 0.10 --- --- 0.004

θ 0° --- 8° 0° --- 8°

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Page 89

10.2 8-Pin VSOP 208-mil (Package Code ST)

A1 0.05 0.10 0.15 0.002

0.004

0.006

c 0.

127 REF 0.00

5 REF

5.18 5.28 5.38 0.

204 0.208 0.212

L 0.50 0.65 0.80

0.020

0.026 0.031

― ― 0.10

― ―

0.004

W25Q32FV

Millimeters Inches

Symbol

Min Nom Max Min Nom Max

A ― ― 1.00 ― ― 0.039

A2 0.75 0.80 0.85 0.030 0.031 0.033

b 0.35 0.42 0.48 0.014 0.017 0.019

D 5.18 5.28 5.38 0.204 0.208 0.212 E 7.70 7.90 8.10 0.303 0.311 0.319

e ― 1.27 ― ― 0.050 ―

θ 0° ― 8° 0° ― 8°

Publication Release Date: Sept 16,, 2013

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Page 90

10.3 8-Pad WSON 6x5-mm (Package Code ZP)

W25Q32FV

Symbol

Millimeters Inches

Min Nom Max Min Nom Max

A 0.70 0.75 0.80 0.028 0.030 0.031

A1 0.00 0.02 0.05 0.000 0.001 0.002

b 0.35 0.40 0.48 0.014 0.016 0.019 C D 5.90 6.00 6.10 0.232 0.236 0.240

D2 3.35 3.40 3.45 0.132 0.134 0.136

L 0.55 0.60 0.65 0.022 0.024 0.026

y 0.00 --- 0.075 0.000 --- 0.003

--- 0.20 REF

4.90 5.00 5.10 0.193 0.197 0.201

4.25 4.30 4.35 0.167 0.169 0.171

1.27 BSC 0.050 BSC

--- --- 0.008 REF

---

Note:

1.The metal pad area on the bottom center of the package is not connected to any internal electrical signals. It can be left floating or connected to the device ground (GND pin). Avoid placement of exposed PCB vias under the pad.

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Page 91

10.4 8-Pad WSON 8x6-mm (Package Code ZE)

Symbol

A 0.70 0.75 0.80 0.028 0.030 0.031

A1 0.00 0.02 0.05 0.000 0.001 0.002

b 0.35 0.40 0.48 0.014 0.016 0.019 C --- 0.20 REF --- --- 0.008 REF D 7.90 8.00 8.10 0.311 0.315 0.319

D2 3.35 3.40 3.45 0.132 0.134 0.136

E 5.90 6.00 6.10 0.232 0.236 0.240

E2 4.25 4.30 4.35 0.167 0.169 0.171

e --- 1.27 --- --- 0.050 ---

L 0.45 0.50 0.55 0.018 0.020 0.022

y 0.00 --- 0.050 0.000 --- 0.002

Min Nom Max Min Nom Max

Millimeters Inches

W25Q32FV

---

Note:

Publication Release Date: Sept 16,, 2013

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Page 92

10.5 16-Pin SOIC 300-mil (Package Code SF)

W25Q32FV

Symbol

A 2.36 2.49 2.64 0.093 0.098 0.104 A1 0.10 --- 0.30 0.004 --- 0.012 A2 --- 2.31 --- --- 0.091 ---

b 0.33 0.41 0.51 0.013 0.016 0.020

C 0.18 0.23 0.28 0.007 0.009 0.011 D 10.08 10.31 10.49 0.397 0.406 0.413

E 10.01 10.31 10.64 0.394 0.406 0.419 E1 7.39 7.49 7.59 0.291 0.295 0.299

e 1.27 BSC 0.050 BSC

L 0.38 0.81 1.27 0.015 0.032 0.050

y --- --- 0.076 --- --- 0.003

θ 0° --- 8° 0° --- 8°

Min Nom Max Min Nom Max

Millimeters Inches

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Page 93

10.6 8-Pin PDIP 300-mil (Package Code DA)

A2 3.18 3.30 3.43 0.125 0.130 0.135

D 9.02 9.27 10.16 0.355 0.365 0.400

E 7.62 BSC

0.300 BSC

θ° 0° 7° 15° 0° 7° 15°

d --- 2.54 --- --- 0.100 ---

W25Q32FV

Millimeters Inches

Symbol

Min Nom Max Min Nom Max

A --- --- 5.33 --- --- 0.210

A1 0.38 --- --- 0.015 --- ---

E1 6.22 6.35 6.48 0.245 0.250 0.255

L 2.92 3.30 3.81 0.115 0.130 0.150

eB 8.51 9.02 9.53 0.335 0.355 0.375

w --- 1.52 --- --- 0.060 ---

p --- 0.46 --- --- 0.018 ---

Publication Release Date: Sept 16,, 2013

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Page 94

10.7 24-Ball TFBGA 8x6-mm (Package Code TB, 5x5-1 ball array)

W25Q32FV

Symbol

A --- --- 1.20 --- --- 0.047 A1 0.25 0.30 0.35 0.010 0.012 0.014 A2 --- 0.85 --- --- 0.033 ---

b 0.35 0.40 0.45 0.014 0.016 0.018

D 7.90 8.00 8.10 0.311 0.315 0.319 D1 4.00 BSC 0.157 BSC

E 5.90 6.00 6.10 0.232 0.236 0.240 E1 4.00 BSC 0.157 BSC SE 1.00 TYP 0.039 TYP SD 1.00 TYP 0.039 TYP

e 1.00 BSC 0.039 BSC

Min Nom Max Min Nom Max

Note: Ball land: 0.45mm. Ball Opening: 0.35mm PCB ball land suggested <= 0.35mm

Millimeters Inches

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Page 95

10.8 24-Ball TFBGA 8x6-mm (Package Code TC, 6x4 ball array)

W25Q32FV

Symbol

A --- --- 1.20 --- --- 0.047 A1 0.25 0.30 0.35 0.010 0.012 0.014

b 0.35 0.40 0.45 0.014 0.016 0.018

D 7.95 8.00 8.05 0.313 0.315 0.317 D1 5.00 BSC 0.197 BSC

E 5.95 6.00 6.05 0.234 0.236 0.238 E1 3.00 BSC 0.118 BSC

e 1.00 BSC 0.039 BSC

Min Nom Max Min Nom Max

Note: Ball land: 0.45mm. Ball Opening: 0.35mm PCB ball land suggested <= 0.35mm

Millimeters Inches

Publication Release Date: Sept 16,, 2013

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Page 96

11. ORDERING INFORMATION

25Q

32F

V xx

W25Q32FV

(1)

W = Winbond

25Q = SpiFlash Serial Flash Memory with 4KB sectors, Dual/Quad I/O

32F = 32M-bit

= 2.7V to 3.6V

SS = 8-pin SOIC 208-mil ST = 8-pin VSOP 208-mil SF = 16-pin SOIC 300-mil DA = 8-pin PDIP 300-mil ZP = WSON8 6x5-mm ZE = WSON8 8x6-mm TB = TFBGA 8x6-mm (5x5-1 ball array) TC = TFBGA 8x6-mm (6x4 ball array)

I = Industrial (-40°C to +85°C)

(2)

G = F = Green Package with Fast Sector Erase time (tSE) P Q = Green Package with QE=1 in Status Register-2

Notes:

1.The “W” prefix is not included on the part marking.

2.Only the 2nd letter is used for the part marking; WSON package type ZP & ZE are not used for the part marking.

3.Standard bulk shipments are in Tube (shape E). Please specify alternate packing method, such as Tape and Reel (shape T) or Tray (shape S), when placing orders.

4.For shipments with OTP feature enabled, please specify when placing orders.

Green Package (Lead-free, RoHS Compliant, Halogen-free (TBBA), Antimony-Oxide-free Sb2O3)

= Green Package with Status Register Power-Down & OTP enabled

(3,4)

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Page 97

W25Q32FV

11.1 Valid Part Numbers and Top Side Marking

The following table provides the valid part numbers for the W25Q32FV SpiFlash Memory. Please contact Winbond for specific availability by density and package type. Winbond SpiFlash memories use a 12-digit Product Number for ordering. However, due to limited space, the Top Side Marking on all packages uses an abbreviated 10-digit number.

PACKAGE TYPE

DENSITY PRODUCT NUMBER TOP SIDE MARKING

W25Q32FVSSIG

SOIC-8 208-mil

32M-bit

W25Q32FVSSIP

W25Q32FVSSIQ

W25Q32FVSSIF

(1)

VSOP-8 208-mil

32M-bit

W25Q32FVSTIG W25Q32FVSTIP W25Q32FVSTIF W25Q32FVSFIG

SOIC-16 300-mil

32M-bit

W25Q32FVSFIP W25Q32FVSFIQ W25Q32FVSFIF

W25Q32FVDAIG

PDIP-8 300-mil

32M-bit

W25Q32FVDAIP

W25Q32FVDAIQ

W25Q32FVDAIF W25Q32FVZPIG

WSON-8 6x5-mm

32M-bit

W25Q32FVZPIP W25Q32FVZPIQ W25Q32FVZPIF

WSON-8 8x6-mm

(1)

TFBGA-24 8x6-mm

(5x5 Ball Array)

(1)

TFBGA-24 8x6-mm

(6x4 Ball Array)

Note:

1.These package types are special order, please contact Winbond for more information.

32M-bit

W25Q32FVZEIG W25Q32FVZEIP W25Q32FVZEIF

W25Q32FVTBIG W25Q32FVTBIP W25Q32FVTBIF

W25Q32FVTCIG

W25Q32FVTCIP W25Q32FVTCIF

25Q32FVSIG 25Q32FVSIP 25Q32FVSIQ

25Q32FVSIF

25Q32FVTIG

25Q32FVTIP 25Q32FVTIF

25Q32FVFIG

25Q32FVFIP

25Q32FVFIQ

25Q32FVFIF 25Q32FVAIG 25Q32FVAIP 25Q32FVAIQ

25Q32FVAIF

25Q32FVIG 25Q32FVIP 25Q32FVIQ

25Q32FVIF 25Q32FVIG 25Q32FVIP

25Q32FVIF

25Q32FVBIG 25Q32FVBIP

25Q32FVBIF

25Q32FVCIG 25Q32FVCIP 25Q32FVCIF

Publication Release Date: Sept 16,, 2013

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Page 98

12. REVISION HISTORY

W25Q32FV

VERSION

A 09/27/2011

B 04/13/2012

C 07/20/2012

D 10/15/2012

D1 01/25/2013

E 03/15/2013

E1 03/29/2013

F 04/13/2013

G 04/29/2013

H 09/16/2013

DATE PAGE DESCRIPTION

New Create Preliminary

10, 14, 84

66 84 89

94-95

All

19, 84

10, 15, 80

95 80

91 95

8, 15 Added rest pin description of SOIC-16 300-mil

103,104

94,95

84 Modified the tSE of W25Q32FVxxIQ & IF 18

19 80

89,90 63-64 80-85

Updated RESET descriptions Referred to SFDP definition application note Updated Erase Time Updated WSON metal pad size Added Q order option

Removed preliminary designator Updated default driver strength setting Added power-down requirement Updated PDIP part number and marking

Updated power-up timing parameters Updated PDIP dimensions Updated ordering part number

Modified the tSE of W25Q32FVxxIQ Added the tSE of W25Q32FVxxIF

Added W25Q32FVxxIF into order information

Added Quad Enable default description Added DRV default setting value Modified Supply Voltage Updated note for metal pad for WSON, USON

Modified the description of 92h, 94h Modified the description of DC/AC table

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Page 99

W25Q32FV

Trademarks

Winbond and SpiFlash are trademarks of Winbond Electronics Corporation. All other marks are the property of their respective owner.

Important Notice

Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Furthermore, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales.

Information in this document is provided solely in connection with Winbond products. Winbond reserves the right to make changes, corrections, modifications or improvements to this document and the products and services described herein at any time, without notice.

Publication Release Date: Sept 16,, 2013

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Page 100

Datasheet W25Q32FV Datasheet (Winbond) [ru]

Specifications and Main Features

Frequently Asked Questions

User Manual