Datasheet W25P022AF-6, W25P022AD-7, W25P022AD-6, W25P022AF-7 Datasheet (Winbond Electronics)

W25P022A

LBO

CE3

CE3

ZZ

64K × 32 BURST PIPELINED HIGH-SPEED

CMOS STATIC RAM

GENERAL DESCRIPTION

The W25P022A is a high-speed, low-power, synchronous-burst pipelined CMOS static RAM
organized as 65,536 × 32 bits that operates on a single 3.3-volt power supply. A built-in two-bit burst
address counter supports both Pentium burst mode and linear burst mode. The mode to be

executed is controlled by the
the FT pin. A snooze mode reduces power dissipation.
The W25P022A supports both 2T/2T mode and 2T/1T mode, which can be selected by pin 42. The

default mode is 2T/1T, with pin 42 low. To switch to 2T/2T mode, bias pin 42 to VDDQ. The state of
pin 42 should not be changed after power up. The 2T/2T mode will sustain one cycle of valid data

output in a burst read cycle when the device is deselected by CE2/
1-1-1-1 in a two-bank, back-to-back burst read cycle. On the other hand, the 2T/1T mode disables

data output within one cycle in a burst read cycle when the device is deselected by CE2/
mode, the device supports only 3-1-1-1-2-1-1-1 in a two-bank, back-to-back burst read cycle.

FEATURES

• Synchronous operation

• High-speed access time: 6/7 nS (max.)

• Single +3.3V power supply

• Individual byte write capability

• 3.3V LVTTL compatible I/O

• Clock-controlled and registered input

• Asynchronous output enable

pin. Pipelining or non-pipelining of the data outputs is controlled by

. This mode supports 3-1-1-1-

. In this

• Pipelined/non-pipelined data output capability

• Supports snooze mode (low-power state)

• Internal burst counter supports Intel burst mode

& linear burst mode

• Supports both 2T/2T & 2T/1T mode

• Packaged in 100-pin QFP or TQFP

BLOCK DIAGRAM

A(15:0)

CLK

CE(3:1)

GW

BWE

BW(4:1)

ADSC
ADSP

ADV
LBO

INPUT

REGISTER

CONTROL

LOGIC

OE

FT

MS

REGISTE

R

64K X 32

CORE

ARRAY

DATA I/O

REGISTER

I/O(32:1)

Publication Release Date: September 1996

- 1 - Revision A1

PIN CONFIGURATION

NC

I/O 17
I/O 18

VDDQ

VSSQ
I/O 19
I/O 20
I/O 21
I/O 22
VSSQ

VDDQ

I/O 23
I/O 24

/FT

VDD

NC

VSS
I/O 25
I/O 26

VDDQ

VSSQ
I/O 27
I/O 28
I/O 29
I/O 30
VSSQ

VDDQ

I/O 31
I/O 32

NC

/

/

/

/

/

/

C

C

A6A

1

0
0

2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29

313233343536373839404142434445464748495

30

B

E

E

W

7

1

2

4

/

B

B

B

C

V

V

W

W

W

3

2

1

C

E

D

S

L

3

D

S

K

100-pin

TQFP MO-136

QFP MO-108

/
G
W

/

/

A

A

B

/

D

D

W

O

S

S

E

E

C

P

/
A
DVA8A

W25P022A

9

818283848586878889909192939495969798991

80

NC
I/O 16

79
78

I/O 15
VDDQ

77

VSSQ

76
75

I/O 14

74

I/O 13
I/O 12

73
72

I/O 11
VSSQ

71

VDDQ

70
69

I/O 10

68

I/O 9

67

VSS
NC

66

VDD

65

ZZ

64
63

I/O 8
I/O 7

62
61

VDDQ
VSSQ

60

I/O 6

59
58

I/O 5
I/O 4

57
56

I/O 3
VSSQ

55
54

VDDQ
I/O 2

53

I/O 1

52
51

0

NC

/

A5A4A3A2A1A0NCNCV
L
B
O

S
S

- 2 -

V

A

A

A

A

A

N

N

D

1

1

CMS

D

0

1

A

1

1

1

C

1

2

3

4

5

PIN DESCRIPTION

CE1

CE3

GW

BWE

BW1

BW4

BWE

OE

ADV

ADSC

ADSP

FT

LBO

SYMBOL TYPE DESCRIPTION

W25P022A

A0−A15

I/O1−I/O32

CLK Input, Clock Processor Host Bus Clock

, CE2,

−

ZZ Input, Asynchronous Snooze Pin for Low-power State, internally pulled low

Input, Synchronous Host Address
I/O, Synchronous Data Inputs/Outputs

Input, Synchronous Chip Enables
Input, Synchronous Global Write
Input, Synchronous Byte Write Enable from Cache Controller
Input, Synchronous

Input, Asynchronous Output Enable Input
Input, Synchronous Internal Burst Address Counter Advance
Input, Synchronous Address Status from chip set
Input, Synchronous Address Status from CPU

Input, Static Connected to VSSQ: Device operates in flow-through

Input, Static Lower Address Burst Order

Host Bus Byte Enables used with

(non-pipelined) mode.
Connected to VDDQ or unconnected: Device operates

in piplined mode.

Connected to VSSQ: Device operates in linear mode.
Connected to VDDQ or unconnected: Device is in non­linear mode.

MS Input, Static Mode Select for 2T/2T or 2T/1T

When unconnected or pulled low, device is in 2T/1T
mode; if pulled high (VDDQ), device enters 2T/2T

mode.
VDDQ I/O Power Supply
VSSQ I/O Ground

VDD Power Supply
VSS Ground

NC No Connection

Publication Release Date: September 1996

- 3 - Revision A1

TRUTH TABLE

W25P022A

CYCLE

Unselected No 1 X X X 0 X X Hi-Z X
Unselected No 0 X 1 0 X X X Hi-Z X
Unselected No 0 0 X 0 X X X Hi-Z X
Unselected No 0 X 1 1 0 X X Hi-Z X
Unselected No 0 0 X 1 0 X X Hi-Z X
Begin Read External 0 1 0 0 X X X Hi-Z X
Begin Read External 0 1 0 1 0 X X Hi-Z Read
Continue Read Next X X X 1 1 0 1 Hi-Z Read
Continue Read Next X X X 1 1 0 0 D-Out Read
Continue Read Next 1 X X X 1 0 1 Hi-Z Read
Continue Read Next 1 X X X 1 0 0 D-Out Read
Suspend Read Current X X X 1 1 1 1 Hi-Z Read
Suspend Read Current X X X 1 1 1 0 D-Out Read
Suspend Read Current 1 X X X 1 1 1 Hi-Z Read
Suspend Read Current 1 X X X 1 1 0 D-Out Read
Begin Write Current X X X 1 1 1 X Hi-Z Write
Begin Write Current 1 X X X 1 1 X Hi-Z Write
Begin Write External 0 1 0 1 0 X X Hi-Z Write
Continue Write Next X X X 1 1 0 X Hi-Z Write
Continue Write Next 1 X X X 1 0 X Hi-Z Write
Suspend Write Current X X X 1 1 1 X Hi-Z Write
Suspend Write Current 1 X X X 1 1 X Hi-Z Write

Notes:

1. For a detailed definition of read/write, see the Write Table below.

2. An "X" means don't care, "1" means logic high, and "0" means logic low.

ADDRESS

USED

CE1

CE2

CE3 ADSP ADSC ADV

OE

DATA WRITE*

3. The OE pin enables the data output but is not synchronous with the clock. All signals of the SRAM are sampled synchronous
to the bus clock except for the OE pin.

4. On a write cycle that follows a read cycle, OE must be inactive prior to the start of the write cycle to allow write data to set up
the SRAM. OE must also disable the output buffer prior to the end of a write cycle to ensure the SRAM data hold timings

are met.

- 4 -

W25P022A

LBO

ADSP

ADSC

ADV

BWE

GW

FUNCTIONAL DESCRIPTION

The W25P022A is a synchronous-burst pipelined SRAM designed for use in high-end personal
computers. It supports two burst address sequences for Intel systems and linear mode, which can

be controlled by the
counter is incremented whenever

pipelined mode if necessary.

Burst Address Sequence

External Start Address 00 01 10 11 00 01 10 11
Second Address 01 00 11 10 01 10 11 00
Third Address 10 11 00 01 10 11 00 01
Fourth Address 11 10 01 00 11 00 01 10

pin. The burst cycles are initiated by

is sampled low. The device can also be switched to non-

INTEL SYSTEM (LBO = VDDQ) LINEAR MODE (LBO = VSSQ)

A[1:0] A[1:0] A[1:0] A[1:0] A[1:0] A[1:0] A[1:0] A[1:0]

or

and the burst

The device supports several types of write mode operations.
byte writes. The BE[7:0] signals can be directly connected to the SRAM BW[4:1]. The

used to override the byte enable signals and allows the cache controller to write all bytes to the
SRAM, no matter what the byte write enable signals are. The various write modes are indicated in the
Write Table below. Note that in pipelined mode, the byte write enable signals are not latched by the
SRAM with addresses but with data. In pipelined mode, the cache controller must ensure the SRAM
latches both data and valid byte enable signals from the processor.

and BW[4:1] support individual

signal is

WRITE TABLE

READ/WRITE FUNCTION GW BWE BW4 BW3 BW2 BW1

Read 1 1 X X X X
Read 1 0 1 1 1 1
Write byte 1 I/O1−I/O8
Write byte 2 I/O9−I/O16
Write byte 2, byte 1 1 0 1 1 0 0
Write byte 3 I/O17−I/O24
Write byte 3, byte 1 1 0 1 0 1 0
Write byte 3, byte 2 1 0 1 0 0 1
Write byte 3, byte 2, byte 1 1 0 1 0 0 0
Write byte 4 I/O25−I/O32
Write byte 4, byte 1 1 0 0 1 1 0

1 0 1 1 1 0
1 0 1 1 0 1

1 0 1 0 1 1

1 0 0 1 1 1

Publication Release Date: September 1996

- 5 - Revision A1

W25P022A

Write Table, continued

READ/WRITE FUNCTION GW BWE BW4 BW3 BW2 BW1

Write byte 4, byte 2 1 0 0 1 0 1
Write byte 4, byte 2, byte 1 1 0 0 1 0 0
Write byte 4, byte 3 1 0 0 0 1 1
Write byte 4, byte 3, byte 1 1 0 0 0 1 0
Write byte 4, byte 3, byte 2 1 0 0 0 0 1
Write all bytes I/O1−I/O32
Write all bytes I/O1−I/O32

The ZZ state is a low-power state in which the device consumes less power than in the unselected
mode. Enabling the ZZ pin for a fixed period of time will force the SRAM into the ZZ state. Pulling the
ZZ pin low for a set period of time will wake up the SRAM again. While the SRAM is in ZZ mode, data
retention is guaranteed, but the chip will not monitor any input signal except for the ZZ pin. In the
unselected mode, on the other hand, all the input signals are monitored.

1 0 0 0 0 0
0 X X X X X

ABSOLUTE MAXIMUM RATINGS

PARAMETER RATING UNIT

Core Supply Voltage to Vss -0.5 to 4.6 V
I/O Supply Voltage to Vss -0.5 to 4.6 V
Input/Output to VSSQ Potential VSSQ -0.5 to VDDQ +0.5 V
Allowable Power Dissipation 1.0 W
Storage Temperaure -65 to 150
Operating Temperature 0 to +70

Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability

of the device.

°C
°C

- 6 -

OPERATING CHARACTERISTICS

(VDD/VDDQ = 3.15V to 3.6V, VSS/VSSQ = 0V, TA = 0 to 70° C)

W25P022A

PARAMETER SYM. TEST CONDITIONS MIN. TYP

.

Input Low Voltage VIL - -0.5 - +0.8 V
Input High Voltage VIH - +2.0 - VDD +0.3 V
Input Leakage Current ILI VIN = VSSQ to VDDQ -10 - +10
Output Leakage

Current

Output Low Voltage VOL IOL = +8.0 mA - - 0.4 V
Output High Voltage VOH IOH = -4.0 mA 2.4 - - V
Operating Current IDD
Standby Current ISB Unselected mode defined in

ZZ Mode Current IZZ

Note: Typical characteristics are measured at VDD = 3.3V, TA = 25° C.

ILO VI/O = VSSQ to VDDQ, and data

I/O pins in high-Z state defined
in truth table

TCYC ≥ min., I/O = 0 mA

truth table, VIN, VIO = VIH
(min.) /VIL (max.) TCYC ≥ min.

ZZ mode, TCYC ≥ min.

-10 - + 10

- - 250 mA

- - 80 mA

- - 5 mA

MAX. UNIT

CAPACITANCE

(VDD = 3.3V, TA = 25° C, f = 1 MHz)

µA
µA

PARAMETER SYM. CONDITIONS MAX. UNIT

Input Capacitance CIN VIN = 0V 6 pF
Input/Output Capacitance CI/O VOUT = 0V 8 pF

Note: These parameters are sampled but not 100% tested.

AC TEST CONDITIONS

PARAMETER CONDITIONS

Input Pulse Levels 0V to 3V
Input Rise and Fall Times 2 nS
Input and Output Timing Reference Level 1.5V
Output Load CL = 30 pF, IOH/IOL = -4 mA/8 mA

Publication Release Date: September 1996

- 7 - Revision A1

AC TEST LOADS AND WAVEFORM

350 ohm

W25P022A

R1 320 ohm

Including
Jig and
Scope

T

OHZ,TOLZ,

5 pF

measurement)

VL = 1.5V

OUTPUT

RL = 50 ohm

Zo = 50 ohm

3.0V

0V

30 pF

Including
Jig and
Scope

2 nS

90%

10%

(For T

10%

3.3V

OUTPUT

KHZ,

90%

2 nS

T

KLZ,

AC TIMING CHARACTERISTICS

(VDD/VDDQ = 3.15V to 3.6V, VSS/VSSQ = 0V, TA = 0 to 70° C, all timings measured in pipelined mode)

PARAMETER SYM. W25P022A-6 W25P022A-7 UNIT NOTES

MIN. MAX. MIN. MAX.

Add. Setup Time TAS 2.5 - 2.5 - nS
Add. Hold Time TAH 0.5 - 0.5 - nS
Write Data Setup Time TDS 2.5 - 2.5 - nS
Write Data Hold Time TDH 0.5 - 0.5 - nS

ADV Setup Time
ADV Hold Time
ADSP Setup Time
ADSP Hold Time
ADSC Setup Time

ADSC Hold Time
CE1, CE2, CE3 Setup Time
CE1, CE2, CE3 Hold Time

GW , BWE X Setup Time

GW , BWE X Hold Time

TADVS 2.5 - 2.5 - nS
TADVH 0.5 - 0.5 - nS
TADSS 2.5 - 2.5 - nS
TADSH 0.5 - 0.5 - nS
TADCS 2.5 - 2.5 - nS
TADCH 0.5 - 0.5 - nS
TCES 2.5 - 2.5 - nS
TCEH 0.5 - 0.5 - nS
TWS 2.5 - 2.5 - nS
TWH 0.5 - 0.5 - nS

R2

- 8 -

W25P022A

AC Timing Characteristics, continued

PARAMETER SYM. W25P022A-6 W25P022A-7 UNIT NOTES

MIN. MAX. MIN. MAX.

Clock Cycle Time TCYC 13.3 - 15 - nS
Clock High Pulsh Width TKH 5 - 6 - nS
Clock Low Pulse Width TKL 5 - 6 - nS
Clock to Output Valid TKQ - 6 - 7 nS
Clock to Output High-Z TKHZ 2 13.3 2 15 nS 1
Clock to Output Low-Z TKLZ 0 - 0 - nS 1
Clock to Output Invalid TKX 2 - 2 - nS 1
Output Enable to Output Valid TOE - 6 - 7 nS
Output Enable to Output High-Z TOHZ - 6 - 7 nS 1
Output Enable to Output Low-Z TOLZ 0 - 0 - nS 1
Output Enable to Output Invalid TOX 0 - 0 - nS
ZZ Standby Time TZZS - 100 - 100 nS 2
ZZ Recover Time TZZR 100 - 100 - nS 3

Notes:

1. These parameters are sampled but not 100% tested

2. In the ZZ mode, the SRAM will enter a low-power state. In this mode, data retention is guaranteed and the clock is active.

3. ADSC and ADSP should not be accessed for at least 100 nS after chip leaves ZZ mode.

4. Configuration signals LBO and FT are static and should not be changed during operation.

Publication Release Date: September 1996

- 9 - Revision A1

TIMING WAVEFORMS

Read Cycle Timing

W25P022A

CLK

ADSP

ADSC

ADV

A[15:0]

GW

BWE

BW[4:1]

CE1

CE2

CE3

Single Read Burst Read

T

ADSS

T

T

CESTCEH

T

CES T

T

CES T

AS T

RD1

T

ADSH

T

ADVSTADVH

AH

TWS

T

WSTWH

CEH

CEH

TKH

T

ADCH

T

ADCS

RD2

T

WH

CE2 and CE3 only sampled with ADSP or ADSC

T

T

OE

OHZ

Pipelined Read

Unselected

T

CYC

T

KL

ADSP is blocked by CE1 inactive

ADSC initiated read

Suspend Burst

RD3

CE1 masks ADSP

Unselected with CE2

OE

Data-Out

Data-In

High-Z

High-Z

T

OLZ

T

KLZ

TKQ

DON'T CARE
UNDEFINED

T

OX

1a

T

KX

2b

2a

2c

2d

T

KX

3a

T

KHZ

- 10 -

Timing Waveforms, continued

Write Cycle Timing

W25P022A

CLK

ADSP

ADSC

ADV

A[15:0]

GW

BWE

BW[4:1]

CE1

CE2

Single Write Burst Write Unselected

T

ADSS

T

T

ADSH

ADCS

T

ADCH

T

CYC

T

KH

T

KL

ADSP is blocked by CE1 inactive

Write

ADSC initiated write

TADVS TADVH

T

AS T

WR1

ADV must be inactive for ADSP write

AH

WR2

T

WSTWH

GWE allows processor address (and BE=BW)

WR3

to be pipelined during a writeback

TWS TWH

T

T

WH

WS

T

CES

T

CESTCEH

WR1

T

CEH

WR2

CE1 masks ADSP

CE2 and CE3 only sampled with ADSP or ADSC

WR3

Unselected with CE2

CE3

OE

Data-Out

Data-In

T

CES T

High-Z

High-Z

CEH

TDST

DH

1a

DON'T CARE

UNDEFINED

BW[4:1] are applied only to first cycle of WR2
2a 2b 2c

2d 3a

Publication Release Date: September 1996

- 11 - Revision A1

Timing Waveforms, continued

Read/Write Cycle Timing

W25P022A

CLK

ADSP

ADSC

ADV

A[15:0]

GW

BWE

BW[4:1]

CE1

CE2

CE3

Single Read

T

ADSS TADSH

T

T

ADVSTADVH

T

AS T

AH

RD1 WR1

T

TWH

WS

T

WSTWH

T

CESTCEH

T

CESTCEH

T

CES T

CEH

T

OE

ADCS

Single Write

T

CYC

T

KH

T

ADCH

T

KL

ADSC initiated read

Burst Read Unselected

ADSP is blocked by CE1 inactive

Suspend Burst

RD2

TWST

WH

WR1

CE2 and CE3 only sampled with ADSP or ADSC

T

OHZ

CE1 masks ADSP

Unselected with CE3

OE

Data-Out

Data-In

High-Z

High-Z

TOLZ

T

KLZ

T

KQ

DON'T CARE

UNDEFINED

T

OH

1a

T

KHZ

TDSTDH

2a

2b

T

KX

2d2c

T

KHZ

1a

- 12 -

Timing Waveforms, continued

ZZ and RD Timing

W25P022A

CLK

ADSP

ADSC

ADV

A[15:0]

GW

BWE

BW[4:1]

CE1

CE2

CE3

OE

Data-Out

Data-In

Single Read Snooze -with Data Retention

TADSS TADSH

TADVS TADVH

TAS

TAH

RD1

TWS TWH

TWST

TWS T

RD RD

T

TCEH

CES

TCES T

CEH

TCES

TCEH

TOE TOHZ

TOLZ

High-Z

High-Z

T

KLZ

T

KQ

TCYC

TKH

TKL

WH

WH

TOH

1a

TKX

TKHZ

Read

RD2

RD

ZZ

DON'T CARE
UNDEFINED

TZZS

T

ZZR

Publication Release Date: September 1996

- 13 - Revision A1

Timing Waveforms, continued

Dual-bank Burst Read Cycle

W25P022A

CLK

ADSP

ADSC

ADV

A[31:3]

GW

BWE

BW[4:1]

CE1

CE[3:2]
Bank 0

Select Bank 0

Active

Read 1

Select Bank 1

Non­Active

Read 2

CE[3:2]
Bank 1

OE

D[63:0]
Bank 0

D[63:0]
Bank 1

Non­Active

DON'T CARE

UNDEFINED

Active

1a

1b

1d1c

2a

2b

2c

2d

- 14 -

ORDERING INFORMATION

W25P022A

PART NO. ACCESS

TIME (nS)

W25P022AF-6 6 250 80 100-pin QFP

W25P022AF-7 7 250 80 100-pin QFP

W25P022AD-6 6 250 80 100-pin TQFP

W25P022AD-7 7 250 80 100-pin TQFP

Notes:

1. Winbond reserves the right to make changes to its products without prior notice.

2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications
where personal injury might occur as a consequence of product failure.

OPERATING

CURRENT

MAX. (mA)

STANDBY
CURRENT

MAX. (mA)

PACKAGE

Publication Release Date: September 1996

- 15 - Revision A1

PACKAGE DIMENSIONS

100-pin QFP

W25P022A

Seating Plane

100-pin TQFP

e

See Detail F

H

D

e

Dimension in inches

H

D

D

Symbol

A
A

A
b
c
D
E
e
HD
H E

E

H

E

L
L

1

y

Min.

1

0.101

2

0.008

0.004

0.547

0.783

0.020

0.669

0.905

0.025

Nom.

0.107

0.012

0.006 0.15

0.551

0.787

0.026

0.677

0.913

0.031

0.063

θ

Notes:

1. Dimensions D & E do not include interlead flash.

2. Dimension b does not include dambar
protrusion/intrusion.

3. Controlling dimension: Millimeters

4. General appearance spec. should be based

b

C

A

2

A

1

y

D

E

H

E

L

L

1

on final visual inspection spec.

Dimension in inches

Symbol

Min.

Nom.

A
A

1

0.055

0.053

2

A

0.009

0.004

0.547

0.783

0.020

0.626

0.862

E

0.018

1

0.013

0.006 0.15

0.551

0.787

0.026

0.630

0.866

0.024

0.039

b
c
D
E

H D
H
L
L

y

e

θ

Notes:

1. Dimensions D & E do not include interlead flash.

2. Dimension b does not include dambar
protrusion/intrusion.

3. Controlling dimension: Millimeters

4. General appearance spec. should be based

b

on final visual inspection spec.

Dimension in mm

Max. Max.

0.113

0.016

0.008

0.555

0.791

0.032

0.685

0.921

0.037

0.003

Max. Max.

0.057

0.015

0.008

0.555

0.791

0.032

0.634

0.870

0.030

0.003

Nom.

Min.

0.350.250.01 0.014 0.018 0.45

2.57

0.20

0.10

13.90

19.90

0.498

17.00

23.00 23.20 23.40

0.65

070

Dimension in mm

Min.

1035

0.22

0.10

13.90

19.90

0.498

15.90

21.90 22.00 22.10

0.45

070

2.72

0.30

14.00

20.00

0.65

17.20

0.80

1.60

Nom.

0.100.050.002 0.004 0.006 0.15

1.40

0.32

14.00

20.00

0.65

16.00

0.60

1.00

2.87

0.40

0.20

14.10

20.10

0.802

17.40

0.95

0.08

1.45

0.38

0.20

14.10

20.10

0.802

16.10

0.75

0.08

7

7

Seating Plane

See Detail F

C

A

2

A

1

y

L

L

1

- 16 -

W25P022A

Headquarters

No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: [phone]
FAX: [phone]
http://www.winbond.com.tw/
Voice & Fax-on-demand: 886-2-7197006

Winbond Electronics (H.K.) Ltd.

Rm. 803, World Trade Square, Tower II,
123 Hoi Bun Rd., Kwun Tong,
Kowloon, Hong Kong
TEL: [phone]
FAX: [phone]

Taipei Office

11F, No. 115, Sec. 3, Min-Sheng East Rd.,
Taipei, Taiwan
TEL: [phone]
FAX: [phone]

Note: All data and specifications are subject to change without notice.

Winbond Electronics North America Corp.
Winbond Memory Lab.
Winbond Microelectronics Corp.
Winbond Systems Lab.

2730 Orchard Parkway, San Jose,
CA 95134, U.S.A.
TEL: [phone]
FAX: [phone]

Publication Release Date: September 1996

- 17 - Revision A1