Datasheet W2465AK-20, W2465AK-15, W2465AK-12, W2465AJ-20, W2465AJ-15 Datasheet (Winbond Electronics)

W2465A

CS1

Chip Select Inputs

WE

Write Enable Input

OE

Output Enable Input

8K × 8 HIGH-SPEED CMOS STATIC RAM

GENERAL DESCRIPTION

The W2465A is a high-speed, low-power CMOS static RAM organized as 8192 × 8 bits that operates
on a single 5-volt power supply. This device is manufactured using Winbond's high performance
CMOS technology.

FEATURES

• High-speed access time: 12/15/20 nS (max.)

• Low-power consumption:

− Active: 400mW (typ.)

• Single +5V power supply

• Fully static operation

PIN CONFIGURATION

NC

A12

A7
A6
A5

A4
A3
A2
A1
A0

I/O1
I/O2
I/O3

V

SS

1
2

3
4
5

6
7
8
9 20
10
11
12
13
14

28

V

DD

27

WE

26

CS2

A8

25

A9

24

A11

23
22

OE
A10

21

CS1
I/O8

19

I/O7

18

I/O6

17
16

I/O5
I/O4

15

• All inputs and outputs directly TTL compatible

• Three-state outputs

• Available packages: 28-pin 300 mil SOJ and

skinny DIP

BLOCK DIAGRAM

V

DD

V

SS

A0

.

A12

CS2

CS1

WE

OE

DECODER

.

CONTROL

CORE

C O RE

ARRAY

DATA I/O

I/O1

I/O8

.
.

PIN DESCRIPTION

SYMBOL DESCRIPTION

A0−A12

I/O1−I/O8

, CS2

Address Inputs
Data Inputs/Outputs

VDD Power Supply
VSS Ground

NC No Connection

Publication Release Date: October 1995

- 1 - Revision A6

W2465A

CS1

CS1

CS1

CS1

DC CHARACTERISTICS

Absolute Maximum Ratings

PARAMETER RATING UNIT
Supply Voltage to VSS Potential -0.5 to +7.0 V
Input/Output to VSS Potential -0.5 to VDD +0.5 V
Allowable Power Dissipation 1.0 W
Storage Temperature -65 to +150
Operating Temperature 0 to +70

Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the
device.

TRUTH TABLE

CS1 CS2 OE WE MODE

H X X X Not Selected High Z ISB, ISB1
X L X X Not Selected High Z ISB, ISB1

L H H H Output Disable High Z IDD
L H L H Read Data Out IDD
L H X L Write Data In IDD

I/O1−I/O8

°C
°C

VDD CURRENT

OPERATING CHARACTERISTICS

(VDD = 5V ±10%, VSS = 0V, TA = 0 to 70° C)

PARAMETER SYM. TEST CONDITIONS MIN. TYP. MAX. UNIT
Input Low Voltage VIL - -0.5 - +0.8 V
Input High Voltage VIH - +2.2 - VDD +0.5 V
Input Leakage Current ILI VIN = VSS to VDD -10 - +10
Output Leakage

Current

Output Low Voltage VOL IOL = +8.0 mA - - 0.4 V
Output High Voltage VOH IOH = -4.0 mA 2.4 - - V
Operating Power

Supply Current

Standby Power
Supply

Note: Typical characteristics are at VDD = 5V, TA = 25° C.

Current

ILO VI/O = VSS to VDD,

= VIH or CS2 = VIL

or OE = VIH or WE = VIL

IDD

= VIL

CS2 = VIH
I/O = 0 mA

Cycle = MIN
Duty = 100% 20 - - 120 mA

ISB

= VIH or CS2 = VIL
Cycle = MIN
Duty = 100%

ISB1

≥ VDD -0.2V

or CS2 ≤ 0.2V

-10 - +10

12 - - 180 mA

15 - - 150 mA

- - 30 mA

- - 5 mA

µA
µA

- 2 -

W2465A

CAPACITANCE

(VDD = 5V, TA = 25° C, f = 1 MHz)

PARAMETER SYM. CONDITIONS MAX. UNIT

Input Capacitance CIN VIN = 0V 8 pF
Input/Output Capacitance CI/O VOUT = 0V 10 pF

Note: These parameters are sampled but not 100% tested.

AC TEST CONDITIONS

PARAMETER CONDITIONS

Input Pulse Levels 0V to 3V
Input Rise and Fall Times 5 nS
Input and Output Timing Reference Level 1.5V
Output Load CL = 30 pF, IOH/IOL = -4 mA/8 mA

AC TEST LOADS AND WAVEFORM

R1 480 ohm

5V

OUTPUT

30 pF

Including
Jig and
Scope

R2
255 ohm

3.0V

0V

5 nS

10%

5V

OUTPUT

(For T T T T

CLZ1,

CLZ2, OLZ,

90% 90%

10%

5 nS

R1 480 ohm

5 pF

Including
Jig and
Scope

T

CHZ1,

CHZ2, OHZ,

R2
255 ohm

T T T

WHZ,

OW

)

Publication Release Date: October 1995

- 3 - Revision A6

W2465A

Chip Select

Chip Selection to

Chip Deselection

Chip Selection to

Write Recovery Time

AC CHARACTERISTICS

(VDD = 5V ±10%, VSS = 0V, TA = 0 to 70° C)

Read Cycle

PARAMETER SYM. W2465A-12 W2465A-15 W2465A-20 UNIT

MIN. MAX. MIN. MAX. MIN. MAX.

Read Cycle Time TRC 12 - 15 - 20 - nS
Address Access Time TAA - 12 - 15 - 20 nS

CS1

Access Time
Output Enable to Output Valid TAOE - 6 - 7 - 10 nS

Output in Low Z
Output Enable to Output in Low Z TOLZ* 0 - 0 - 0 - nS

to Output in High Z
Output Disable to Output in High Z TOHZ* - 6 - 7 - 10 nS

Output Hold from Address Change TOH 3 - 3 - 3 - nS

* These parameters are sampled but not 100% tested.

CS2 TACS2 - 12 - 15 - 20 nS

CS1

CS2 TCLZ2* 3 - 3 - 3 - nS

CS1

CS2 TCHZ2* - 6 - 7 - 10 nS

TACS1 - 12 - 15 - 20 nS

TCLZ1* 3 - 3 - 3 - nS

TCHZ1* - 6 - 7 - 10 nS

Write Cycle

PARAMETER SYM. W2465A-12 W2465A-15 W2465A-20 UNIT

MIN. MAX. MIN. MAX. MIN. MAX.

Write Cycle Time TWC 12 - 15 - 20 - nS

CS1

End of Write
Address Valid to End of Write TAW 10 - 13 - 17 - nS

Address Setup Time TAS 0 - 0 - 0 - nS
Write Pulse Width TWP 10 - 10 - 12 - nS

Data Valid to End of Write TDW 7 - 9 - 10 - nS

CS2 TCW2 10 - 13 - 17 - nS

CS1, WE

CS2 TWR2 0 - 0 - 0 - nS

Data Hold from End of Write

Write to Output in High Z TWHZ* - 7 - 8 - 10 nS
Output Disable to Output in High Z TOHZ* - 7 - 8 - 10 nS
Output Active from End of Write TOW 0 - 0 - 0 - nS

* These parameters are sampled but not 100% tested.

TCW1 10 - 13 - 17 - nS

TWR1 0 - 0 - 0 - nS

TDH 0 - 0 - 0 - nS

- 4 -

TIMING WAVEFORMS

Read Cycle 1
(Address Controlled)

Address

D

OUT

Read Cycle 2
(Chip Select Controlled)

CS1

CS2

D

OUT

W2465A

T

RC

T

AA

T

OH

T

ACS1

T

ACS2

T

CLZ1

T

CLZ2

T

OH

T

CHZ1

T

CHZ2

Read Cycle 3
(Output Enable Controlled)

Address

OE

CS1

CS2

D

OUT

T

RC

T

AA

T

CHZ2

T

CHZ1

T

OH

T

OHZ

T

T

CLZ1

CLZ2

T

T

T

ACS1

ACS2

OLZ

T

AOE

Publication Release Date: October 1995

- 5 - Revision A6

Timing Waveforms, continued

Write Cycle 1

(OE Clock)

Address

OE

CS1

W2465A

T

WC

T

WR1

T

CW1

CS2

WE

D

OUT

D

IN

Write Cycle 2

(OE = VIL Fixed)

Address

CS1

CS2

WE

D

OUT

D

IN

T

CW2

T

AW

T

T

AS

T

OHZ

(1, 4)

T

AW

T

AS

WP

T

WC

T

CW1

T

CW2

T

WP

T

WHZ(1, 4)

T

WR2

T

DW

T

DW

T

T

WR1

WR2

T

T

DH

T

OH

T

OW

DH

(2)

(3)

Notes:

1. During this period, I/O pins are in the output state, so input signals of opposite phase to the outputs should not be applied.

2. The data output from DOUT are the same as the data written to DIN during the write cycle.

3. DOUT provides the read data for the next address.

4. Transition is measured ±500 mV from steady state with CL = 5 pF. This parameter is guaranteed but not 100% tested.

- 6 -

ORDERING INFORMATION

W2465A

ACCESS

PART NO.

W2465AK-12 12 180 5 300 mil skinny
W2465AK-15 15 150 5 300 mil skinny
W2465AK-20 20 120 5 300 mil skinny
W2465AJ-12 12 180 5 300 mil SOJ
W2465AJ-15 15 150 5 300 mil SOJ
W2465AJ-20 20 120 5 300 mil SOJ

Notes:

1. Winbond reserves the right to make changes to its products without prior notice.

2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications
where personal injury might occur as a consequence of product failure.

TIME (nS)

OPERATING

CURRENT

Max. (mA)

STANDBY
CURRENT
Max. (mA)

PACKAGE

Publication Release Date: October 1995

- 7 - Revision A6

PACKAGE DIMENSIONS

28-pin P-DIP Skinny

28

1

E

1 14

S

2

A

A

L

D

B
B

e

1

1

W2465A

Dimension in Inches Dimension in mm

Symbol

A
A
A
B
B

15

1

A

Base Plane

Mounting Plane

E

e

A

a

c

c
D
E
E

e
L

a

e

S

Notes:

1. Dimension D Max. & S include mold flash or
tie bar burrs.

2. Dimension E1 does not include interlead flash.

3. Dimension D & E1 include mold mismatch and
are determined at the mold parting line.

4. Dimension B1 does not include dambar
protrusion/intrusion.

5. Controlling dimension: Inches.

6. General appearance spec. should be based on
final visual inspection spec.

Min.

0.010

1

0.125

2

0.016

1

0.008

1
1

0.120

°

0

A

Nom.

Max. Max.

0.175

0.130

0.135

0.018

0.022

0.060 1.52

0.0640.058

0.010

0.014

1.388 1.400

0.3100.300 0.320

0.2930.2880.283

0.110

0.140

0.130

0.370

0.3500.330 8.38 8.89

0.055

Nom.

Min.

0.25

3.18

3.30

0.41

0.46

0.20

35.26 35.56

7.19

2.29 2.54 2.790.090 0.100

3.05

°

°

15

0

4.45

3.43

0.56

1.631.47

0.36

0.25

8.13

7.877.62

7.447.32

3.30

3.56

°

15

9.40

1.40

28-pin Small Outline J Band

28

1

D

b

s

Seating Plane

b

1

e

Dimension in Inches

Symbol

Min. Nom. Max. Max.Nom.Min.

A

0.027

1

A

0.095

0.100

2

A

0.026

b 1

0.016

0.044

1

E

0.077

0

0.018

0.010 0.25

0.710

0.050 0.056

0.2650.245 7.246.736.22

0.087

15

E

E

H

b
c

D
E

e
e
H

14

L
S

y
0

Notes:

1. Dimension D Max. & S include mold flash
or tie bar burrs.

2. Dimension b does not include dambar

2

A

A

L

1

A

y

0

e

c

1

protrusion/intrusion.

3. Dimension D & E include mold mismatch
and are determined at the mold parting line.

4. Controlling dimension: Inches.

5. General appearance spec. should be based
on final visual inspection spec.

0.140

0.105

0.0320.028

0.022

0.0140.008

0.730

0.3050.3000.295

0.285

0.347

0.097 1.96

0.045

0.004
10

Dimension in mm

0.69

2.41

2.54

0.41

0.46

18.03

7.49

7.62

1.12

1.27

8.31 8.56 8.810.327 0.337

2.21

0

3.56

18.54

1.14

0.10

2.67

0.810.710.66

0.56

0.360.20

7.75

1.42

2.46

10

- 8 -

W2465A

Headquarters

No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: [phone]
FAX: [phone]
http://www.winbond.com.tw/
Voice & Fax-on-demand: 886-2-7197006

Winbond Electronics (H.K.) Ltd.

Rm. 803, World Trade Square, Tower II,
123 Hoi Bun Rd., Kwun Tong,
Kowloon, Hong Kong
TEL: [phone]
FAX: [phone]

Taipei Office

11F, No. 115, Sec. 3, Min-Sheng East Rd.,
Taipei, Taiwan
TEL: [phone]
FAX: [phone]

Note: All data and specifications are subject to change without notice.

Winbond Electronics North America Corp.
Winbond Memory Lab.
Winbond Microelectronics Corp.
Winbond Systems Lab.

2730 Orchard Parkway, San Jose,
CA 95134, U.S.A.
TEL: [phone]
FAX: [phone]

Publication Release Date: October 1995

- 9 - Revision A6