Datasheet W24256S-70LL, W24256S-70L, W24256Q-70LL, W24256Q-70L, W24256-70LL Datasheet (Winbond Electronics)

Preliminary W24256

15

14

R

CS

WE

OE

32K × 8 CMOS STATIC RAM

GENERAL DESCRIPTION

The W24256 is a normal speed, very low power CMOS static RAM organized as 32768 × 8 bits that operates on a single 5-volt power supply. This device is manufactured using Winbond's high performance CMOS technology.

FEATURES

•

Low power consumption:

•

Access time: 70 nS (max.)

•

Active :300 mW

Standby :250 µW

•

Single 5V power supply

•

Fully static operation

•

All inputs and outputs directly TTL compatible

•

Three-state outputs

•

Battery back-up operation capability

•

Data retention voltage: 2V (min.)

•

Packaged in 28-pin 600 mil DIP, 330 mil SOP and standard type one TSOP (8 mm × 13.4 mm)

PIN CONFIGURATIONS

1

A14 A12

2

A7

3

A6

4

A5

5

A4

6

28-pin

7

DIP 8 9 10 11 12 13 14

28-pin TSOP

A11

A13

WE V A14 A12

A3 A2

A1

A0 I/O1 I/O2 I/O3

V

SS

OE

1 2

A9

3

A8

4 5 6 7

DD

8 9

A7

10

A6

11

A5

12

A4

13

A3

BLOCK DIAGRAM

CLK GEN.

A12 A14 A2

WE CS OE

A3 A4 A5 A6 A7 A13 I/O1 I/O8

DATA CNTRL.

28

V

DD

27

WE

26

A13

25

A8

24

A9

23

A11

22

OE

21

A10

20

CS I/O8

19

I/O7

18

I/O6

17

I/O5

16

I/O4

CLK GEN.

R O

W

D E C O D E

PRECHARGE CKT.

CORE CELL ARRAY

512 ROWS

64 X 8 COLUMNS

I/O CKT.

COLUMN DECODER

A10 A1 A0A8A9

A11

PIN DESCRIPTION

A10

28 27

CS

26

I/O8

25

I/O7

24

I/O6

23

I/O5

22

I/O4

21

VSS

20

I/O3

19

I/O2

18

I/O1

17

A0 A1

16

A2

15

SYMBOL DESCRIPTION

A0−A14

I/O1−I/O8

Address Inputs Data Inputs/Outputs Chip Select Input Write Enable Input Output Enable Input

VDD Power Supply VSS Ground

Publication Release Date: October 1999

- 1 - Revision A1

TRUTH TABLE

CS OE WE

WE

CS

Preliminary W24256

MODE

I/O1−I/O8

VDD CURRENT

H X X Not Selected High Z ISB, ISB1

L H H Output Disable High Z IDD L L H Read Data Out IDD L X L Write Data In IDD

DC CHARACTERISTICS

Absolute Maximum Ratings

PARAMETER RATING UNIT

Supply Voltage to VSS Potential -0.5 to +7.0 V Input/Output to V Allowable Power Dissipation 1.0 W Storage Temperature -65 to +150 Operating Temperature 0 to 70

Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device.

Operating Characteristics

(VDD = 5V ±10%; VSS = 0V; TA = 0° C to 70° C)

SS

Potential -0.5 to VDD +0.5 V

°

C

°C

PARAMETER SYM.

Input Low Voltage V Input High Voltage V Input Leakage Current I Output Leakage Current I

IL

IH

LI

LO

TEST CONDITIONS MIN. TYP.* MAX. UNIT

- -0.5 - +0.8 V

- +2.2 - VDD +1 V

VIN = VSS to VDD -5 - +5 VI/O = VSS to VDD, CS = VIH

-5 - +5

µ

A

µ

A

(min.) or OE = VIH (min.) or

= VIL (max.) Output Low Voltage V Output High Voltage V Operating Power Supply Current Standby Power Supply

Current

I LL - - 50

Note: Typical parameter is measured under ambient temperature TA = 25° C and VDD = 5V.

OL IOL

OH IOH

DD

I

= +2.1 mA - - 0.4 V

= -1.0 mA 2.4 - - V

= VIL (max.), I/O = 0 mA ,

Cycle = min , Duty = 100 %

SB

I

= VIH (min.), Cycle = min.

Duty = 100%

SB1

≥ VDD -0.2V

- - 60 mA

- - 3 mA

L - - 100

µ

A

µ

A

- 2 -

Preliminary W24256

CAPACITANCE

(VDD = 5V, TA = 25° C, f = 1 MHz)

PARAMETER SYM. CONDITIONS MAX. UNIT

Input Capacitance CIN VIN = 0V 6 pF Input/Output Capacitance C

Note: These parameters are sampled but not 100% tested.

I/O

V

OUT

= 0V 8 pF

AC CHARACTERISTICS

AC Test Conditions

PARAMETER CONDITIONS

Input Pulse Levels 0V to 3.0V Input Rise and Fall Times 5 nS Input and Output Timing Reference Level 1.5V Output Load See the drawing below

AC TEST LOADS AND WAVEFORM

1 TTL

OUTPUT

100 pF Including Jig and Scope

OUTPUT

(For T T T T T T )

CLZ, OLZ,

OHZ, WHZ, OW

CHZ,

1 TTL

5 pF Including Jig and Scope

3.0V 0V

90% 10%

5 nS

90%

10%

5 nS

Publication Release Date: October 1999

- 3 - Revision A1

Preliminary W24256

CS, WE

AC Characteristics, continued (VDD = 5V ±10%; VSS = 0V; TA = 0° C to 70° C)

Read Cycle

PARAMETER SYM. W24256-70L/LL UNIT

MIN. MAX.

Read Cycle Time TRC 70 - nS Address Access Time TAA - 70 nS Chip Select Access Time T Output Enable to Output Valid T Chip Selection to Output in Low Z T Output Enable to Output in Low Z T Chip Deselection to Output in High Z T Output Disable to Output in High Z T Output Hold from Address Change TOH 3 - nS

These parameters are sampled but not 100% tested

∗

ACS

- 70 nS

AOE

- 30 nS

CLZ

* 5 - nS

OLZ

* 5 - nS

CHZ

* - 20 nS

OHZ

* - 20 nS

Write Cycle

PARAMETER SYM. W24256-70L/LL UNIT

MIN. MAX.

Write Cycle Time TWC 70 - nS Chip Selection to End of Write TCW 70 - nS Address Valid to End of Write TAW 70 - nS Address Setup Time TAS 0 - nS Write Pulse Width TWP 50 - nS Write Recovery Time

Data Valid to End of Write TDW 30 - nS Data Hold from End of Write TDH 0 - nS Write to Output in High Z T Output Disable to Output in High Z T Output Active from End of Write TOW 5 - nS

These parameters are sampled but not 100% tested

∗

TWR 0 - nS

WHZ

* - 25 nS

OHZ

* - 30 nS

- 4 -

TIMING WAVEFORMS

AA

Read Cycle 1

(Address Controlled)

Address

OUT

D

Read Cycle 2

(Chip Select Controlled)

Preliminary W24256

TRC

T

OH

T

TOH

CS

D

OUT

Read Cycle 3

(Output Enable Controlled)

Address

OE

CS

D

OUT

T CLZ

TACS

T

CLZ

T

CHZ

RC

T

AA

AOE

T

TOLZ

ACS

T

OH

T

OHZ

CHZ

T

Publication Release Date: October 1999

- 5 - Revision A1

Timing Waveforms, continued

Write Cycle 1

Address

OE

CS

WE

D

OUT

D

IN

Write Cycle 2

Preliminary W24256

T

WC

T

WR

T

CW

T

AW

T

AS

T

OHZ

(1, 4)

WP

T

DW

DH

(OE = VIL Fixed)

T

WC

Address

(1, 4)

T

DW

T

WR

T

OH

T

OW

T

DH

(2) (3)

T

CW

CS

T

AW

WE

D

OUT

D

IN

T

AS

T

WP

T

WHZ

Notes:

1. During this period, I/O pins are in the output state, so input signals of opposite phase to the outputs should not be applied.

2. The data output from DOUT are the same as the data written to DIN during the write cycle.

3. DOUT provides the read data for the next address.

4. Transition is measured ±500 mV from steady state with CL = 5 pF. This parameter is guaranteed but not 100% tested.

- 6 -

DATA RETENTION CHARACTERISTICS

CS

(TA = 0° C to 70° C)

PARAMETER SYM. TEST CONDITIONS MIN. TYP. MAX. UNIT

Preliminary W24256

VDD for Data Retention VDR Data Retention Current I Chip Deselect to Data

DDDR

CDR

T

≥ VDD -0.2V ≥ VDD -0.2V, VDD = 3V

See data retention waveform 0 - - nS

2.0 - 5.5 V

- - 20

µ

A

Retention Time Operation Recovery Time TR TRC* - - nS

Read Cycle Time

*

DATA RETENTION WAVEFORM

DD

V

CS

V

IH

0.9 DD

V

T

CDR

>

VDR2V

=

>

DD

VCS

=

-0.2V

0.9 DDV

R

T

IH

V

ORDERING INFORMATION

PART NO. ACCESS

TIME

(nS)

W24256-70L 70 60 100 600 mil DIP W24256-70LL 70 60 50 600 mil DIP W24256S-70L 70 60 100 330 mil SOP W24256S-70LL 70 60 50 330 mil SOP W24256Q-70L 70 60 100 Standard type one TSOP W24256Q-70LL 70 60 50 Standard type one TSOP

OPERATING

CURRENT MAX.

(mA)

STANDBY

CURRENT MAX.

(

A)

µ

PACKAGE

Notes:

1. Winbond reserves the right to make changes to its products without prior notice.

2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure.

Publication Release Date: October 1999

- 7 - Revision A1

PACKAGE DIMENSIONS

28-pin P-DIP

Preliminary W24256

28

E

1

S

A

2A

L

D

B B

1

28-pin SOP Wide Body

28

1

D

S

Seating Plane

e

Dimension in Inches

Symbol

Min. Nom. Max. Max.Nom.Min.

A

0.010

A

1

0.150

A B B1 c D

15

14

E

A

1

Base Plane Seating Plane

e

1

e

a

A

c

E E e L

a

e S

Notes:

1. Dimensions D Max. & S include mold flash or tie bar burrs.

2. Dimension E1 does not include interlead flash.

3. Dimensions D & E1 include mold mismatch and are determined at the mold parting line.

4. Dimension B1 does not include dambar protrusion/intrusion.

5. Controlling dimension: Inches.

6. General appearance spec. should be based on final visual inspection spec.

Symbol

15

E

E H

14

b

1e

θ

L

Detail F

θ

Notes:

1. Dimensions D Max. & S include mold flash

1

e

A

2

1

A

y

See Detail F

c

E

L

or tie bar burrs.

2. Dimension b does not include dambar protrusion/intrusion.

3. Dimensions D & E include mold mismatch and determined at the mold parting line.

4. Controlling dimension: Inches.

5. General appearance spec should be based on final visual inspection spec.

0.155

2

0.016

0.018

0.060 1.52

0.008

0.010

1.460 1.470 37.08 37.34

0.6000.590

0.540

1

0.090

0.100

1

0.120

0.130

0 15

0.630

0.650

A

Dimension in Inches

Nom.

Min.

A

0.004

1

A

0.098

0.093

A

2

0.014

0.016

b

0.0100.008

c

0.713

D E

e HE

0.028

0.036

L

0.059

0.067

LE S y

0 10

Dimension in mm

0.210 5.33

0.25

0.160

3.81

3.94

0.41

0.022

0.0640.058

0.014

0.610

0.5500.545

0.110

0.140

0.670

0.090

0.46

0.20

0.25

15.24

14.99

13.72 13.9713.84

2.29

2.54 2.79

3.05

3.30

16.00 16.51

.

Dimension in mm

Nom.

Max. Max.

Min.

0.112

0.10

0.103

2.36

2.49

0.36

0.41

0.020

0.014 0.36

0.733

0.3360.3310.326

0.4770.4650.453 12.1211.8111.51

0.044

0.075 1.50

0.047

0.004

0.250.20

18.11

8.28

8.41

1.12 1.27 1.420.044 0.050 0.056

0.91 1.12

0.71

1.70

0

.

15.49

2.85

2.62

0.51

18.62

8.53

1.91

4.06

0.56

1.631.47

0.36

3.56

17.02

2.29

1.19

0.10 10

150

- 8 -

Package Dimensions, continued

28-pin Standard Type One TSOP

H

D

1

e

b

θ

L

L1

Preliminary W24256

Dimension In Inches

Symbol

Min.

Nom. Max. Min. Nom.

c

E

A

2

A

1

Y

A

0.002

A

1

2

A

b c D

E

D

H e

L

1

Y

θ

Controlling dimension: Millimeters

0.040

0.035

0.007 0.008 0.011

0.004

0.006

0.461 0.465 0.469

0.311 0.315 0.319

0.520 0.528 0.536

0.022

0.020

0.024 0.028

0.010

0.000 3

0

0.047

0.006

0.041

0.008

0.004 5

Dimension In mm

0.05

1.000.95

0.17

0.20 0.27

0.10

0.15 0.21

11.70

11.80

8.00 8.10

7.90

13.20

13.40

0.55

0.50

0.60

0.25

0.00 3 5

0

Max.

1.20

0.15

1.05

11.90

13.60

0.70

0.10

Publication Release Date: October 1999

- 9 - Revision A1

Preliminary W24256

VERSION HISTORY

VERSION DATE PAGE DESCRIPTION

A1 Oct. 1999 - Initial issued

Headquarters

No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5796096 http://www.winbond.com.tw/ Voice & Fax-on-demand: 886-2-27197006

Taipei Office

11F, No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-27190505 FAX: 886-2-27197502

Note: All data and specifications are subject to change without notice.

Winbond Electronics (H.K.) Ltd.

Rm. 803, World Trade Square, Tower II, 123 Hoi Bun Rd., Kwun Tong, Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064

- 10 -

Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab.

2727 N. First Street, San Jose, CA 95134, U.S.A. TEL: 408-9436666

FAX: 408-5441798