Datasheet W182 Datasheet (Cypress)

Full Feature Peak Reducing EMI Solution

Features

Cypress PREMIS™ family offering

•

• Generates an EMI optimized c locking signal at the
output

• Selectable output frequency range

• Single 1.25% or 3.75% dow n or center spread output

• Integrated loop filter components

• Operates with a 3.3 or 5V supply

• Low power CMOS design

• Available in 14 -p i n S OIC (S mall Outl in e Int e g ra te d
Circuit)

Key Specifications

Suppl y Voltages: .............. .......... .......... .. .......VDD = 3.3V±5%

Fr equency Range: ........ ............ ..........8 M H z ≤ F

Cycle to Cy c le Ji tte r:........... .. .. .......... .......... .....300 ps (max.)

Selectabl e Spread Percentage: .......... ..........1.25% or 3.75%

Output Duty Cycle: ............................... 40/60% (worst case)

Output R is e a n d Fall Tim e : . .. .. .......... .......... ......... 5 ns (max.)

or V

= 5V±10%

DD

≤

28 MHz

in

T able 1. Modulation Width Selection

W182

SS%

0F

1F

≥

F

in

– 1.25%

≥

F

in

– 3.75%

Output

≥

F

out

≥

F

out

in

in

F

in

– 0.625%
F

in

–1.875%

Table 2. Frequency Range Selection

FS2 FS1 Frequency Range

00 8 MHz ≤ F
0 1 10 MHz ≤ F
10 15 MHz ≤ F
11 18 MHz ≤ F

IN

IN
IN
IN

W182

W182-5

Output

+ 0.625% ≥ F

+ 1.875% ≥ F

≤

10 MHz

≤

15 MHz

≤

18 MHz

≤

28 MHz

in

in≥

≥

Simplified Block Diagram

3.3V or 5.0V

X1

XTAL
Input

Oscilla tor or
Reference Input

X2

W182

3.3V or 5.0 V

W182

Spread Spectrum
Output

(EMI su ppressed)

Spread Spectrum
Output

(EMI suppressed)

Pin Configuration

SOIC

FS2

CLKIN or X1

NC or X2

GND
GND

SS%
FS1

1
2
3
4
5
6

7

W182/W182-5

13
12
11
10

9
8

OE#
SSON#
Reset

VDD
VDD
CLKOUT

REFOUT

14

PREMIS is a trademark of Cypress Semiconductor Corporation.

Cypress Semiconductor Corporation

• 3901 North First Street • San Jose • CA 95134 • 408-943-2600
June 8, 2000 , rev. *A

Pin Definitions

W182

Pin Name Pin No.

CLKOUT 8 O

REFOUT 14 O

CLKIN or X1 2 I

NC or X2 3 I

SSON# 12 I

SS% 6 I

OE# 13 I

Reset 11 I

FS1:2 7, 1 I

VDD 9,10 P
GND 4,5 G

Pin

Ty pe Pin Description

Output Modulated Frequency

(SSON# asserted).

Non-Modulated Output:

This output will not have the Spread Spect rum feature enabl ed regardless of
the state of logic input SSON#.

Crystal Connection or External Reference Frequency Input:

dual functions. It may either be connected to an ex ternal crystal , or to an
external reference clock.

Crystal Connection:

ternal reference, this pin mus t be left unconnected.

Spread Spectrum Contro l (Active LOW):

turns the internal modul ation wav e f orm on. Thi s pin has an internal pul l-do wn
resistor.

Modulation Width Selection:

this pin is used to select the am ount of variation and peak EMI reduction that
is desired on the output signal. This pin has an internal pull -up resistor.

Output Enable (Active LOW):

are placed in a high-impedance mode.This pin has an internal pull-down re­sistor.

Modulation Profile Restart:

pattern at the begi nning of its de fined path . This pin has an internal pul l-do wn
resistor.

Frequency Selection Bit(s):

ation. Refer to Table 2. These pins have internal pull-up resistors.

Po wer Connec tion:
Ground Connection:

Input connectio n for an external crystal. If using an ex-

Connected to 3.3V or 5V po wer supply.

Connect all g round pins to the common ground plane.

: Freq uency modulat ed copy of the input clock

This pin provides a copy of the ref erence frequ ency.

This pin has

Asserting this signal (acti ve LOW )

When Spread Spectrum feature is turned on,

When this pi n is he ld HIGH, th e output b uff er s

A rising edge on this input restarts the modulati on

These pins select the frequency range of oper-

2

W182

Overview

The W182 product is one of a seri es of de v ices i n the Cypr ess
PREMIS family. The PREMIS family incorporates the latest
advanc es in PLL spread spectrum frequency synthesizer t ech­niques. By frequency modulating the output with a low-fre­quency carrier, peak EMI is greatl y reduced. Use of this tech­nology allows s ystems to pass increasingl y diff icult EMI testin g
without resorting to costly shielding or redesign.

In a system, not only i s EMI reduce d in the v arious cl oc k li nes,
but also in all signals which are synchronized to the clock.
Therefore, the benefits of using this technology increase with
the number of address and dat a lines in the syst em. The Sim­plified Block Diagram shows a simple implementation.

Functional Description

The W182 uses a Phase-Locked Loop (PLL) to frequency
modulate an input clock. The result is an output clock whose
frequency is slowly swept over a narrow band near the input
signal. The basic circuit topology is shown in Figure 1. The
input reference signal is divided by Q and fed to the phase
detector. A signal from the VCO is divided by P and fed back
to the phase detec tor als o . The PLL will f or ce the frequen cy of
the VCO output sign al to change until the divid ed output signal
and the divided reference signal match at the phase detector
input. The output frequency is then equal to the ratio of P/Q

times the ref er ence fre quenc y. (Note: F or t he W182 t he outpu t
frequency is nominally equal to the input frequency.) The
unique feature of the Spread Spectrum Frequency Timing
Generator is that a modulating waveform is superimposed at
the input to th e VCO. This cau ses the VCO out put to be slo wl y
swept across a predetermined frequency band.

Because the modulating frequency is typically 1000 times
slower than the fundamental clock, the spread spectrum pro­cess has little impact on system performance.

Frequency Selection With SSFTG

In Spread Spectrum Frequency Timing Generation, EMI re­duction depends on the shape, modulation percentage, and
frequency of the modulating waveform. While the shape and
frequency of the modulating waveform are fixed for a given
frequency, the modulation percentage may be va ried .

Using frequency select bits (FS2: 1 pins), the frequency range
can be set (see Table 2). Spreading percentage is set with pin
SS% as shown in Table 1.

A larger spreading per centage improves EMI reduction. How­ever, large spread percentages may either exceed system
maximum frequ ency ra tings o r lo wer the a v er age fr eque ncy to
a point where performance is affected. For these reasons,
spreading percent age options are provided.

V

DD

Clock Input

Reference Input (EMI suppressed)

Freq. Phase

Q

Detector

Feedback

Divider

P

Charge

Pump

GND

Σ

Modulating

Waveform

VCO

PLL

Post

DividersDivider

CLKOUT

Figure 1. Functional Block Diagram

3

W182

Spread Spectrum Frequency Timing
Generation

The device generates a clock that is frequency modulated in
order to increase the bandwidth that it occu pies. By increas ing
the bandwidth of the fundamental and its harmonics, the am­plitudes of the radiated electromagnetic emissions are re­duced. This effect is depicted in Figure 2.

As shown in Figure 2, a harmonic of a modulated clock has a
much low er amplit ude than that of an un modulated si gnal. The
reduction in amplitude is dependent on the harmonic number
and the frequency deviation or spread. The equation for the
reduction is:

dB = 6.5 + 9*log

Amplitude (dB)

(P) + 9*log10(F)

10

SSFTG Typical Clock

Where P is the pe rcentag e of de vi ation an d F is the frequency
in MHz where the reduction is measured.

The output clock is modulated with a waveform depicted in
Figure 3. This waveform, as discussed in “Spread Spectrum
Clock Gener ation f or the Redu ct ion of Radiat ed Emission s” by
Bush, Fessler, and Hardin produces the maximum reduction
in the amplitude of radiat ed electro magnetic emis sions. Figure
3 details the Cypress spreading pattern. Cypress does offer
options with more spread and greater EMI reduction. Contact
your local Sales representativ e for details on these devices.

EMI Reduction

Spread

Spectrum

Enabled

Amplitude (dB)

Non-

Spread

Spectrum

Frequency Span (MHz)

Center Spread

Frequency Span (MHz)

Down Spread

Figure 2. Clock Harmonic with and with out SSCG Modulati on Frequency Dom ain Representat ion

MAX.

10%

20%

30%

40%

50%

60%

70%

80%

FREQUENCY

MIN.

90%

100%

10%

20%

30%

40%

50%

60%

70%

80%

Figure 3. Typical Modulation Pr ofile

90%

100%

4

Absolute Maximum Ratings

W182

Stresses greater than those listed in this table may cause per­manent damage to the de vice . These represent a stress ratin g
only. Operation of the device at these or any other conditions

.

above those specified i n the operating sec ti ons of this specif i­cation is not implied. Maximum conditions for extended peri­ods may affect reliability.

Parameter Description Rating Unit

V

, V

DD

IN

T

STG

T

A

T

B

P

D

DC Electr i cal C h ar acteristics

Voltage on any pin with respect to GND –0.5 to +7 .0 V
Storage Temperature –65 to +150 °C
Operating Tempera ture 0 to +70 °C
Ambient Temperature under Bias –55 to +125 °C
Power Dissi pation 0.5 W

:

0°C < T

< 70°C, VDD = 3.3V ±5%

A

Parameter Description T est Condition Min. T yp. Max. Unit

I

DD

t

ON

V

IL

V

IH

V

OL

V

OH

I

IL

I

IH

I

OL

I

OH

C

I

R

P

Z

OUT

Note:

1. Inputs FS2:1 have a pull-up resistor; Input SSON# has a pull-down resistor.

Supply Current 18 32 mA
Power Up Time First locked clock cycle after Power

5ms

Good
Input Low Voltage 0.8 V
Input High Vol tage 2.4 V
Output Low Voltage 0.4 V
Output High Voltage 2.4 V
Input Low Current Note 1 –50 µA
Input High Current Note 1 50 µA
Output Low Current @ 0.4V, VDD = 3.3V 15 mA
Output High Current @ 2.4V, VDD = 3.3V 15 mA
Input Capacitance 7pF
Input Pull-Up Resistor 500 kΩ
Clock Output I mp edance 25 Ω

5

W182

DC Electr i cal C h ar acteristics:

0°C < T

< 70°C, VDD = 5V ±10%

A

Parameter Description Test Condition Min. Typ. M ax. Unit

I
t

V
V
V
V
I
I
I
I
C
R
Z

DD
ON

IL
IH
OL

OH
IL
IH
OL
OH

I

P

OUT

Supply Current 30 50 mA
Power Up Time First locked clock cycle after

5ms

Power Good
Input Low Voltage 0.15V
Input High Voltage 0.7V

DD

DD

Output Low Voltage 0.4 V
Output High Voltage 2.4 V
Input Low Current Note 2 –50 µA
Input High Current Note 2 50 µA
Output Low Current @ 0.4V, VDD = 5V 24 mA
Output High Current @ 2.4V, VDD = 5V 24 mA
Input Capacitance 7pF
Input Pull-Up Resistor 500 kΩ
Clock Output I mp edance 25 Ω

TA = 0°C to +70°C, VDD = 3.3V ±5% or 5V±10%

AC Electrical Characteristics:

Symbol Parameter T est Condition Min. Typ. M ax. Unit

f

IN

f

OUT

t

R

t

F

t

OD

t

ID

t

JCYC

Input Frequency Input Clock 8 28 MHz
Output Frequency Spread Off 8 28 MHz
Output Rise Time 15-pF load, 0.8V–2.4V 2 5 ns
Output Fall Time 15-pF load, 2.4 –0.8V 2 5 ns
Output Duty Cycle 15-pF load 40 60 %
Input Duty Cycle 40 60 %
Jitter, Cycle-to-Cyc le 250 300 ps
Harmonic Reduction f

= 20 MHz, thir d harmonic

out

8dB
measured, reference board,
15-pF load

Note:

2. Inputs FS1:2 have a pull-up resistor; Input SSON# has a pull-down resistor.

V
V

6

W182

Application Information

Recommended Circuit Configuration

For optimum performance in system applications the power
supply decoupli ng scheme sho wn in Figure 4 should be used .

decoupling is important to both reduce phase jitter and

V

DD

EMI radiation. The 0.1-µF decoupling capacitor should be
placed as close to the V

Xtal Connec tio n or Re f e ren ce Input

pin as possible, otherwise the in-

DD

1

Xtal Connection or NC

2

W182

3

GND

4

5

6

7

3.3V or 5V System Supply

Figure 4. Recommended Circuit Configuration

14
13
12
11

10

9
8

creased trace inductance will negate its decoupling capability.
The 10-µF decoupling capacitor shown should be a tantalum
type. For further EMI protection, the V
made via a ferrite bead, as shown.

connection can be

DD

Recommended Board Layout

Figure 5 shows a recommended a 2-layer board la yout.

C3

µF

0.1

R1

Clock
Output

C1

µF

0.1

FB

C2

µF Tantalum

10

Xtal Connec tion or Reference Input

Xtal Connection or

Power Supply Input

(3.3V or 5V)

Ordering Information

Ordering Code

W182
W182-5

C1, C3 =

NC

G

G

FB

C2

C3

G

C1

G

G

R1

Figure 5. Recommended Board Layout (2-Layer Board)

Package

Name

Packag e Type

G 14-Pin Plastic SOIC (150-mil)

High-frequency supply decoupling
capacitor (0.1-

C2 =

Common supply low frequency
decoupling capacitor (10­recommended).

R1 =

Match value to line impedance

FB

=

Ferrite Bead

G

=

Via To GND Plane

Clock Output

µF recommended).

µF tantalum

Document #: 38-00789-A

7

Package Diagram

W182

14-Pin Small Outline Integrat ed Circuit (SOIC, 150-mil )

© Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it conv ey or imply any lice nse under patent or other rights. Cypress Semicondu ctor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.