Page 1
PRELIMINARY
Frequency Generator for Integrated Core Logic
W147G
Cypress Semiconductor Corporation
• 3901 North First Street • San Jose • CA 95134 • 408-943-2600
October 13, 1999, rev. **
Features
• Maximized EMI suppression usi ng Cypress’s Spread
Spectrum Technology
• Low jitter and tight ly controlled clock skew
• Highly int egrated device pr oviding clocks required for
CPU, core logic, and SDRAM
• Three copies of CPU clock at 66/100 MHz
• Nine copies of 100-MHz SDRAM clocks
• Eight copies of PCI clock
• T wo copies of synchronous APIC c lock
• T wo copies of 4 8-MHz cloc k (non-spre ad spectrum) optimized for USB refer ence input and video dot clock
• T w o copies of 66-MHz fixed cl ock
• One copy of 14.31818-M Hz reference clock
• Power-down control
•I
2
C interface for turning off unused clock s
Key Specifications
CPU, SDRA M Ou t p ut s C y cl e -to - C yc le Ji tt er:............ ..2 5 0 ps
APIC, 48MHz, 3V66, PCI Output s
Cycle-to-Cycle Jitter: ...................................................500 ps
APIC, 48MHz, SDRAM Output Skew: .........................250 ps
CPU, 3V66 O ut p u t Skew: ............... ............. ............ ....1 7 5 p s
PCI Output Skew: ........................................................500 ps
CPU to SDRAM Skew (@ 100 MHz):.................4.5 to 5.5 ns
CPU to 3V6 6 Skew (@ 66 MH z ): . ............ ..........7.0 to 8. 0 n s
3V66 to PCI Skew (3V66 lead):..........................1.5 to 3.5 ns
PCI to AP IC S kew: . ... .. ............ ...................... ............ .±0.5 ns
T able 1. Pin Selectable Functions
SEL1 SEL0 Function
0 0 Three-state
01 Test
1 0 66-MHz CPU
1 1 100-MHz CPU
Block Diagram
Pin Configuration
VDDQ3
VDDQ2
CPU2_ITP
PCI0_ICH
XT A L
PLL REF FREQ
PLL 1
X2
X1
REF/APICDIV
PCI1:7
USB
DOT
PLL2
OSC
VDDQ3
I2C
SDATA
Logic
SCLK
3V66_0:1
CPU0:1
SEL0:1
APIC0:1
Divider,
Delay,
and
Phase
Control
Logic
7
2
VDDQ3
2
2
DCLK
SDRAM0:7
8
PWRDWN#
REF/APICDIV
VDDQ3
X1
X2
GND
GND
3V66_0
3V66_1
VDDQ3
VDDQ3
PCI0_ICH
PCI1
PCI2
GND
PCI3
PCI4
GND
PCI5
PCI6
PCI7
VDDQ3
VDD3
GND
GND
W147G
GND
APIC0
APIC1
VDDQ2
CPU0
VDDQ2
CPU1
CPU2_ITP
GND
GND
SDRAM0
SDRAM1
VDDQ3
SDRAM2
SDRAM3
GND
SDRAM4
SDRAM5
VDDQ3
SDRAM6
SDRAM7
GND
DCLK
VDDQ3
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
32
31
30
29
USB
DOT
VDDQ3
SEL0
PWRDWN#
SCLK
SDATA
SEL1
Page 2
W147G
PRELIMINARY
2
Pin Definitions
Pin Name Pin No.
Pin
T ype Pin Description
REF/APICDIV 1 I/O
Reference Cloc k:
3.3V 14.318-MHz clock output. This pin doubles as th e select
strap fo r APIC clock fre quency. If stra pped LOW during power up , APIC clock runs
at half PCI clock speed. Otherwise, APIC clocks run at PCI clock speed.
X1 3 I
Crystal Input:
This pin has dual functi ons. It can be used as an ext ernal
14.318-MHz crystal connection as an external reference frequency input.
X2 4 I
Crystal Output:
An input connection f or an external 14.318-MHz crystal. If using
an external reference, thi s pin must be left unconnected.
PCI0_ICH,
PCI1:7
11, 12, 13, 15,
16, 18, 19. 20
O
PCI Clock 0 through 7:
3.3V 33-MHz PCI clock outputs. PCI 1:7 can be i ndividually
turne d of f vi a I
2
C interface.
3V66_0:1 7, 8 O
66-MHz Clock Outp ut:
3.3V fix ed 66-MHz clock.
USB 25 O
USB Clock Output:
3.3V fixe d 48-MHz, non- spread sp ectrum USB cloc k outputs .
DOT 26 O
Dot Clock Output:
3.3V 48-MHz, non-spread spectrum signal.
SEL0:1 28, 29 I
Clock Function Selection pins:
LVTTL-compatible input to select device func-
tions. See Table 1 for det ail ed descriptions.
PWRDWN# 32 I
Power Down Control:
LVTTL-compati ble asynchronous input that places the de-
vice in power- down mode when held LOW.
CPU2_ITP,
CPU0:1
49, 52, 50 O
CPU Clock Outputs:
Clock output s for the host bus interface and inte grated test
port. Output frequen cies run at 66 MHz o r 100 MHz dependi ng on the conf iguration
of SEL0:1. Voltage swing set by V
DDQ2
.
SDRAM0:7,
DCLK
46, 45, 43, 42,
40, 39, 37, 36, 34O
SDRAM Clock Outputs:
3.3V outputs running at 100 MHz. SDRAM0:7 can be
individually turned off via I
2
C interface.
APIC0:1 55, 54 O
Sychronous APIC Clock Outputs:
Clock outputs running di vide synchronous
with the PCI clock out puts. Output freque ncy is controlled by the st rap option on
REF. Voltage swing set by V
DDQ2
.
SDATA 30 I/O Data pin for I
2
C circuitry .
SCLK 31 I Clock pin for I
2
C circuitry.
VDDQ3 2, 9, 10, 21, 27,
33, 38, 44
P
3.3V Pow er Connection:
Po wer supply for SDRAM output buffers, PCI out put
buffe rs, 3V66 o utput b u ff ers, reference output buff ers, and 48-MHz output buf fer s .
Connect to 3.3V.
VDD3 22 P
3.3V Pow er Connection:
Po wer supply for cor e logi c, PLL circuitry. Connect to
3.3V.
VDDQ2 51, 53 P
2.5V Power Conne ction:
Powe r supply f or IO APIC and CPU output bu ff ers. Con-
nect to 2.5V or 3.3V.
GND 5, 6, 14, 17, 23,
24, 35, 41, 47,
48, 56
G
Ground Connections:
Connect all ground pins to the common system ground
plane.
Page 3
W147G
PRELIMINARY
3
Overview
The W147G is a highly integrated frequency timing generator,
supplying all the required clock sources for an Intel® architecture platform using graphics in tegrated core logic.
Functional Description
I/O Pin Operation
REF/APICDIV is a dual purpose l/O pin. Upon power-up the
pin acts as a logic input. If the pin is strapped to a LOW state
externally, APIC cloc k outputs will run divide synchronously at
half PCI clock speed. If it is pulled HIGH, APIC clock will run
synchronous to PCI cloc ks. An external 10-kΩ s trapp ing r esi stor should be used. Figure 1 shows a suggested method for
strapping resistor connections.
After 2 ms, the pin becomes an output. Assuming the power
supply has stabilized by then, the specified output frequency
is delivered on the pins. If the power supply has not yet
reached full value, output freq uency initiall y m ay be below target but will increase to target once supply voltage has stabilized. In either case, a short output clock cycle may be produced from the CPU clock outputs when the outputs are
enabled.
Pin Selectable Function s
Table 1 outlines the device functions selectable through
SEL0:1. Specific outputs available at each pin is detailed in
Table 2 below. The SEL0 pin requires a 220Ω pull-up resistor
to 3.3V for the W147G to sense the maximum host bus frequency of the processor and configure itself accordingly.
Notes:
1. APIC clock frequency determined by the strap option on the REF/APICDIV input pin.
2. Provided for board level “bed of nails” testing.
3. “Normal” mode of operation.
4. TCLK is a test clock overdriven on the XTAL_IN input during test mode.
5. Required for DC output impedance verification.
6. Range of reference frequency allowed is: min. = 14.316 MHz, nominal = 14.31818 MHz, max. = 14.32 MHz.
7. Frequency accuracy of 48 MHz must be +167 PPM to match USB default.
Power-on
Reset
Timer
Output Three-state
Data
Latch
Hold
QD
W147G
V
DD
Clock Load
10 k
Ω
Output
Buffer
(Load Option 1)
10k
Ω
(Load Option 0)
Output
Low
Output Strapping Resistor
Series Termination Resistor
Figure 1. Input Logic Selection Through Resistor Load Option
Table 2. CK Whitney Truth Table
SEL1 SEL0 CPU SDRAM 3V66 PCI 48MHz REF APIC
[1]
Notes
0 0 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z 2
0 1 TCLK/2 TCLK/2 TCLK/3 TCLK/6 TCLK/2 TCLK TCLK/6 4, 5
1 0 66 MHz 100 MHz 66 MHz 33 MHz 48 MHz 14.318 MHz 16.67 MHz 3, 6, 7
1 1 100 MHz 100 MHz 66 MHz 33 MHz 48 MHz 14.318 MHz 16.67 MHz 3, 6, 7
Page 4
W147G
PRELIMINARY
4
Offsets Among Clock Signal Groups
Figure 2 and Figur e 3 represe nt the pha se rel ation shi p amon g
the different groups of clock outputs from W147G when it is
providing a 66-MHz CPU clock and a 100-MHz CPU clock,
respectively. It should be noted that when CPU clock is operating at 100 MHz, CPU clock output is 180 degrees out of
phase with SDRAM clock outputs.
CPU 66-MHz
SDRAM 100-MHz
3V66 66-MHz
PCI 33-MHz
REF 14.318-MHz
USB 48-MHz
APIC 33-MHz
0 ns
CPU 66 Period
SDRAM 100 Period
Hub-PCI
Figure 2. Group Offset W aveforms (66-MH z CPU Clock)
40 ns30 ns20 ns10 ns
CPU 100-MHz
SDRAM 100-MHz
3V66 66-MHz
PCI 33-MHz
REF 14.318-MHz
USB 48-MHz
APIC 33-MHz
0 ns
SDR A M 10 0 P e riod
CPU 100 Period
Hub-PCI
Figure 3. Group Offset Waveforms (100-MHz CPU Clock)
40 ns30 ns20 ns10 ns
Page 5
W147G
PRELIMINARY
5
Power Down Control
W147G provides one PWRDWN# signal t o place the devi ce in lo w-power mode . In lo w-power mode , the PLLs are turned off and
all clock outputs are driven LOW.
Notes:
8. Once the PWRDWN# signal is sampled LOW for two consecutive rising edges of CPU clock, clocks of interest should be held LOW on the next HIGH-to-LOW
transition.
9. PWR_DWN# is an asynchronous input and metastable conditions could exist. This signal is synchronized inside W147G.
10. The shaded sections on the SDRAM, REF, and USB clocks indicate “don’t care” states.
11. Diagrams shown with respect to 100 MHz. Similar operation when CPU is 66 MHz.
T able 3. W147G Maximum Allowed Current
W147
Condition
Max. 2.5V supply consumption
Max. discrete cap loads,
V
DDQ2
= 2.625V
All static inputs = V
DDQ3
or V
SS
Max. 3.3V supply consumpti on
Max. discrete cap loads
V
DDQ3
= 3.465V
All static inputs = V
DDQ3
or V
SS
Powerdown Mode
(PWRDWN# = 0)
100 µA 200 µA
Full Active 66 MHz
SEL1,0 = 10 (PWRDWN# =1)
70 mA 280 mA
Full Active 100 MHz
SEL1,0 =11 (PWRDWN# = 1)
100 mA 280 mA
1 2
Center
0ns 25ns 50ns 75ns
VCO Internal
CPU 100MHz
3V66 66MHz
PCI 33MHz
APIC 33MHz
PwrDwn
SDRAM 100MHz
REF 14.318MHz
USB 48MHz
Figure 4. W147G PWRDWN# Timing Diagram
[8, 9, 10, 11]
Page 6
W147G
PRELIMINARY
6
Spread Sp ectrum Clocking
The device generates a clock that is frequency modulated in
order to increase the bandwidth that it occu pies. By increas ing
the bandwidth of the fundamental and its harmonics, the amplitudes of the radiated electromagnetic emissions are reduced. This effect is depicted in Figure 5.
As shown in Figure 5, a harmonic of a modulated clock has a
much low er amplitude th an that of an un modulated si gnal. The
reduction in amplitude is dependent on the harmonic number
and the frequency deviation or spread. The equation for the
reduction is
dB = 6.5 + 9*log
10
(P) + 9*log10(F)
Where P is the perce nta ge of de viati on and F is the frequen cy
in MHz where the reduction is measured.
The output clock is modulated with a waveform depicted in
Figure 6. This waveform, as discussed in “Spread Spectrum
Clock Generation f or the Reducti on of Radiated Emissio ns” by
Bush, Fessler, and Hardin produces the maximum reduction
in the amplitude of radiated electromagnetic emissions. The
deviation selected for this chip is –0.5% of the selected frequency. Figure 6 details the Cypress spreading pattern.
Cypress does off er optio ns with more spr ead and great er EMI
reduction. Contact your local Sales representative for details
on these devices.
Spread Spectrum clocking is activated or deactivated by selecting the appropriate value for bit 3 in data byte 0 of the I
2
C
data stream. Refer to page 8 for more details.
Spread
Spectrum
Enabled
EMI Reduction
Spread
Spectrum
Non-
Figure 5. Typical Clock and SSFTG Comparison
MAX.
MIN.
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
FREQUENCY
Figure 6. Typica l Modulation Profile
Page 7
W147G
PRELIMINARY
7
Serial Data Interface
The W147G features a two-pin, serial data interface that can
be used to configure i nternal register settings that control pa rticular device functions.
Data Protocol
The clock dri ver serial protocol accepts onl y block writes from
the controller. The bytes must be accessed in sequenti al order
from lowe st to hi ghest by te with t he abilit y to s top afte r any
complete byte has been transferred. Indexed bytes are not allowed.
A bloc k write be gins wit h a sla ve address an d a write conditi on.
After the command code the core logic issues a byte count
which describes how many more bytes will follow in the message. If the host had 20 bytes to send, the first byte would be
the number 20 (14h), followed b y the 20 bytes of data. The b yte
count ma y not be 0. A bl ock write command is allowed to tr ans-
fer a maximum of 32 data bytes. The slave receiver address
for W147G is 11010010. Figure 7 sho ws an e xample of a bloc k
write.
The command code and the byte count bytes are required as
the first tw o b ytes of an y tr ans fe r . W147G e x pects a comm and
code of 0000 0000. The byte count byte is the number of additional bytes required for the transfer, not counting the command code and byte count bytes. Additionally, t he byte count
byte is required to be a minimum of 1 byte and a maxi m um of
32 bytes to satisfy the above requirement. Table 4 shows an
example of a possible byte count value.
A transfer is considered valid after the acknowledge bi t corresponding to the b yte count is read by the controller. The command code and byte count bytes are ignored by the W147G.
However, these bytes must be included in the data write sequence to maintain proper byte allocation.
Notes:
12. The acknowledgment bit is returned by the slave/receiver (W147G).
13. Data Bytes 3 to 7 are reserved.
1 bit 7 bits 1 1 8 bits 1
Start bit Slave Address R/W Ack Com mand Code Ack Byte Count = N
Ack Data Byte 1 Ack Data Byte 2 Ack ... Data Byte N Ack Stop
1 bit 8 bits 1 8 bits 1 8 bits 1 1
Figure 7. An Example of a Block Write
[12]
T able 4. Example of Possible Byte Count Value
Byte Count Byte Notes
MSB LSB
0000 0000 Not allowed. Must have at least one byte.
0000 0001 Data for functional and frequency select register (currently byte 0 in spec)
0000 0010 Reads first two bytes of data. (byte 0 then byte 1)
0000 0011 Reads first three bytes (byte 0, 1, 2 in order)
0000 0100 Reads first four bytes (byte 0, 1, 2, 3 in order)
0000 0101 Reads first five bytes (byte 0, 1, 2, 3, 4 in order)
[13]
0000 0110 Reads first six b ytes (byte 0, 1, 2, 3, 4, 5 in order)
[13]
0000 0111 Reads first seven bytes (byte 0, 1, 2, 3, 4, 5, 6 in order)
0010 0000 Max byte count supported = 32
T able 5. Serial Data Interface Control Func ti ons Sum mary
Control Function Description Common Application
Output Disable Any individual clock output(s) can be disabled.
Disabled out puts are actively hel d LOW.
Unused outputs are disabl ed to reduce EMI and system power. Examples are cloc k outputs to unused
PCI slots.
Spread Spectrum
Enabling
Enables or dis ables spread spectrum cl ocking. For EMI reduction.
(Reserved) Reserved function for future de vice re vision or pro-
duction device testing.
No user appli cation. Re gister bit must be written as 0.
Page 8
W147G
PRELIMINARY
8
W147G Serial Configuration Map
1. The serial bit s will be read by the cloc k driver in the fol lowing
order:
Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0
2. All unused register bits (reserved and N/A) sho uld be written to a “0” level.
3. All register bits labeled “Initialize to 0" must be written to
zero during initialization. Failure to do so may result in higher than normal operating cur rent.
4. Only Byte 0, 1 and 2 are defined in W147G Byte 3 to Byte
7 are reserved and must be writte n to “zero.”
Note:
14. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be configured at power-on and are not expected to be
configured during the normal modes of operation.
Byte 0: Control Regist er (1 = Enable, 0= Disable)
[14]
Bit Pin# Name Pin Description
Bit 7 - Reserved (Active/Inactive)
Bit 6 - Reserved (Active/Inactive)
Bit 5 - Reserved (Active/Inactive)
Bit 4 - Reserved (Active/Inactive)
Bit 3 - Spread Spectrum (1=On/0=Off) ( Active/Inacti ve)
Bit 2 26 DOT (Active/Inactive)
Bit 1 25 USB (Active/Inactive)
Bit 0 49 CPU2_ITP (Active/Inactive)
Byte 1: Control Regist er (1 = Enable, 0= Disable)
[14]
Bit Pin# Name Pin Description
Bit 7 36 SDRAM7 (Active/Inactive)
Bit 6 37 SDRAM6 (Active/Inactive)
Bit 5 39 SDRAM5 (Active/Inactive)
Bit 4 40 SDRAM4 (Active/Inactive)
Bit 3 42 SDRAM3 (Active/Inactive)
Bit 2 43 SDRAM2 (Active/Inactive)
Bit 1 45 SDRAM1 (Active/Inactive)
Bit 0 46 SDRAM0 (Active/Inactive)
Byte 2: Control Regist er (1 = Enable, 0= Disable)
[14]
Bit Pin# Name Pin Description
Bit 7 20 PCI7 (Active/Inactive)
Bit 6 19 PCI6 (Active/Inactive)
Bit 5 18 PCI5 (Active/Inactive)
Bit 4 16 PCI4 (Active/Inactive)
Bit 3 15 PCI3 (Active/Inactive)
Bit 2 13 PCI2 (Active/Inactive)
Bit 1 12 PCI1 (Active/Inactive)
Bit 0 - Reserved (Active/Inactive)
Page 9
W147G
PRELIMINARY
9
DC Electr i cal C h ar acteristics
DC parameters must be sustainable und er st eady state (DC) conditions .
Note:
15. Input Leakage Current does not include inputs with pull-up or pull-down resistors.
Absolute Maximum DC Power Supply
Parameter Description Min. Max. Unit
V
DD3
3.3V Core Supply Voltage –0.5 4.6 V
V
DDQ2
2.5V I/O Supply Voltage –0.5 3.6 V
V
DDQ3
3.3V Supply Voltage –0.5 4.6 V
T
S
Storage Temperature –65 150 °C
Absolute Maximum DC I/O
Parameter Description Min. Max. Unit
V
ih3
3.3V Input High Voltage –0.5 4.6 V
V
il3
3.3V Input Low Voltage –0.5 V
ESD prot. Input ESD Protection 2000 V
DC Operating Requirements
Parameter Description Condition Min. Max. Unit
V
DD3
3.3V Core Supply Voltage 3.3V±5% 3.135 3.465 V
V
DDQ3
3.3V I/O Supply Voltage 3.3V±5% 3.135 3.465 V
V
DDQ2
2.5V I/O Supply Voltage 2.5V±5% 2.375 2.625 V
V
DD3 =
3.3V±5%
V
ih3
3.3V Input High Voltage V
DD3
2.0 VDD+0.3 V
V
il3
3.3V Input Low Voltage VSS–0.3 0.8 V
I
il
Input Leakage Curr ent
[15]
0<Vin<V
DDQ3
–5+5µA
V
DDQ2 =
2.5V±5%
V
oh2
2.5V Output High Voltage Ioh=(–1 mA) 2.0 V
V
ol2
2.5V Output Low Voltage Iol=(1 mA) 0.4 V
V
DDQ3 =
3.3V±5%
V
oh3
3.3V Output High Voltage Ioh=(–1 mA) 2.4 V
V
ol3
3.3V Output Low Voltage Iol=(1 mA) 0.4 V
V
DDQ3 =
3.3V±5%
V
poh3
PCI Bus Output High Voltage Ioh=(–1 mA) 2.4 V
V
pol3
PCI Bus Output Low Voltage Iol=(1 mA) 0.55 V
C
in
Input Pin Capacitance 5 pF
C
xtal
Xtal Pin Capacitance 13.5 22.5 pF
C
out
Output Pin Capacitance 6 pF
L
pin
Pin Inductance 0 7 nH
T
a
Ambient Temperature No Airflow 0 70 °C
Page 10
W147G
PRELIMINARY
10
AC Electrical Characteristics
TA = 0°C to +70°C, V
DDQ3
= 3.3V±5%, V
DDQ2
= 2.5V±5%
f
XTL
= 14.31818 MHz
Spread Spectrum functi on turned off
AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the
clock o utput.
[16]
Notes:
16. Period, jitter, offset, and skew measured on rising edge at 1.25 for 2.5V clocks and at 1.5V for 3.3V clocks.
17. T
HIGH
is measured at 2.0V for 2.5V outputs, 2.4V for 3.3V outputs.
18. T
LOW
is measured at 0.4V for all outputs.
19. The time specified is measured from when V
DDQ3
achieves its nominal operating level (typical condition V
DDQ3
= 3.3V) until the frequency output is stable and
operating within specification.
20. T
RISE
and T
FALL
are measured as a transition through the threshold region Vol = 0.4V and Voh = 2.0V (1 mA) JED EC specification.
Parameter Description
66.6-MHz Host 100-MHz Host
Unit NotesMin. Max. Min. Max.
T
Period
Host/CPUCLK Peri od 15.0 15.5 10.0 10.5 ns 16
T
HIGH
Host/CPUCLK High Time 5.2 N/A 3.0 N/A ns 19
T
LOW
Host/CPUCLK Low Time 5.0 N/A 2.8 N/A ns 20
T
RISE
Host/CPUCLK Rise Time 0.4 1.6 0.4 1.6 ns
T
FALL
Host/CPUCLK Fal l Ti m e 0.4 1.6 0.4 1.6 ns
T
Period
SDRAM CLK Period 10.0 10.5 10.0 10.5 ns 16
T
HIGH
SDRAM CLK High Time 3.0 N/A 3.0 N/A ns 19
T
LOW
SDRAM CLK Low Time 2.8 N/A 2.8 N/A ns 20
T
RISE
SDRAM CLK Rise Time 0.4 1.6 0.4 1.6 ns
T
FALL
SDRAM CLK Fall Time 0.4 1.6 0.4 1.6 ns
T
Period
APIC CLK Period 60.0 64.0 60.0 64.0 ns 16
T
HIGH
APIC CLK High Time 25.5 N/A 25.5 N/A ns 19
T
LOW
APIC CLK Low Time 25.3 N/A 25.3 N/A ns 20
T
RISE
APIC CLK Rise Time 0.4 1.6 0.4 1.6 ns
T
FALL
APIC CLK Fall Time 0. 4 1.6 0.4 1.6 ns
T
Period
3V66 CLK Period 15.0 16.0 15.0 16.0 ns 16, 18
T
HIGH
3V66 CLK High Time 5.25 N/A 5.25 N/A ns 19
T
LOW
3V66 CLK Low Time 5.05 N/A 5.05 N/A ns 20
T
RISE
3V66 CLK Rise Time 0.5 2.0 0.5 2.0 ns
T
FALL
3V66 CLK Fall Time 0.5 2.0 0.5 2.0 ns
T
Period
PCI CLK Period 30.0 N/A 30.0 N/A ns 16, 17
T
HIGH
PCI CLK High Time 12.0 N/A 12.0 N/A ns 19
T
LOW
PCI CLK Low Time 12.0 N/A 12.0 N/A ns 20
T
RISE
PCI CLK Rise Time 0.5 2.0 0.5 2.0 ns
T
FALL
PCI CLK Fall Time 0.5 2.0 0.5 2.0 ns
tp
ZL
, tp
ZH
Output Enable Delay (All outputs) 1.0 10.0 1.0 10.0 ns
tp
LZ
, tp
ZH
Output Disable Delay (All outputs) 1.0 10.0 1.0 10.0 ns
t
stable
All Clock Stabilizati on from Power- Up 3 3 ms
Page 11
W147G
PRELIMINARY
11
Intel is a registered trademark of Intel Corporation.
Document #: 38-00820
Group Skew and Jitter Limits
Output Group Pin-Pin Skew Max Cycle-Cycle Jitter Duty Cycle Nom Vdd
Skew, Ji tter
Measure Point
CPU 175 ps 250 ps 45/55 2.5V 1.25V
SDRAM 250 ps 250 ps 45/55 3.3V 1.5V
APIC 250 ps 500 ps 45/55 2.5V 1.25V
48MHz 250 ps 500 ps 45/55 3.3V 1.5V
3V66 175 ps 500 ps 45/55 3.3V 1.5V
PCI 500 ps 500 ps 45/55 3. 3V 1.5V
REF N/A 1000 ps 45/55 3.3V 1.5V
Clock Out pu t Wave
2.5V Clock in g
3.3V Clocking
Test Point
Test Load
T
PERIOD
Duty Cycle
T
HIGH
2.0
1.25
0.4
T
LOW
T
RISE
T
FALL
T
LOW
T
RISE
T
FALL
T
PERIOD
Duty Cycle
T
HIGH
2.4
1.5
0.4
Output
Buffer
Interface
Interface
Figure 8. Output Buffer
Ordering Information
Ordering Code
Package
Name
Package Type
W147G H 56-pin SSOP (300 mils)
Page 12
W147G
PRELIMINARY
© Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it con vey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
Package Diagram
56-Pin Shrink Small Outline Package (SSOP, 300 mils)
Summary of nominal dimensions in inches:
Body Width: 0.296
Lead Pitch: 0.025
Body Length: 0.625
Body Height: 0.102
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