Datasheet VV5300 Datasheet (Vision)

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VV5300 Sensor

Integrated CMO S Image Sensor with on-chip ADC.

DISTINCTIVE CHARACTERISTICS

• Standard image format: 160 x 120

• 164 x 124 pixel array

• Variable frame rate (2 fps - 60 fps)

• On-chip 8-bit A/D convertor

• 8-bit and 4-bit conversi on modes

• 8-wire and 4-wire parallel data output modes

GENERAL DESCRIPTION

VV5300 is a highly-int egrated CMOS image sensi ng device. In addition to a 160 x 120 pixel image sensor array, the device includes on-chip circuitry to drive and sense the array.

The output stage of the sensor contains a successive approximation circuit which performs analogue-todigital conversion of the photodiode array to produce 8-bit or 4-bit pixel data.

• Reduced flicker operation with 50Hz and 60Hz mains frequencies

• 2 serial data output modes

• Automatic exposure and gain controller

• Automatic black level calibration

• Options selectable via serial interface

VV5300 features electronic exposure and gain control over a wide range, enabling the use of a single fixed-aperture lens.

A bi-directional 2-wire serial communications inter-

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face allows the device to be configured and its operating status monitored. The status information may also be multiplexed onto the digital output bus.

CLKI

CLKO

VBLTW

VRT

VCM

VREF2V5

VPED/VBG

VCDS

The primary image size is 160 x 120 but border pixels/lines can be enabled to give an effective image size of 164 x 124.

BLOCK DIAGRAM

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VERTICAL

SHIFT

CLOCK

CIRCUIT

ANALOG

VOLTAGE

REFS.

PHOTO DIODE ARRAY

SAMPLE & HOLD

HORIZONTAL SHIFT REGISTER

A/D CONVERTOR

DIGITAL

CONTROL

LOGIC

IMAGE

FORMAT

SDA

SCL

D[7:0]

SIN

FST

QCK

Pixel Resolution 160 x 120

Pixel Size 12µm x 12µm

Array Size 1.92mm x 1.44mm

Power Supply 5v +/-10%

Min.illumination 0.1 Lux

Power 175 mW (Typ.)

S/N 36 dB (Typ.)

Exposure control Automatic (25000:1)

Temperature -20

C to +70oC

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VV5300 Sensor

Main Features

On-chip 8-bit successive approximation analogue-to-digital convertor with 8-wire, 4-wire parallel and two serial data output modes.

The default image format is 160x 120. Extra border pixel/lines can be enabled to give an image size of 164 x 124. Digital pixel data coding assigns 10 frame sync periods.

The VV5300 frame rates can be integer multiples of the mains supply frequencies used worldwide, i.e. 50Hz and 60Hz. This ensures reduced flicker operation of the sensor

All VV5300 operating modes and system status information can be accessed via a two wire bidirectional serial interface.

VV5300 features an automatic electronic exposure algorithm that enables the use of a single fixed-aperture lens. Automatic gain control enhances operation under low light conditions.

Automatic black level control ensures consistent picture quality across the whole range of operating conditions. Extensive use of automated operation and on chip references means that only a small number of passive components are needed to realise a complete video camera.

as black and F0H as white. Other codes specify line sync and

On-chip voltage references simplifies the support circuitry and maintains device stability over a wide range of operating conditions.

This device is also available with bayer pattern colour filters (VV6300), see seperate datasheet.

Exposure Control

With automatic exposure control selected VV5300 uses a complex algorithm to automatically set the exposure value for the current sc ene. When comb ined with clock co ntrol and gain c ontrol the VV5 300 can operate over a very wide range of illumination levels.

Where direct control of the exposure is required the exposure value can be directly selected by writing to the appropriate registers via the serial interface.

Clock Control

The system clock can be divided down internally to extend the operating range of VV5300 by allowing longer exposure times. The clock divisor can be varied from 2 to 16 in times two steps i.e there are 4 different values. Note: changing the system clock divisor modifies the pixel and frame rate.

Gain Control

If the image is to dark and the exposur e is alrea dy clos e to its m aximum, VV5300 wi ll incr ease the system gain. Gain can be varied from x1 to x8 in times two steps i.e there are 4 different gain settings. If the scene is too dark and integration period has almost reached its maximum value the gain value is incremented by one step (i.e. doubled). If the gain setting changes the exposure value is automatically set to half the maximum integration period. The exposure controller then increases the exposure value as necessary.

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Similarly if the image is too bright and the integra tion period is sh ort then gain will be redu ced by one step (i.e. divide by two). As before, the exposure value is set to half the maximum integration period. The exposure controller can then adjust the exposure value as necessary to provide a correctly exposed image.

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VV5300 Sensor

Device Pinout

CLKI

CLKO

SDA

SCL

VSS

DVSS

AUTOLOADB

VREG

VDD

31 32 33 34

35 36 37 38 39

40 41 42

VV5300

24 23 22 21 20 1930 29 28 27 26 25

18 NC 17 QCK 16 FST 15 SIN 14 VDD 13 DVDD 12

AVDD

VDD

VSS

D[7]

D[6]

D[5]

D[4]

D[3]

D[2]

D[1]

D[0]

VSS

Pad List

12345643 44 45 46 47 48

VRT

VCDS

TEST

HPIX

AVSS

Viewed from above

VBLOOM

VBLTW

VBG

VREF2V7

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Pin Name Type Description

POWER SUPPLIES 6 AVSS GND Analogue ground 9 AVDD PWR Analogue power

13 DVDD PWR Digital power 14 VDD PWR Power 19 VDD PWR Power 20 VSS GND Ground

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29 VSS GND Ground 30 VDD PWR Power 35 VSS GND Ground 36 DVSS GND Ground

ANALOGUE OUTPUTS

1 VRT IA Pixel reset voltage

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VV5300 Sensor

Pin Name Type Description

2 VCDS IA Voltage reference 3 TEST IA Analogue test

40 VREG ΙΑ Reference voltage input 44 VBLOOM ΟΑ Internal reference voltage 45 VBLTW IA Bitline test white reference 46 VBG OA Internally generated bangap reference voltage

47 VREF2V5 ΟΑ Internally generated reference voltage 2.5V

16 FST OD Frame start. Synchronises external image

1.22V

DIGITAL OUTPUTS

capture.

17 QCK OD Pixel sample clock. Qualifies video output for

external image capture. 25-28 D[3:0] BI↓ Parallel 4-bit databus. D[0] serial data bus. 21-24 D[7:4] OD↓ Parallel 4-bit databus.

DIGITAL CONTROL SIGNALS 34 SCL BI↑ Serial bus clock (bidirectional, open drain) 33 SDA BI↑ Serial bus data (bidirectional, open drain) 37 AUTOLO

ADB

38 CE ID↑ Chip enable

4HPIXID↓Hold pixel value.

15 SIN ID↓ Frame Timing reset(Soft reset)

ID↓ Enable autoload from EEPROM

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31 CLKI ID Oscillator input. 32 CLKO OD Oscillator output.

SYSTEM CLOCKS

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OA - Analogue output A - Analogue input OD - Digital output D - Digital input BI - Bidirection al ID↑ − Digital input with internal pull-up OD↓ − Digital output with internal pull-down

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VV5300 Sensor

SPECIFICATIONS

Package Details

14.22

Viewed from below

Spectral Response

0.51

1.56

1.016 PITCH

1.0

2.16 PIN 1

13.7

0.55

0.53

The optical array is centred within the

package to a tolerance of ± 0.2 mm, and rotated no more than ± 0.5

Tolerances on package dimensions ±10% Glass lid placement is controlled so that no

package overhang exists. All dimensions in millimetres +/-

Glass Lid

Die

Base

Viewed from side

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0.5

0.86

0.8

0.6

0.4

0.2

Normalised Response

400

500

600

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Wavelength nm

700

800

900

1000

1100

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VV5300 Sensor

Absolute Maximum Ratings

Parameter Value

Supply Voltage -0.5 to +7.0 volts Voltage on other input pins -0.5 to V Temperature under bias -15 Storage Temperature -30 Maximum DC TTL output Current Magnitude 10mA (per o/p, one at a time, 1sec. duration)

Note: Stresses exceeding the Absolute Maximum Ratings may induce failure. Exposure to absolute

maximum ratings for extended periods may reduce reliability. Functionality at or above these conditions is not implied.

C to 85oC

C to 125oC

+ 0.5 volts

DC Operating Conditions

Symbol Parameter Min. Typ. Max. Units Notes

Operating supply voltage 4.75 5.0 5.25 Volts

Input Voltage Logic “1” 2.4 VDD+0.5 Volts Input Voltage Logic “0” -0.5 0.8 Volts Ambient Operating Temperature 0 70

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C Still air

AC Operating Conditions

Symbol Parameter Min. Typ. Max. Units Notes

CKIN

SCL

Crystal frequency 14.318 MHz 1 Serial Data Clock 100 KHz 2

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1. Pixel Clock =

2. Serial Interface clock must be generated by host processor.

Electrical Characteristics

Symbol Parameter Min. Typ. Max. Units Notes

DCC

ADD

CKIN

Digital supply current Analog supply current

Typical conditions, VDD = 5.0 V, TA = 27oC

10 mA 1 25 mA 1

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VV5300 Sensor

Symbol Parameter Min. Typ. Max. Units Notes

REF2V7

ILK

1. Digital and Analogue outputs unloaded - add output current.

Overall supply current

Internal voltage reference 2.700 Volts Internal bandgap reference 1.22 Volts

Output Voltage Logic “1” 2.4 Volts I Output Voltage Logic “0” 0.6 Volts I

Input Leakage current

Typical conditions, VDD = 5.0 V, TA = 27oC

-1 µA

35 mA 1

1 µA

VIH on input

VIL on input

= 2mA

= -2mA

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VV5300 Sensor

Operating Characteristics

Parameter min. typ. max. units Note

Dark Current Signal 50 mV/Sec Modal pixel voltage due to photodiode leak-

age under zero illumination with Gain=1

= (Vt1 - Vt2)/(t1-t2), calculated over

dark

two different frames

Sensitivity 6 V/Lux·Sec V

Min. Illumination 0.1 Lux Standard CCIR clock Shading TBA % Variance of V

Random Noise -36 dB RMS variance of all pixels, at 66% satura-

Smear TBA % Ratio of V

Flicker TBA % Variation of V

Lag TBA % Average residual signal with no illumination

Blooming TBA Ratio of spot illumination level that produces

/Lux·10ms, where Lux gives 50% satu-

Ave

ration with Gain=1 and Exposure=10ms

over eight equal blocks at

66% saturation level illumination

tion, over four frames

25 lines high illuminated at 500xV to V

Ave

at 66% saturation level illumination

in the field following one field of 66% sat.

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illumination

0.1xV

sat

spot to the V hole target)

ave

of the area outside a rectangle

ave

of the rectangle

ave

output from immediately around the

sat

of one line from f iel d to fiel d

spot illumination level (pin-

50%

level

Note: Devices are normally not 100% tested for the above characterisation parameters, other than

Dark Current Signal (see Blemish Specification below).

All voltage (VA, V blemishes are excluded (see Blemish Specificatio n below). V saturation, that is peak white

est Conditio ns

The sensor is tested using the example support circuit illustrated later in this document. Standard imaging conditions used for optical tests employ a tungsten halogen lamp to uniformly illuminate the sensor (to better than 0.5%), or to illuminate specific areas. A neutral density filter is used to control the level of illumination where required.

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ave

, V

) measurements are referenced to the black level, V

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sat

xx%

, and spot

refers to the output that is xx% of

xx%

Illumination Colour Temp. 3200o K Clock Frequency 14.318MHz Exposure Maximum Gain x1 Auto. Gain Control (AGC) Off

black

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VV5300 Sensor

Blemish Specification

A Blemish is an area of pixels that produces output sign ificantly different fr om its surrounding pixels for the same illumination level. The definition of a Blemish Pixel varies according to testing conditions as follows:

Test Exposure Illumination Blemish Pixel output definition

1 - Black Frame Minimum Black Differing more than ± 100 mV. from modal

value.

2 - Dark Current Maximum Black Output more than three times the modal value

(see Dark Current Signal above).

3 - Pixel Variation Mid range 66% Sat. Differing more than ±35mV from modal value.

Note: The mode of pixel values must be within ±70 mV of 66% of V

for all devices.

sat

Note: Gain is set to Minimum and Correction set to Linear for all tests; measurement of blemishes for

Test 3 is conducted under standard illumination (see above), set to produce average output of 66% saturation level.

The blemish specification is then defined as follows:

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Max. No. of Blemishes Notes

4 Unconnected single pixels 1 Of up to four connected pixels (2x2 max.)

NB, pixel blemishes may occur anywhere on the array.

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VV5300 Sensor

System Clock Generation

VV5300 generates a system clock when a quartz crystal or ceramic resonator circuit is connected to the CLKI and CLKO pins. The device can also be driven directly from an external clock source driving CLKI.

CLK

CLOCK

DIVISION

VV5300

CKIN

C1=C2=47pF R1=1MΩ R2=510Ω X1= 14.318MHz (up to 60fps)

17.73MHz (up to 50fps)

For greater flexibility the input frequency can be divided by 2, 4, 8 or 16 to select the pixel clock frequency. Two bits in the clock division register in the serial interface select the input clock frequency divisor. The table below gives the different frame rates that can be selected, when CLKI = 14.318MHz, for each divisor. The default clock divisor setting is a divide by 2. To achieve maximum frame rates data is converted at 4 bit resolution.

CKOUT

32 31

Camera Clock Source

Clock Source

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VV5300

CMOS Driver

CKIN

CLK

CLOCK

DIVISION

CKOUT

3231

CLKI

(MHz)

14.318 0 0 2 1790 59.98 default

14.318 0 1 4 895 29.99

14.318 1 0 8 448 15.01

14.318 1 1 16 224 7.5

1. Approximate frame rate. Assumes 160 x 120 image format, parallel data output and 4 bit data conversion

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Clock Division (60Hz Video Mode)

Divisor

Pixel Freq.

(kHz)

Frame rate

(fps)

Comments

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VV5300 Sensor

Image Format

VV5300 has a single output image size, 160 x 120 pixel. The image size can be modified by asserting the

“enable borders” serial interface register bit, (Setup1, [001_0001 pixels. The default image format is 160 pixels by 120 lines.

Enable borders Image size (column x row) Comment

0 160 x 120 default 1 164 x 124

Image Format Selection

The diagram below shows the relationship between the default 160 x 120 pixel image and the extended 164 x 124 pixel format. A border, 2 pixels wide is enabled around the basic array.

164

]). The extended image size is 164 x 124

160

Output Image Dimensions

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120

124

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VV5300 Sensor

Frame Timing

The VV5300 frame rate depends upon:

(i) the frequency of the clock input (CLKI) (ii) the ADC conversion accuracy (ii) the internal clock divis or cho se n.

Users can set their own values for CLKI, the ADC conversion rate and also the clock divisor setting, subject to achieving a frame rate up to 60 frames/sec.

The frame rate is determined in the following way: An example is given with a clock input of 14.318MHz, 160 x120 image format, 8 bit ADC conversion rate and

a clock divisor of 4.

1. Determine clock input (CLKI) frequency - 14.318MHz

2. Pixel period = (Divisor x 8) / CLKI

Example: Pixel period = (4 x 8) / 14.318MHz = 2.235µs

3. Line period = (no. of active pixels + line overhead) * pixel period The number of active pixels per line is either 160 or 164. The interline pixel period overhead (including the 4

border pixels that can be enabled to qualify extra video information) is mode dependent, 43 pixel periods for 60fps or 135 pixel periods for 50fps. Refer to figure * for more information.

Example: Line period = (160 + 43) x 2.235µs= 453.705µs

4. Frame period = (no. of active lines + frame overhead) * line period For the purposes of calc ul ating th e effective frame rate the nu mbe r of ac tiv e l ine s is a ssumed to be fixed at

120. The frame overhead (which includes the 4 border lines that can be enabled to qualify extra video information) has a constant value of 27 line periods. Refer to table * for more information.

Example: Frame period = (120 + 27) x 453.705µs= 66.694ms

Frame rate = 1 / frame period = 15 frames per second

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inar

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VV5300 Sensor

Digital Data Output Modes

VV5300 provides several different output modes. The different data formats are selected via the appropriate register in the serial interface, Setup0, [001_0000 selected via the serial interface, Setup1, [001_0001 Wire parallel output format then 2 consecutive pixel nibbles may be packed into a single output byte therefore increasing the effective frame rate.

], bits 5 and 6. 8-bit or 4-bit pixel data conversion is also

]. If 4-bit pixel data conversion is selected as well as 8-

Setup

Bit 6

0 0 8-Wire Parallel 0 1 4-Wire Parallel default 10 Serial 11 Serial UART

Setup

Bit 5

Description Comment

Data Output Modes

Frame Level Formatting

The frame level format for each mode is common and is given below. FST can be used for frame synchronisation. The FST pulse is exactly one line period in length and the rising edge occurs just before the status line start sequence (see line level formatting) is output.

FST

Line

BL ST BK BK BL

Start / Status Line (ST)

Frame Start

Black Lines (BK)

BL BL BL BL

Blank Lines (BL)

BL BL

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BL VL VL VL VL VL VL VL

Visible Lines (VL)

120 Visible Lines

FST

Line

VL BL

BL BL

Frame End (FE)

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BL FE BL ST

BL BL

Frame Period = 147 Lines

BLBLBL BL BL BL BL

BL BL

Frame Format (160 x 120 mode)

FST

Line

BL ST BK BK BL

Start / Status Line (ST)

FST

VL VL

Line

Black Lines (BK)

Frame Start

BL BL

BL BL BL BL

Blank Lines (BL)

BL BL

Frame End (FE)

Visible Lines (VL)

VL VL VL VL VL VL VL VL

124 Visible Lines

BL FE BL ST

BL BL

Frame Period = 147 Lines

BLBLBL BL BL BL BL

BL BL

Frame Format (164 x 124 mode)

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VV5300 Sensor

Line Level Formatting

Each line type (black, blank, visible) has a specific format associated with it independent of the data output format selected. Each line begins with a start sequence of FF the line type. The next two bytes provide supplementary data (specifically the line number within the current frame). Following this data are two guaranteed blank bytes (07 If the border lines/pixels have been enabled the next 2 bytes will be visible pixels otherwise they shall appear as blank bytes. The next part of the line is reserved for the 160 visible pixels. The 4 bytes following the visible pixels are formatted in the same way as the 4 bytes preceeding the 160 visible pixels. At the end of each line, an end of line sequence is produced, (FF (lines 11 to 134 if the border lines are enabled otherwise lines 13 to 132), the end of line sequence is immediately followed by 2 bytes containing the mean values for the central 128 pixels. The first byte contains the mean value for the first 64 pixels of the middle 128 pixels and the second byte contains the mean value for the latter 64 pixels of the middle 128 pixels. The 128 pixels comprise the standard 120 visible pixels, the 4 border pixels and an extra 4 border pixels that are never enabled as visible pixels but are used for exposure control and hence contribute to the mean pixel value for the line. If the line type is not visible then the two bytes following the end of line sequence will contain 07 data output is always FF

Sensor status and configuration information is output during the frame start line, (line 0), each data byte is separated by a blank value (07 information output during the status line reflects, if the sensor is operating in 8bit ADC mode, the first 64 locations in the serial interface register map. If the sensor is operating in 4 bit mode less data can be output during the status line. All the serial interface registers are 8bit values therefore 2, 4bit pixel periods are required to output a single serial interface location. Note that the serial interface data is only output during the visible monochrome pixels of the status line. This allows for one quarter of the serial interface address space to be output during any status line. It is possible to select the remaining registers in the serial interface for output, (see serial interface register setup 2, bits 7:6).

The “end of frame” line, it is actually 2 lines prior to the status line will output the 4 exposure control bin averages during the first 4, (or 8 if operating in 4bit modes), monochrome pixels. Again the data is separated by mode dependent padding data.

) to avoid possible false line start conditions being generated. The

FFH 00H 80H). If the line is within the visible part of the frame,

FFH 00H followed by XYH where XYH indicates

for 8 bit modes, 01H01H for 4 bit modes).

H 07H

07H. For the remainder of the interline period the

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VV5300 Sensor

Escape/Sync Sequence

8-wire output mode 4-wire output mode

Command

Nibble X

Supplementary Data

(i) Line Number (L11 MSB)

Nibble D

(Line Code)

C1C

L10L

L4L

Odd word parity

Nibble Y

Nibble D

P1P

Line Code Nibble XH [1 C2 C1 C0] Nibble YH [P3P2P1P0]

L6PL

L0PL

or (ii) If Line Code = End of Line then

Mean Pixel Value for first half of the line

Mean Pixel Value for second half of the line

M5M

N5N

D3D2D1D

N1N

M1M

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End of Line 10002 (8H) 00002 (0H) Blank Line (BL) 1001 Black line (BK) 1010 Visible Line (VL) 10112 (BH)0110 Start of Frame (SOF) 1100 End of Frame (EOF) 1101 Reserved 11102 (EH) 11002 (CH) Reserved 1111

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) 11012 (DH)

2 (9H

)1011

2 (AH

) 01112 (7H)

2 (CH

)1010

2 (DH

) 00012 (1H)

2 (FH

(BH)

(6H)

(AH)

Line Level Formatting

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VV5300 Sensor

FRAME START

BLACK

BLANK

Line Start Sequence

FFHFF

Line Start

SD 07HSD 07

Line Start Sequence

FFHFF

Line Start

PV PV PV PV

Line Start Sequence

FFHFF

Line Start

07H07H07H07

C7HLN 07H07

Line Type

ABHLN 07H07

Line Type

9DHLN 07H07

Line Type

Line Number

07H07

FFHFFH00

Line End

FFHFFH00

Line End

07H07

FFHFFH00

Line End

Sensor Status Data

SD 07HSD 07HSD 07HSD 07HSD 07

Line End Sequence

PV PV PV PV PV PV PV PV PV PV

Line End Sequence

07H07H07H07H07H07H07H07H07H07

Line End Sequence

Black Level Pixel Values (Nominally - 10H)

Blank Level (07H)

inar

Inter-Line Period

SD 07

Next Line Start

PV PV

Next Line Start

07H07

Next Line Start

VISIBLE

FRAME END

Line Start Sequence

FFHFF

Line Start

PV PV PV PV

Line Start Sequence

FFHFF

Line Start

07H07H07H07

B6HLN 07H07

Line Type

DAHLN 07H07

Line Type

Line Number

07H07

FFHFFH00

PV PV PV PV PV PV PV PV PV PV

Line End Sequence

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Line End

07H07

FFHFFH00

Line End

Line End Sequence

Line Coding

160 Visible Pixels

MN80

Line Mean Values

Frame Mean Values

MN MN

Inter-Line Period

Black = 10H - White = F0

MN07H07

07H07

PV PV

Next Line Start

07H07

Next Line Start

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VV5300 Sensor

8-Wire Parallel Mode

8-Wire parallel mode is selected when the appropriate bits are set via the serial interface. When 8-bit conversion mode is selected the 8-bit pixel data is output on pins DATA[7:0]. The start of a frame

is indicated by a pulse on FST. The data is valid on the falling edge of the pixel sample clock fast QCK (QCK or on each edge of the slow QCK (QCK

Line Start Line No.Line Type

)

DATA[7:0]

QCK

DATA[7:0]

QCK

P117 P118 P119 P120

P1 P2

B6HLN 07H07

07H07

Line End

FFHFFH00

Line Mean

MN80

P3 P4 P5

P6 P7 P8 P9 P10

8-Wire Parallel Mode (8-bit Pixel Data)

When 4-bit conversion mode is selected the 4-bit pixel data is output two bytes at a time on the DATA[7:0] pins. The first pixel is mapped onto DATA[7:4] and the second pixel is output on DATA[3:0]. This effectively doubles the pixel rate (and halves the frame period).

inar

Line Start Line No.Line Type

DATA[7:4]

DATA[3:0]

FHF

BHLN 1

6HLN 1

P0LN P2 P4 P6 P8 P10 P12 P14 P16 P18 P200

P3 P5 P7 P9 P11 P13 P15 P17 P19 P210

P22

P23

P24

P25

QCK

DATA[7:4]

DATA[3:0]

QCK

P104 P106 P108

P102

P105 P107 P109

P103

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Line Mean

MN8

MN0

Line End

P110 P112 P114 P116 F

P118

P119 MNP111 P113 P115 P117 F

1HFHFH0

8-Wire Parallel Mode (4-bit Pixel Data)

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VV5300 Sensor

4-Wire Parallel Mode

4-Wire parallel mode is selected when the appropriate bits are set via the serial interface. When 8-bit data conversion mode is selected (CONV8 = 1) the 8-bit pixel data is output on pins DATA[7:4] in two 4-bit nibbles. The start of a frame is indicated by a pulse on FST. A QCK sample edge is generated for each nibble.

Line Start Line No.Line Type

DATA[7:4]

QCK QCK

DATA[7:4]

QCK QCK

LN LN

0H7

FHF

FH0

0H7

P119P118P116 P117P115

BH6

LN LN 0H7H0H7

0H7

FHFHF

Line End

8H0

DATA[7:4]

QCK QCK

FHF

FHFHF

FHF

FH0

BH6

LN LN

MN F

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4-Wire Parallel Mode (8-bit Pixel Data)

When 4-bit data conversion mode is selected (CONV8 = 0) the 4-bit pixel data is output on pins DATA[7:4].

Line Start Line No.Line Type

DATA[7:4]

QCK

FHF

FH0

BH6

LN LN

LN LN 1H1

1H1

P0 P1 P2 P3

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Line End

P119P118P117P116P115P114P113

DATA[7:4]

QCK

1H1

FHFHF

8H0

LN LN

DATA[7:4]

QCK

FHF

FHFHF

FHF

FH0

BH6

LN LN

4-Wire Parallel Mode (4-bit Pixel Data)

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LN LN

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VV5300 Sensor

Serial Mode

Serial mode is selected when the appropriate bits are set via the serial interface. When 8-bit data conversion mode is selected the 8-bit pixel data is output on pin DATA[0] least significant bit first.

DATA[0]

QCK

DATA[0]

QCK

DATA[0]

QCK QCK

Line Start

P116 P117 P118 P119

Line Type

B6HLN 07H07

0123

Line No.

07H07

Pixel_0

FFHFFH00

07H07

Line End

P0 P1 P2 P3 P4 P5 P6 P7 P8 P9

0123

MN80

Pixel_1 Pixel_2

5 0123

Serial Mode (8-bit Pixel Data)

When 4-bit data conversion mode is selected (CONV8 = 0) the 4-bit pixel data is output on pin DATA[0] least significant bit first.

inar

P10

DATA[0]

QCK

DATA[0]

QCK

DATA[0]

QCK

DATA[0]

QCK

P112P111

FHF

Line Start Line No.

P117 P118P116P114 P115P113

Line Type

P119

Preli

Pixel_0

FHFHF

Pixel_1 Pixel_2

FHF

0321

LN LN

LN LN 1H1

1H1

FHF

0321

FHFHF

FH0

P2 P3

Line End

BH6

Pixel_3 Pixel_4

8H0

LN LN

021

P5 P6

LN LN

Serial Mode (4-bit Pixel Data)

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VV5300 Sensor

Serial UART Mode

Serial UART mode is selected when the appropriate bits are set via the serial interface. When 8-bit data conversion mode is selected the 8-bit pixel data is output on pin DATA[0] least significant bit first. Each pixel is preceded by a start bit and followed by an additional data bit and two stop bits.

Line Start Line No.Line Type

DATA[0]

P116 P117 P118 P119

B6HLN 07H07

07H07

FFHFFH00

07H07

Line End

P0 P1 P2 P3 P4 P5 P6 P7 P 8 P9

MN80

P10

DATA[0]

0123

Least Significant Bi t Fir s t

Start Bit

Pixel_0

Unused Data Bit

Two Stop Bits

Pixel_1

2 567

Serial UART Mode (8-bit Pixel Data)

When 4-bit data conversion mode is selected the 4-bit pixel data is output two pixels at a time on pin DATA[0] least significant bit first. Each pixel is preceded by a start bit and followed by an additional data bit and two stop bits.

DATA[0]

Line Start Line No.

P112P111

FH0

P117 P118P116P114 P115P113

Line Type

0H8

P119

LN LN

inar

LN LN 1H1

1H1

H1H

FHFHF

P0 P1

Line End

P3 P4

0HE

Preli

DATA[0]

FHF

Pixel_0 Pixel_1

0123

Start Bit

Least Signif icant Bit First

FHFHF

Unused Data Bit

FHF

Two Stop Bits

FH0

Pixel_2

0H8

2 123

LN LN

Pixel_3

MN F

Serial UART Mode (4-bit Pixel Data)

cd34011-b.fm 17/10/97 20

LN LN

Page 21

VV5300 Sensor

Qualifying the Output Data

Data is output from VV5300 in a continuous stream. By utilising signals, like FST, and key events, like the start of a line or the end of line, the user can sample and display the image data. QCK is used to sample the data, as described in the previous section. By default the falling edge of QCK will sample the data, however it is possible to use both the rising and falling edges of a slow QCK QCK

Different sections of the frame can be enabled by QCK. The options, which are selected via setup register4 in the serial interface, are as follows, firstly the QCK can be disabled, therefore no data will be qualified. This is the default option.

The second option is to have the QCK free running where all the data is qualified. The third option is to only qualify the image data, which also includes the 2 black calibration monitor lines,

lines 1 and 2 in the frame. This option is further complicated in that extra black lines and the extra border pixels/lines can be enabled giving the following 4 options:

to sample the data.

1. Black lines (1-2) plus image (160 pixels by 120 lines)

2. Black lines (1-8) plus image (160 pixels by 120 lines)

3. Black lines (1-2) plus image (164 pixels by 124 lines)

4. Black lines (1-8) plus image (164 pixels by 124 lines)

The final option is to qualify the embedded frame control sequences as well as the image data. These control sequences are the 6 bytes at the start and at the end of each image line, where an image line is defined above. The frame start or status line, image and control sequence pixels, will also be qualified during this mode.

QCK Exceptions

The output data from VV5300 can be formatted in many ways, as detailed in an earlier section of this document. Under certain operating conditions the relationship between QCK and the output data is compromised.

It is vital that the phase relationship between the output data stream and the QCK must be maintained from line to line, for example ensuring that, if enabled, the line code byte is always qualified by the same edge of the QCK, clearly only applicable when considering slow QCK qualification. It is known that there are an odd number of pixel periods in each line of the frame. If the slow QCK is selected then clearly two pixels are qualified during each QCK cycle resulting in the following modes of operation requiring special care: 4 bit ADC 8 wire output, 8 bit ADC 8 wire output and 4 bit ADC 4 wire output. During the interline period, when the data bus is outputting data fixed at FF (8bit ADC) or F (4bit ADC), the phase of the QCK is toggled, this will occur during every interline period. For the 8bit 8wire or 4bit 4 wire options this change is a simple inversion. The 4bit 8wire option is not quite as straightforward. During the interline period the QCK signal is changed from its former state to 1 of 3 other states. In addition 2 out of the 4 possible states are video timing mode dependent.

Preli

inar

Please note that the number of nibbles/bytes qualified by the clocks described above, during the free running QCK mode, will differ from the expected value, as follows:

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VV5300 Sensor

QCK Exception Details

Number of pixels qualified

Operating Mode

4bit 4wire 203 202 301 300 4bit 8wire 202 198 300 298 8bit 8wire 203 202 301 300

Serial Interface - Exposure Control Handshake

The process of writing timed exposure, clock division or gain settings to VV5300 using the serial interface requires special attention. These timed parameters can be written to the serial interface at any point within the frame timing but will only be transferred from shadow registers to their active registers at a specific point within the frame timing, see diagram below. Please note that writing immediate clock division or gain

parameters are treated as a “normal” serial interface write messages.

odd frame flag

50 frames per second

QCK

Pixel qualification exceptions

QCK

Number of pixels qualified

60 frames per second

QCK

inar

old_exp

new_exp

old_clock_div

old_gain

Preli

Since the new external exposure, clock division or gain settings are written to shadow registers the user continues to have full read/write access to the serial interface. A handshake system has been implemented between the exposure controller and the serial interface to avoid the user writing, for example, a second external timed gain value while the exposure controller has yet to transfer the first external timed gain value from the shadow register to the active register. If an external timed gain message has been written a special flag will be raised to indicate that it has yet to be transferred to the active register. This flag is available to the user via reading the status 0 register in the serial interface. Until the flag is lowered the user knows that it is not safe to write a further external gain value. Identical handshake protocols are used to implement timed external exposure and cloc k div isi on w rites .

1 frame period

new_clock_div

new_gain

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VV5300 Sensor

Auto Black Calibration

Black calibration is used to remove voltage offsets that cause shifts in the black level of the video signal. VV5300 is equipped with an automatic function that continually monitors the output black level and calibrates if it has moved out of range. Black calibration can be split into two stages, monitor (1 cycle) and update (3 cycles). During the monitor phase the current black level is compared against two threshold values. If the current value falls outside the threshold window then an update cycle is triggered. The update cycle can also be triggered by a change in the gain applied to sensor core or via the serial interface.

Serial Interface

In order to be controlled and configured by its host, VV5300 can receive and transmit data via a two-wire serial interface.

Serial Communication Protocol

The host must perform the role of a communications master and the camera acts as either a slave receiver or transmitter.The communication from host to camera takes the form of 8-bit data with a maximum serial clock frequency of up to 100kHz. Since the serial clock is generated by the host it determines the data transfer rate. The bus address for VV5300 is 20

. Data transfer protocol on the bus is shown below.

Start condition

SDA

MSB

Read/Write bit Acknowledge from receiver

inar

SCL

7891

ACK

Data Transfer Protocol

Data format

A message contains at least two bytes preceded by a

start

followed by another message. The first byte contains the device address byte which includes the data direction read/write bit. The device address is 32 address byte indicates the direction of the message. An even address causes the addressed slave to receive information from the master (write), an odd address indicates message read by the master.

Write, 3310 Read. The 5 msbs of the address byte are fixed as 0010_02. The lsb of the

Sensor acknowledges valid address

address[7:1]

0 0 1 0 0 0 0

Preli

[0]

start

condition and followed by either a

INDEX[6:0]INC

3 - 8 9

Acknowledge from slave

DATA[7:0]

stop

ACK

Stop condition

repeated

/W bit

Data Format

After the read/write bit is sampled, the data direction cannot be changed, until the read/write bit next message is received. The next byte contains the location of the first data byte (also referred to as the be up to 128 such locations. If the msb of the second byte is set the automatic increment feature of the address index is selected.

cd34011-b.fm 17/10/97 23

DATA[7:0]

index

).There may

Page 24

VV5300 Sensor

Message interpr e tation

All serial interface communications with the sensor must begin with a followed by a valid address byte then further communications can take place. The sensor will acknowledge the receipt of a valid address by driving SDA low. The state of the read/write bit (lsb of the address byte) is stored and the next byte of data can be interpreted.

During a write sequence the second byte received is an address index and is used to point to one of the internal registers. The msbit of the following byte is the serial interface will automatically increment the index address by one location after each slave acknowledge. The master can therefore send data bytes continuously to the slave until the slave fails to provide an acknowledge or the master terminates the write communication with a

(Sr)

start

data bytes. As data is received by the slave it is written bit by bit to a serial/parallel register. After each data byte has

been received by the slave, an acknowledge is generated, the data is then stored in the internal register addressed by the current index.

During a read message, the current index is read out in the byte following the device address byte. The next byte read from the slave device are the contents of the register addressed by the current index. The contents of this register are then parallel loaded into the serial/parallel register and clocked out of the device by At the end of each byte, in both read and write message sequences, an acknowledge is issued by the receiving device. Although VV5300 is always considered to be a slave device, it acts as a transmitter when the bus master requests a read from the sensor.

. If the auto increment feature is used the master does

index auto increment

start

condition. If the

flag. If this flag is set then the

stop

condition or sends a

not

have to send indexes to accompany the

start

condition is

repeated

scl.

At the end of a sequence of incremental reads or writes, the terminal index value in the register will be one

greater

from the internal registers. A message can only be terminated by the bus master, either by issuing a stop condition, a repeated start

condition or by a negative acknowledge after reading a complete byte during a read operation.

The programmers model

There are 128, 8-bit registers within the camera, accessible by the user via the serial interface. They are grouped according to function with each group occupying a 16-byte page of the location address space. There are eight such groups, The primary categories are given below:

the last location read from or written to. A subsequent read will use this index to begin retrieving data

inar

• Setup registers with bit significant funct ions including status (read only) bits

Preli

• Exposure parameters that influence output i mage brightness.

• System functions and test bit significant registers.

Any internal register that can be written to can also be read from.

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VV5300 Sensor

Index Name R/W Default Comments

000_0000 RO 1100 00002 (C0H) 000_0001 RO 0001 0010 000_0010 status0 RO 0 000 100 0 000_0011 unused 000_0100 line_count RO Current line counter value 000_0101 leftav RO Average value of pixels in the first

Status

000_0110 rghtav RO Average value of pixels in the second

000_0111 frame_av RO Average value of pixels in a frame. 000_1000 bin1 RO Partial frame average - bin1 000_1001 bin2 RO Partial frame average - bin2 000_1010 bin3 RO Partial frame average - bin3 000_1011 bin4 RO Partial fra me aver age - bin 4

000_11xx unus ed 001_0000 setup0 R/W 0010_01112 (27H) Configure the digital logic 001_0001 setup1 R/W 0111_0000 001_0010 setup2 R/W 0001_1111 001_0011 setup3 R/W 0000_1111 001_0100 setup4 R/W 0000_0000

Setup

001_0101 unused -

001_011x unused -

001_1xxx unused 010_0000 unused 010_0001 fine R/W 0000_0000 010_0010 unused 010_0011 coarse R/W 0111_0000 010_0100 gain R/W 0000_0000 010_0101 clk_div R/W 0000_0000 010_0110 gn_lim R/W 0000_011 1

Exposure

010_0111 tl R/W 0101_0101 010_1000 tc R/W 1001_0110 010_1001 th R/W 0110_0110 010_101x unused -

010_1xxx unused -

111_0011 xfav R/W 1000_00002(80H) External frame average

111_0101 dcth R/W 1000_0000

111_1001 unused

111_1010 unused

System

111_1011 unused

111_11xx unused

Preli

(12H)

(08H) System status information

half of the current line.

(70H) Configure the digital logic

(1FH) Pixel counter reset value

(0FH) Exposure control modes

(00H) FST/QCK options

inar

(00H) Fine exposure initially zero

(70H) Coarse exposure

(00H) Gain value

(00H) Clock division

(07H) Maximum allowable gain

(55H) Lower exposure control threshold.

(64H) Centre exposure control threshold.

(73H) Upper exposure control threshold.

(80H) Digital comparator threshold

Reserved

The programmers model

A detailed description of each register follows. The address indexes are shown as binary in brackets.

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VV5300 Sensor

Status 0 [000_00102]

The loading of certain system parameters is timed to avoid disturbing the video signal part way through a frame. Bits 0-2 can be polled to check that a value written to either the exposure, gain or clock division registers has been consumed or not. Bit 3 is essentially an internal flag differentiating between consecutive frames.

Bit Function Default Comment

0 Exposure value update pending 0 New exposure setting sent but not yet con-

sumed by the exposure controller

1 Clock division value update

pending

2 Gain value update pending 0 New gain value sent but no t yet con sumed by

3 Odd/even frame 0 The flag will toggle state on alternate frames 4 Black Calibration fail flag 0 If the black calibration algorithm returns very

7:5 Unused 0

0 New clock division setting sent but not yet

consumed by the exposure controller

the exposure controller

poor black level s - out with bo th t he calib ratio n and monitor windows then this f lag will be s et and it will stay set until the next successful calibration is complete

Status 0 [000_00102]

Line_count [000_01002]

inar

Bits Function Default Comment

7:0 Line count 0000_00002Displays current line count

Line_count [000_01002]

The video timing logic is controlled by the pixel counter and the line counter. To reduce the level of digital switching noise these counters implement a gray count sequence, where only a single counter register can change state in a clock period. However the gray count sequence is user unfriendly,e.q. 248,232,233,

235,234. A binary version of the line count is generated internally, realising a 0,1,2,3,4..... sequence, and it

is this count sequence that is read by the serial interface and hence made available to the sensor user.

Line_avg 0 [000_01012] & Line_avg 1 [000_01102]

The exposure controller accumulates the pixel output values. On a line by line basis the accumulation is performed in two stages. The qualified pixels in the left half of the video line are accumulated and then stored in a latch. The process is then repeated during the right half of the video line. During the interline line period (up until the latch that stores the value for the left half of the line is updated during the next line) the latches will present valid average 8-bit pixel values for both halves of the line.

Preli

Bits Function Default Comment

7:0 Line average 0 Average pixel value for first half of current line.

Line_avg 0 [000_01012]

Bits Function Default Comment

7:0 Line average 0 Average pixel value for second half of current line.

Line_avg 1 [000_01102]

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VV5300 Sensor

Frame_avg [000_01112]

The average pixel values stored in latch es halfway through and at the end of each act ive video line are ultimately stored in bins that will maintain a frame sum of the pixel values. At the end of the frame the values stored in these bins are used t o determine the overall pixel average for t he whole frame.

Bits Function Default Comment

7:0 Frame average 0 Pixel average for previous frame

Frame_avg [000_01112]

Bin1_avg [000_10002]

Bits Function Default Comment

7:0 Bin1 average 0 Pixel average for current line

Bin1_avg [000_10002]

Bin2_avg [000_10012]

Bits Function Default Comment

7:0 Bin2 average 0 Pixel average for current line

Bin2_avg [000_10012]

inar

Bin3_avg [000_10102]

Bits Function Default Comment

7:0 Bin3 average 0 Pixel average for current line

Bin3_avg [000_10102]

Preli

Bin4_avg [000_10112]

Bits Function Default Comment

7:0 Bin4 average 0 Pixel average for current line

Bin4_avg [000_10112]

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VV5300 Sensor

Setup 0 [001_00002]

Setup registers 0,1,2,3 and 4 are used to alter the operating parameters of the sensor. All of these registers can be written to and read from.

Setup 0 register controls some fundamental exposure and output format parameters. Defaults are shown in

Bold.

Bit Function Default Comment

0 Automatic exposure control.

Off/On

1 Clamp fine exposure

Off/On

2 Automatic gain control.

Off/On

3 Enable immediate gain

update. Off/On

4 Enable immediate clock divi-

sion update. Off/On

6:5 Data format select. 01 00 - 8 wire parallel output

7 3/4 crystal clock

Off/On

1 E nables or disables auto matic exposure control.

Current exposure value is frozen when disabled.

1 If this bit is set

exposure has e xceeded the cl amp thresho ld, 16, then the fine exposure will be clamped to 0.

1 E nables or disables automa tic gain control. Cur-

rent gain value is frozen when disabled.

0 Allow manual change to gain to be applied imme-

diately.

0 Allow manual change to clock division to be

applied immediately.

01 - 4 wire parallel output

10 - 2 wire serial output 11 - 1 wire serial output

0 Achieves clock division by 3 rather than 4.

Setup0 [001_00002]

inar

and

aec is enabled

and

the coarse

Setup 1 [001_00012]

Setup 1 register controls registers that are less likely to be modified on a regular basis. The user should note that the border pixels/lines can be disabled/enabled independently from the enabling/disabling of the custom analogue horizontal shift register.

Bit Function Default Comment

0 Enable additional black lines (3-8)

Off/On

1 Enable border pixels

Off/On

2 Enable horizontal shuffle mode.

Off/On

cd34011-b.fm 17/10/97 28

Preli

0 If enabled extra black lines are visible at

device output

0 Extends qualified image size to 164 x 124.

Default image size is 160 x 120

0 The contents of the horizontal shift register

are shuffled so tha t all the even colu mns then all the odd columns are read out.

Setup1 [001_00012]

Page 29

VV5300 Sensor

Bit Function Default Comment

3 Enable samp le mod e

Off/On

4 Status line data output enable.

Off/On

5 8-bit or 4-bit ADC select 1 The analogue output ADC can be configured

6 50fps timing/60fps timing 1 The sensor will implement 60Hz like line

7 External frame average

Off/On

Setup1 [001_00012]

0 If enable d the data bus will continuously out-

put a “96 mode a user can deter mine the best point at which to sample the data.

1 Enables the output of serial interface status

information on the data bus. By default the bottom 64 locations from the serial interface will be output.

to convert to 4-bit or 8-bit resolution.

timing by default giving reduced flicker operation with 60Hz s ou rce frequencies. If the supply frequency is 50Hz then 50Hz like timing should be selected.

0 Normally the accumulator arithmetic logic

calculates the frame average of the pixel samples. However if this bit is enabled then the user may specify a frame average.

” pattern. WIth the sensor in this

inar

Setup 2 [001_00102]

In many systems VV5300 will be continuously synchronised. During this synchronisation the video timing is reset to a fixed point within the frame timing. The counter reset value is definable.

Bit Function Default Comment

5:0 Pixel counter reset value. 011111

6 Status information output option.

Off/On

7 Status information output option.

Off/On

Bit 7 Bit 6

00 00

Preli

Setup 2 [001_00102]

During synchronisation the pixel counter is

reset to the defined value.

0 Selects which system parameters are output

on status line. See table below.

0 Selects which system parameters are output

on status line. See table below.

8-bit modes

- 3F

4-bit modes

00H - 1F

01 40 10 - 40

Status line information options

cd34011-b.fm 17/10/97 29

- 7F

20H - 3F

- 5F

Page 30

VV5300 Sensor

Bit 7 Bit 6

11 - 60

Setup 3 [001_00112]

Bit Function Default Comment

3:0 Exposure control mode

select.

4 Autoload control 0 This bit controls the autoload feature 6:5 Exposure step size 01 Selects exposure step size. 1/8 for fast but

7Unused 0

Note1: The state of this pin can affect the autoload function in a number of ways.

1. If the autoload bit is high continuously and the autoload pin is also high then an autoload will not take place.

2. If the autoload bit is initially high and is then forced low then an autoload will take place regardless of the state of the autoload pin.

3. If the au toload pin is initially hi gh and is then forced low an autoload will take place re gardless of t he state of th e autoload bit.

4. A low to high transiti on on e ither the a utoload bit or t he auto load p in while VV5300 is runn ing w ill have no ef fec t on the autoload function.

8-bit modes

Status line information options

1111

Setup 3 [001_00112]

The average value for the frame that the

exposure controller use s can be calculated in a number of different ways. See table below.

jerky convergence to 1/64 for slow but smooth convergence. Default 1/16.

4-bit modes

- 7F

inar

Note1

Bit 3 Bit 2 Bit 1 Bit 0 Function

0000bin1

Preli

0001bin2 0010bin3 0011bin4 0100(bin1 + bin2) / 2 0101(bin3 + bin4) / 2 0110(bin1 + bin3) / 2 0111(bin2 + bin4) / 2 1000(bin1 + bin4) / 2 1001(bin2 + bin3) / 2

Frame Average Options

cd34011-b.fm 17/10/97 30

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VV5300 Sensor

Bit 3 Bit 2 Bit 1 Bit 0 Function

1010(bin1 + bin2 + bin3 + bin4) / 4 1011(bin1 + bin2 + bin3 + bin4) / 4

Frame Average Options

Bit 6 Bit 5 Step size Comment

00 1/8 0 1 1/16 Default 1 0 1/32 1 1 1/64

Exposure step size options

Setup 4 [001_01002]

The data output on the serial wire or the 4 wire/8 wire busses can be qualified, if required, by an internally

fast

and a

slow

generated clock signal, QCK. This clock can be configured variously. Both a generated. If the former is selected then the falling edge of the clock will qualify the current data nibble/byte, i.e. if the sensor is operating in 4 bit-4 wire mode then any true 8 bit data (e.g. line type code) will be qualified

slow

on a nibble basis. If the current data nibble/byte.

QCK option is preferred then both edges of this clock are used to qualify the

inar

QCK can be

The QCK function has a dedicated pin assigned, however by selecting the appropriate bits the FST pin can also output QCK data. By default QCK is disabled. However by writing the appropriate message, QCK can be forced to free run, qualify the embedded coding sequences and the visible data or the visible data only. FST can also be enabled or disabled or alternatively the FST pin can output a timing signal to synchronise several VV5300 sensors or finally the FST pin can output the state of the custom analogue block successive approximation ADC output comparator.

Bit Function Default Mode

1:0 FST/QCK pin mode. 00

3:2 QCK mode select 00

5:4 unused 00 7:6 FST mode select 00

Preli

2 2

Setup 4 [001_01002]

FST pin QCK pin

00 01 10 11

Normal FST

QCK

Inverted QCK

disable

free running

validate control and image data

validate image data only

disable FST

enable FST

synchronisation pulse output (SNO)

output ADC comparator output, CPO

QCK

QCK QCK

S F

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VV5300 Sensor

Exposure Control Registers [010_00012] - [010_10012]

There is a set of parameters that control the time that the sensor pixels are exposed. The parameters are as follows: fine and coarse exposure time, clock division control and finally gain control. The latter parameter does not affect the integration period rather it amplifies the video signal at the output stage of the sensor core. An internal automatic algorithm will, if enabled, continually monitor the pixel output and then, if required, use this data to correct the current exposure.

Manually changing the divisor applied to the incoming crystal clock can alter the effective integration of the sensor. By slowing the internal clock down the integration period can be increased, i.e. halving the pixel clock frequency will double the integration period.

If the user wishes to use the automatic exposure algorithm, the automatic exposure control (controlling

coarse

and gain manually via the serial interface even if the exposure is adjusted automatically.

If a user wishes to write an external value to one of the automatic exposure algorithm registers then it is advised that the automatic control for that register be disabled prior to using the serial interface to write the external value.

exposure) must be enabled. Additional gain control is optional. It is also possible to change the

fine

Note:

The external exposure (coarse, fine or gain) values do not take effect immediately. Data from the serial

interface is read by the exposure algorithm at the start of a video frame. If the user reads an exposure value via the serial interface then the value reported will be the data as yet unconsumed by the exposure algorithm, because the serial interface logic locally stores all the data written to the sensor.

Between writing the exposure data and the point at which the data is consumed by the exposure algorithm, bit 0 of the status register is set. The gain value is updated a frame later than the coarse and fine exposure parameters. The gain is applied directly at the video output stage and does not require the long set up time of the coarse and fine exposure settings.

The automatic exposure algorithm uses a set of exposure threshold settings. These thresholds may also be

modified by the user to alter the algorithm’s performance. The exposure algorithm uses these thresholds in a histogram. The three thresholds divide the histogram into 4 regions, very overexposed, overexposed, underexposed and very underexposed. The pixel data received from the sensor core is compared against the thresholds to determine the accuracy of the current exposure setting. A series of flags are set to describe the outcome of the histogram comparison and the new exposure setting can then be derived.

Each exposure parameter is subject to a maximum setting. The fine exposure setting can be clamped to a fixed value regardless of the decision made by the automatic algorithm. The clamping will occur if the coarse exposure setting exceeds a predetermined value and the clamping has been enabled via the serial interface.

Bit Function Default Comm ent

7:0 Fine exposure value 0000_00002 (00H) maximum fine (50Hz mode) = FF

Preli

Fine Exposure Value [010_00012]

inar

maximum fine (60Hz mode) = A8

H H

Bit Function Default Comment

7:0 Coarse exposure value 0111_00002 (70H) maximum coarse (50Hz and 60Hz modes)

Coarse Exposure Value [010_00112]

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VV5300 Sensor

Bit Function Default Comment

2:0 Gain value 0 8 possible gain states can be written via the

serial interface

Gain Value [010_01002]

All 8 binary codes can be written to the core via the serial interface. Only the 4 thermometer codes 000,001,011 and 1 11 are selected by the automatic exposure algorithm. The 4 other codes are however still valid and will be evaluated as detailed in the table below. It is clear, from the non-linear relationship between the binary code and the actual gain applied at the analogue output stage, that care should be taken when using non thermometer code gain settings. If the user writes a gain code of 110 (real gain = 1.600) and then enables automatic gain control and the controller then decided to reduce the gain, the new gain value would be 011 (real gain = 4.000) i.e. the effective applied gain at the analogue output stage has actually been increased.

Gain binary code Actual signal gain

000 1.000 001 2.000 010 1.333

011 4.000 100 1.143 101 2.667

110 1.600

111 8.000

Bit Function Default Comment

1:0 Clock divisor value 0 Pixel clock = Crystal clock ÷2

System Gain

inar

n+1

Preli

Clock Divisor Value [010_01012]

The

undivided

a small number of other registers in the design. The remaining digital logic and the analogue circuitry, use internally generated clocks, namely the pixel clock and the faster ADC clocks. These clocks are all slower versions of the crystal clock. The ADC clocks may be up to half the crystal frequency, but can be further divided by factors of 2, 4 or 8. The pixel clock is in turn slower than the ADC clock. If the ADC is operating in 4 bit mode then the pixel clock is 1/4 the frequency of the ADC clock, otherwise the pixel clock will be 1/8 the frequency of the ADC clock.

input crystal clock is used by the clock generator circuitry, elements of the serial interface and

Bit Function Default Comment

2:0 Gain limit 7

Gain Limit[010_01102]

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VV5300 Sensor

Bit Function Default Comment

7:0 Exposure lower threshold 85

Exposure Lower Threshold [010_01112]

Bit Function Default Comment

7:0 Exposure centre threshold 100

Exposure Centre Threshold [010_10002]

Bit Function Default Comment

7:0 Exposure higher threshold 115

Exposure Higher Threshold [010_10012]

Frame Average [111_00112]

The exposure controller normally compiles a frame average from the data received from the core. A complete frame period is required to produce a frame average. This is clearly unacceptable for simulation and test purposes. It is possible to manually force a frame average via the serial interface. This feature together with the ability to curtail the frame duration will allow the behaviour of the exposure controller to be examined in a realistic simulation period.

inar

This register is read/write compatible

Bit Function Default Comment

7:0 Frame average 0 Allow a synthetic frame average to be

written to and used by the exposure controller

Preli

Frame Average [111_00112]

Digital Comparator Threshold [111_01012]

The ADC output from the CAB can be digitally compared against a digital threshold. This threshold is fully programmable via the serial interface register. If the current ADC output is greater than or equal to the programmed threshold then the modified ADC output will be forced to the full scale output. The full scale value is mode dependent:- 224 for 8 bit ADC conversion or 14 for 4 bit conversion. If the current ADC output is less than the threshold then the modified ADC output will be forced to minimum video. The minimum video setting (the black level) is again mode dependent:- 16 for 8 bit ADC conversion or 1 for 4 bit conversion.

If this feature is not enabled, (tms[7] = 0), then the ADC output will pass unaltered. As indicated above the ADC can convert to either 4 bit or 8 bit accuracy. When operating in a 4-bit mode the

threshold value should be packed to the 4 most significant bits of the register i.e. if the required threshold

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VV5300 Sensor

value is 10 then 160 should be written to the threshold register.

Bit Function Default Comment

[7:0] Threshold for digital comparator 128 The default has been set at the mid-

Digital Comparator Threshold [111_01012]

range video setting for 8 bit ADC conversion. The user must reprogram the register if the test is run when the ADC is converting to 4 bit accuracy.

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inar

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VV5300 Sensor

Types of messages

This section gives guidelines on the basic operations to read data from and write data to the serial interface. The serial interface supports variable length messages. A message may contain no data bytes, one data byte

or many data bytes. This data can be written to or read from common or different locations within the sensor. The range of instructions available are detailed below.

• No data byte, only sets the index for a subsequent read message.

• Single location multiple data write or read for monitoring for real time control

• Multiple location, multiple data read or write for fast information transfers.

Examples of these operations are given below. A full description of the internal registers is given in the previous section

For all examples the slave address used is 0010000 corresponds to applying logical zero to both the

Single location, single data write.

When a random value is written to the sensor, the message will look like this:

=3210 for writing and 00100012=3310 for reading. This

sab0

and

sab1

inputs.

inar

00100000 0

AAA

010_0000

0101_0101

In this example, the w bit is set to zero for writing and the writing the value. The location is preserved and may be used by a subsequent read.

Single location, single data read.

A read message always contains the index used to get the first byte.

coarse

(index = 01000002=3210) exposure value has been written as 010101012. The r/

inc

bit is set to zero to disable automatic increment of the index after

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00100001

This example shows a terminated with a negative acknowledge (A to issue a stop condition at any other time during a read message. This is because if the data sent by the slave is all zeros, the

cd34011-b.fm 17/10/97 36

coarse

sda

(index = 3210) value of 0101_01012 been read. Note that the read message is

line cannot rise, which is part of the stop condition.

010_0000 0101_0101

) from the master: it is not guaranteed that the master will be able

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VV5300 Sensor

No data write followed by same location read.

When a location is to be read, but the value of the stored index is not known, a write message with no data byte must be written first, specifying the index. The read message then completes the message sequence. To avoid relinquishing the serial to bus to another master a repeated start condition is asserted between the

gain

write and read messages. In this example, the

No data write Read index and data

value (index = 3610) is read as 1510:

Write

setup1

As mentioned in the previous example, the read message is terminated with a negative acknowledge (A the master.

Same location multiple data write.

It may be desirable to write a succession of data to a common location. This is useful when the status of a bit,(e.g. requesting a new black calibration), must be toggled.

The message sequence indexes

ABC

on and then finally off again, leaving it in the default state.

setup1

Sr A

Turn off ABC

inar

ABC

off. The next two data bytes then turn

Toggle “Force Black Cal.”.

128

A20

) from

Same location multiple data read

When an exposure related value ( beginning of the next video frame, (remember that the application of the other exposure parameters). To signal the consumption of the written value, a flag is set when any of the exposure or gain registers are written and is reset at the start of the next frame. This flag appears in register and may be monitored by the bus master. To speed up reading from this location, the sensor will repeatedly transmit the current value of the register, as long as the master acknowledges each byte read.

fine

In the next example, a then constantly read until the master terminates the read message.

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exposure value of 0 is written, the status register is addressed (no data byte) and

coarse, fine, acc

gain

) is written, it takes effect on the output at the

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gain

value is a frame later than the

status0

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VV5300 Sensor

Write

fine

with zero

Address the status0 reg.

Multiple location write

If the automatic increment bit is set, msb of the first data byte following the byte that contains the slave device address, then it is possible to write data bytes to many adjacent internal registers. A write to the black calibration parameters with their default values is shown in the following example.

Read continuously...

Incremental write

...until flag res e t

A20

inar

Multiple location read

In the same manner, multiple locations can be read with a single read message. In this example the index is written first, to ensure the exposure related registers are addressed and then all seven are read

No data write

1 Sr

Preli

gain

fine

Note that a stop condition is not required after the negative acknowledge from the master.

gn_lim

Incremental read

AAA

coarse

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Serial Interface Autoload

VVL_300 can be configured automatically at power-up with any user defined set of system parameters using the serial interface auto-load feature. An external E

PROM is used to store the configuration data.

Both shortly after power up and in response to an off-sensor ‘soft’ reset on SIN, the auto-loader will interrogate the E

If no E changed from their existing values.

If, however, an E starting from location zero in the E

The first byte is a register header code which determines the destination of the following data byte. This simple index & data format allows any sub-set of the VVL_300 registers map to be configured at power-up and it allows them to be stored in the E

If the auto-loader detects the ‘end-of-PROM-contents’ code 00h, it will then issue a STOP condition on the serial interface, raise a flag to indicate that the parameters have been loaded and close down.

device is detected the auto-loader will shut-down and the serial interface register values will not be

PROM to determine whether or not valid data is present.

device is detected, the auto-loader will begin to load data into the parameter registers from

in any order.

Header ROM contents

00h ROM empty or end of data xxh

Parameter header into which the following byte is to be written.

inar

E2PROM header bytes

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VV5300 Sensor

Serial Interface Timing

stopstartstop start

SDA

SCL

thd;sta

all values r eferred to the minimum input level (high) = 3.5V, and maximum input level (low) = 1.5V

Serial Interface Timing Characteristics

Parameter Symbol Min. Max. Unit

SCL clock frequency fscl 0 *** kHz

thightftsu;datthd;dat tsu;sta tsu;sto

...

inar

Bus free time between a stop and a start

tbuf *** - us

thd;statlowtbuf

Hold time for a repeated

start

LOW period of SCL tlow *** - us HIGH period of SCL thigh *** - us Set-up time for a repeated

start

Data hold time thd;dat *** - us Data Set-up time tsu; dat *** - ns Rise time of SCL, SDA tr - *** ns Fall time of SCL, SDA tf - *** ns Set-up time for a stop tsu;sto *** - us Capacitive load of each

bus line (SCL, SDA)

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thd;sta *** - us

tsu;sta *** - us

Cb - *** pF

Serial Interface Timing Characteristics

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VV5300 Sensor

EXAMPLE SUPPORT CIRCUIT

Vin +8 to +12v dc

GND

C12

C13

IC2

C1 C2

C11

C10

VDD2

(48 pin LCC)

VDD3

IC1

AVCC

VV5300

VSS1

VSS2

VSS3

DVSS

AGND

VRT

VCM/VREF2V5

VCDS

VBLTW

VBG

VBLOOM

VDD1

Preli

C17

DVDD

AUTOLOADB

inar

TEST

VREG

D[0] D[1] D[2] D[3] D[4]

D[5] D[6]

D[7]

QCK FST SIN

HPIX

37 40

28 27 26 25 24

23 22 21

3 4

16 15

VDD

C18

D[0] D[1] D[2] D[3]

D[4]

D[5]

D[6]

D[7]

QCK FST

SIN

TEST

HPIX

CLKI

SCL SDA

C17

CLKO

3231

C16

SDA

SCL

3334

C14

Optional E2 for configuration autoload

IC3

E2PROM

C16

C15

TEST

SCL

SDA GND

A0VCC A1

1 2 3 4

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VV5300 Sensor

Component Pa rt No. / Provisional Value Rating / Notes

IC1 VV5300 VVL camera chip (48 pin LCC) IC2 7805 5V regulator IC3 24C01 E2PROM SOIC (8 pin)

C3 10.0 µF

C1,C2, C4-C11 0.1 µF

C12, C13 4.7 µF C14, C15 100pF C16, C17 22pF

C18 1nF

R1 0Ω R2 0Ω R3 0Ω R4 33Ω

R5, R6 2k2Ω

R7 1MΩ R8 10Ω

Preli

inar

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VV5300 Sensor

VLSI VISION LIMITED

UK Headquarters

Aviation House, 31 Pinkhill, EDINBURGH EH12 7BF Scotland Tel:+44 (0) 131 539 7111 Fax:+44 (0)131 539 7141 eMail: [email protected]

VLSI Vision Ltd. reserves the right to make changes t o its products and specifications at any time. Infor mation fur nished by VI SION is beli eve d to be ac curate, but no responsibility is assumed by VISION for the use of said in formation, nor any infringements of patents or of any other third party rights which may result from said use. No license is granted by implication or otherwise under any patent or patent rights of any VISION group company.

USA Western Office

1190 Saratoga Ave., Suite 180, SAN JOSE CA 95129 USA Tel: +1 408 556 1550 Fax: +1 408 556 1564

eMail: [email protected]

inar

USA Eastern Office

571 West Lake Avenue, Suite 12, BAY HEAD NJ 08742 USA Tel: +1 732 701 1101 Fax: +1 732 701 1102

eMail: [email protected]

VLSI Vision agent or distributor

Preli

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