Datasheet VSC880TY Datasheet (VITESSE)

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VITESSE

SEMICONDUCTOR CORPORATION

Data Sheet

VSC880

Features

• 16x16 Synchronous Serial Crosspoint Switch

• Serial Data Rates: 2.0Gb/s

• 32Gb/s Aggregate Data Bandwidth

• Parallel Switches Can Increase Data Bandwidth in Multiples of 32Gb/s

• Designed in Conjunction with the VSC870 Backplane Transceiver

• Automatic Word and Cell Synchronization to the Transceiver

• Two Modes of Operation: Distributed Control Self-routing Packet Mode and Central Control Cell Mode

• Multicast Supported in All Modes

High Performance 16x16

Serial Crosspoint Switch

• Supports Variable Length Packets in Packet Mode

• Built-in Flow Control Channel in Packet Mode

• Supports Cell Synchronization in Cell Mode

• Parallel CPU Interface and Parallel Switch Configuration Interface

• Loopback, Built-in Self Test and Scan Functions

• 5V Tolerant TTL Inputs

• Dual 3.3V/2.5V or Dual 3.3V/2.0V Power Supplies

• Serial Port Quadrants Can be Powered Down

• Available in 304 BGA Package

VSC880 Block Diagram

Serial Port (1 6x)

TXS+/TXS-

RXS+/RXS-

WCLK

REFCLK

TCLKEN

LOCKDET

CCLK

RESET

BSTLPBK

BSTEN

BSTRST

BSTPASS

DRU

CMU

Clock

Gen

BIST Logic

Parallel

Serial

Parallel

Port

Logic

Switch Matrix

Arbitration Logic

and Switch Control

Registers

Status and

Control Registers

VSCTE VSCIPNC VSCOPNC

MEN

FACLPBK CMODE

TESTEN

SCANIN SCANOUT

CEN

DATA[15:0]

FI[3:0]

WEN

ADDR[5:0]

CDATA[7:0]

CWEN

CSEL

INT

RESYNEN

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VITESSE

SEMICONDUCTOR CORPORATION

High Performance 16x16 Serial Crosspoint Switch

Data Sheet

VSC880

General Description

The VSC880 is a 16x16 serial crosspoint switch with serial data rates at 2.125Gb/s. The VSC880 has been designed to operate with the VSC870 backplane transceiver to establish a synchronous high performance switching system with an aggregate bandwidth of 32Gb/s. The switch chip transmits the master word clock (62.5Mb/s), and master cell clock (if used) to all port cards through the serial data channels. The transceivers automatically perform bit alignment, word alignment and cell alignment to the switch chip. The transceiver and switch chip have been optimized for both self-routing and cell-based systems and include special commands for connection requests (selfrouting) and cell synchronous operation (cell based). In addition, a parallel CPU interface can be used to control internal modes and read status information from the switch. A 20-bit interface can als o be used to pro gram the switch matrix in 4 clock cycles. The switch chip runs of f of a 3.3V/2.5V or 3.3V/2.0V power supplies. The serial I/O buffers contain on-chip termination resistors (see Application Note 34).

Pin Descriptions

Pin Name I/O

TXS[15:0]+/

TXS[15:0]-

RXS[15:0]+/

RXS[15:0]-

DATA[15:0] Configuration Data Input I

FI[3:0] Force IDLE Input I

CEN

WEN

ADDR[5:0] Data Address I

CSEL

CDATA[7:0] Status Data Output B

CWEN Control Write Enable I

Transmit Serial Outputs O

Receive Serial Inputs I

Configure Enable I

Wri te E nable I

Chip Select I

Freq Type

2.125Gb/s LVDS

62.5Mb/s TTL

Description

16 high speed serial di fferential transmit channels

16 high speed serial differential receive channels Parallel input signals used to p rog ram t he switc h m atrix in 4

clock cycles when the signal CEN Parallel input signals used to program force IDLE words at

the switch matrix output in 4 clock cycles when the signal CEN

is LOW .

When CEN can be used to program the switch matrix in 4 word clock cycles timed to the WEN signal.

If CEN for loading switch configuration data into DATA[15:0] and FI[3:0].

The address to read and write data through parallel interface CDATA[7:0].

This signal allows several switch chip s to sha re an 8 bi t d ata bus connected to CDATA[7:0]. If CSEL be read or written to CDATA[7:0]. If CSEL outputs will be high impedance and the inputs disabled.

Bidirectional CPU interface for the status and control registers. If CSEL into this port. If CSEL impedance and the inputs will be disabled.

This signal is set HIGH to read the internal status registers through the parallel interface CDATA[7:0]. It is set LOW to write into this interface.

is held LOW , the inputs DATA[15:0] and FI[3:0]

is LOW , this sign al provi des a syn chroniza tion pul se

is LOW, the data will be read or written

is HIGH, the outputs will be high

is LOW.

is LOW, data will

is HIGH, the

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SEMICONDUCTOR CORPORATION

Data Sheet

VSC880

Pin Name I/O

RESYNEN Resynch Enable I

INT

MEN Reserved I

FACLPBK Facility Loop Back I

CMODE Cell Mode I

TESTEN Scan Test Enable I

SCANIN Scan Data In I

SCANOUT Scan Data Out O

WCLK Word Clock O

REFCLK Reference Clock I

TCLKEN Test Clock Enable I

CCLK Cell Clock I

RESET

BSTLPBK

BSTEN Built-in Self Test Enable I

BSTRST Built-in Self Test Reset I

BSTPASS Built-in Self Test Pass O

Interrupt O

Reset I

Built-in Self Test Loop

Back

Freq Type

<1MHz

TTL

<1MHz

TTL

<1MHz

TTL

<1MHz

TTL

<1MHz

TTL

<1MHz

TTL

62.5Mb/s TTL

62.5MHz TTL

<1MHz

TTL

62.5MHz TTL

<1MHz

TTL

<1MHz

TTL

<1MHz

TTL

<1MHz

TTL

<1MHz

TTL

High Performance 16x16

Serial Crosspoint Switch

Description

If RESYNEN is HIGH, all links that have a link error condition will be reinitia lized. This will o verride th e inter nal control register settings.

is LOW, a receive error has occurred in one o f the

If INT

links that has it’s output enable (OE) bit set HIGH and interrupt control register bit set HIGH.

This signal is reserved for future use and should be set LOW during normal operation.

If this signal is set HIGH, all serial inputs are looped back to their serial outputs. This will override the internal control register setting.

CMODE is set HIGH for Cell Mode operation. This signal is used in ATE testing to measure propagation

delay . It is a lso used i n AT E te sting o f the BIS T lo gic . S et to logic LOW in normal operation.

The input signal for measuring propagation delay on the ATE tester.

The output signal for measuring propagation delay on the ATE tester. When TESTEN is set LOW, the longer delay path is enabled.

This is the word clock output. This is the reference clock and the source of the system wide

word clock period. This input is set HIGH in test mode, so that the CMU is

bypassed and the REFCLK becomes the bit clock. This signal is for ATE test only. Set LOW in normal operation.

This is the source of the system wide cell clock. It is internally synchronized to the REFCLK. In Packet mode , set this signal HIGH to enable external switch c onfigu ratio n for BIST.

Global chip reset (active LOW) When BSTLPBK is set HIGH and TESTEN is LOW, all

serial data output signals are looped back to their serial data inputs. If BSTLPBK is set HIGH and TESTEN is HIGH, only ports 0-7 are placed in lo opback.

When BSTEN is HIGH, at-speed built-in self testing is enabled.

The BSTRST signal is set HIGH to reset the PRBS generator and comparator.

The BSTPASS signal is HIGH if BTSEN is HIGH and the PRBS comparator detects the correct pattern in built-in self test mode.

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VITESSE

SEMICONDUCTOR CORPORATION

High Performance 16x16 Serial Crosspoint Switch

Pin Name I/O

LOCKDET CMU Lock Detect O

VSCTE NOR Chain Test Enable I

VSCIPNC NOR Chain Input I

VSCOPNC NOR Chain Output O

VDD1, VDD2,

VDD3, VDD4

VDDA CMU Power Supply P 3.3V Clean power supply for CMU

VSSA CMU Ground P 0V Clean ground for CMU VMM Core Power Supply P 2 ~ 2.5V Core power supply

Serial Port Power

Supplies

Freq Type

<1MHz

TTL

<1MHz

TTL

<1MHz

TTL

<1MHz

VECL

P3.3V

Data Sheet

VSC880

Description

This signal is LOW while the CMU is acquiring lock. Used for ATE testing of the parametric NOR chain in the I/O

frame. Set to logic LOW during normal operation. Used for ATE testing of the parametric NOR chain in the I/O

frame. Leave output open during normal operation. VDD1 = Serial Port 0-3 power supply

VDD2 = Serial Port 4-7 power supply VDD3 = Serial Port 8-11 power supply VDD4 = Serial Port 12-15 power supply

Functional Description

The VSC880 switch can be used in conjunction with the VSC870 transceivers to support two modes of operation: Packet Mode and Cell Mode. In Packet mod e, the ch ip s et pr ovides a sw itching sy stem to s upport v ariable length, self-routing data packets. In Cell Mode, the chip set provides a cell synchronous switching system with a user defined scheduler. In this mode, it can support only fixed length data packets (cells). Routing decisions are carried out in the scheduler and crosspoint configuration is synchronized to a cell clock. The scheduler configures the switch matrix using the parallel interface. To conserve power, each serial port quadrant can be powered down if not used.

The following section gives a detailed functional descrip tion of the operation of the switch chip. Most of the discussion includes some of the transceiver operation (see the VSC870 data sheet). The two major operation modes are described separately in the Packet Mode and the Cell Mode sections.

1.0 Common Features

1.1 Synchronization

1.1.1 Link Characteristic

The serial link is used to connect the switch chip to transceivers. These links operate at 2.125 Gb/s and are initialized simultaneously at power up, or separately when a link error occurs. A link is first bit synchronized, then word synchronized and, if CMODE is HIGH, cell synchronized. In Packet or Cell mode, the switch acts as the master, generating the bit clock along with the word and cell boundary information. The transceivers act as slaves, recovering the bit clock, word clock and cell clock. The transceiver also contains redundant serial inputs and outputs which can be used with a redundant switch chip.

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SEMICONDUCTOR CORPORATION

Data Sheet

VSC880

High Performance 16x16

Serial Crosspoint Switch

1.1.2 Data Scrambling

To allow the VSC 870 CRU to recover the bit clock, a 15% edge transition density m ust be guaranteed on the serial data links. All command words and connection request words contain this required density. In order to get this density on data words, scrambling must be employed by the transceiver (see VSC870 data sheet).

1.1.3 Bit Synchronization

In Packet Mode and Cell Mode, th e switch acts as the sour ce of the bit clock. It multip lies the local 62.5MHz reference clock by 34 to generate a 2.125GHz clock and uses this clock to serialize the 32-bit word and 2 overhead bits. The transceiver receives and feeds this serial data stream to a digital CRU to recover the bit clock and deserialize the data stream to a 32-bit word plus 2 overhead bits at 62.5MHz. The transceiver also uses this recovered clock to serialize its transmit words th at are sent to the switch. In this way, the switch and all the transceivers are frequency-locked to one clock source which is provided by the reference clock on the switch card. Because of this, the switch chip needs to recover only the phase information on the serial receive channel using a data recovery unit (DRU). The DRU is designed as a delay lock loop and remains phase-locked to the incoming data stream as long as the temperature does not change by more than 20 °C after link initialization. If this temperature variation is exceeded, a link error may occur causing the link to reinitialize. Because of this, system reset should be held until the system reaches temperature stability before starting the link initializing process.

1.1.4 Word Synchronization

During power up or at reset, the transceiver can initiate the word synchronization process. First, the transceiver sends reset patterns to the switch to request that the switch starts the initialization process. The switch, upon receiving this request, will send out special ALIGN words. The transceiver receives this serial data stream and word aligns to this ALIGN word by adjusting its own word boundary one bit at a time. Up on detecting the correct word alignment, it starts the transmit word alignment process. In this process, the transceiver continuo usly sends ALIGN words to the switch. The switch uses its own word clock (REFCLK) to detect this ALIGN word. If the transmitters word is not aligned to the switch chip word clock when it arrives at the switch, the switch chip continues to send out ALIGN words. After receiving 32 ALIGN words from the switch chip, the transceiver changes its transmit word boundary by 1 bit position and repeats the p rocess (this limit s the distan ce from the transceiv er to the switch to less than 180ns one way). If the switch detects the transceivers ALIGN word correctly, it sends IDLE words to the transceiver to signal that the transmitter has now word synchronized with the switch. It also clears the internal registers LERR, TERR, DERR and CERR and sets the signal INT successfully initialized (see section 1.4).

HIGH if all the enabled serial channels are

1.1.5 Cell Synchronization

If CMODE is set HIGH, after the word synchronization process completes, the transceiver starts the cell synchronization process. In this process, the transceiver detects the received cell clock (CCLK) sent from the switch embedded in the alignment word. The switch delays the global cell clock to adjust out th e pipeline delay from the transceiver to the switch. The switch ch ip does this by connecting each port to itself during link initialization. By sending an ALIGN words to itself, the transceiver can adjus t the transmit clock until it is properly phase shifted relative to the global cell clock. If cells are sent from the transceiver aligned to this transmit cell clock, they will arrive at the switch aligned to the master cell clock which is originated at the switch. For this alignmen t process to work, the minimum cell size is 8 words (32 bytes).

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SEMICONDUCTOR CORPORATION

High Performance 16x16 Serial Crosspoint Switch

Data Sheet

VSC880

1.1.6 Link Error Detection

There are four types of link errors that can be flagged on the receive serial links. Link errors are detected using

IDLE words. If a link error is detected, a bit in the LERR register is set HIGH for that particular channel (see section

1.4). After every 8 link errors, a bit in the TERR register is set HIGH. If the DRU goes out of range, a bit in the DERR register is set HIGH. If the last word in the cell period is an IDLE word and it does not have b its B[1:0] set HIGH to designate a cell clock, a bit in the CERR register will be set HIGH. If an error bit is set in any of these registers, the

signal can be programmed to go LOW and/or the link can be programmed to automatically start link

INT initialization depending on the value loaded in to the I nterrupt Control R egister ( see section 1.4). These er ror reg ister bits will be cleared if the link is reinitialized, or the registers are read. If the s ignal RESYNEN is set HIGH, link initialization will begin immediately upon the detection of any of these errors. If the switch is used without IDLE words, the user is responsible for detecting parity error conditions and restarting the link initialization process.

1.2 Data Encoding Format

To provide self-routing and cell synchronization, the transceiver and switch require special word formats. Depending on the mode that the switch is u sed in, different word types are recognized by the switch. In both the Packet and Cell Modes, the switch processes both data words and command words. They have the same format in both modes and will be described in following section. The format for the connection request words and header words are described later in the Packet Mode section.

1.2.1 Data Word Format on the Serial Data Lines

The data word format as seen at the serial output of the transceiver or switch chip is shown below. Two overh ead bits are added by the transceiver or switch chip to designate a data word to the receiving switch chip or transceiver. The serial data is transmitted with the MSB first.

33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 B B

1 0

Where:

B[1:0]If Packet Mode, 01=Flow control channel,

D[31:0]32 bit data payload

D D D D 31 30 29 28

If Cell Mode, 01, 10, 11 = data

D D D D 27 26 25 24

10=Flow control channel ,

11=Acknowledge from switch chip or header word to switch chip

D D D D 23 22 21 20

D D D D 19 18 17 16

--------------- Da ta Payload ----------------

D D D D 15 14 13 12

D D D D 11 10 09 08

D D D D 07 06 05 04

D D D D 03 02 01 00

1.2.2 Command Word Format on the Serial Data Lines

The command word format as seen at the serial output of the transceiver or switch chip is shown below. Two overhead bits are added by the trans ceiver or switch to designate a co mmand word (0 0) to the receiving switch chip or transceiver. The serial data is transmitted with the MSB first. In Packet Mode, the IDLE word from the switch always returns the current output connections for the port.

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Data Sheet

VSC880

33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 0 0 1 B B

Where:

B[1:0]00=Undefined (during normal operation) or alignment word

01=Flow control channel, 10=Flow control channel, 11=Acknowledge (from switch chip only) or link initialization reset or cell clock in cell mode

C[4:0]Command type

D[15:0]Optional data payload

High Performance 16x16

Serial Crosspoint Switch

1 0

-- Command -- -- Data --

C C C C C 04 03 02 01 00

00XXX=Link Control (00000=ALIGN word, 00111=IDLE word) 01XX0=Command word for tr ansceiver (01000=set DLYEN/CCKIN value) 10XX0=Command word for switch 11XX0=Command word for receiving port card (TBD)

Default=1010101010101010 IDLE Word from switch=Current switch outputs this port is connected to

D[15] is for port 0, D[0] is for port 15

If C[4:0]=01000, D[3:0]=DLYEN/CCKIN value

D D D D 15 14 13 12

D D D D 11 10 09 08

D D D D 07 06 05 04

D D D D 03 02 01 00

1 0 1 0 1 0 1 0

1.2.3 IDLE Words

IDLE words are the default word used on t he ser ial channe l whe n none o f the other wo rd types are p resent. In most cases, these words are automatically generated by the transceiver or switch chip. In Packet Mode, IDLE words are inserted between pa ckets an d the ID LE wor d from th e switch always returns t he curre nt output c onnections for the port that is receiving the ID LEs. Th ese connection bi ts will be in the s ame locat ion as in the C RQ word. In cell mode, IDLEs will be transmitted from the s witch chip if the f orce IDLE (FI) bit i s set in the contro l registers. IDLE words are also used to detect link error conditions. If the switch chip detects an IDLE word, it uses a bit mask to verify the proper bit pattern within the word.

1.3 Loopback

The VSC880 supports a loopback function at the serial interf aces which is used in built-in self -test mode. If th e BSTLPBK signal is set HIGH and TESTEN is set LOW, the serial transmit data is looped back to the serial receive side for all 16 channels. If the BSTLPB K signal is set HIGH and TESTEN is set HIGH, the serial transmit d ata is looped back to the serial receive side for channels 0-7 only. If the FACLPBK signal is set HIGH, the serial receive signal is looped back to the serial output for all 16 chann els. Each chan nel can also b e pro grammed to be loo ped b ack separately from serial input to serial output b y using the control registers described below. The VSC880 does not support simultaneous BIST and facilty loopback functions (either FACLPBK pin or LPBK[15:0] register).

1.4 Internal Register Definitions

The internal status and control registers are defined in the following table. The address signal ADDR[5:0] is used along with CSEL and HIGH to read from this port. If CSEL

and CWEN to read or write data through the CDATA[7:0] interface. CWEN is set LOW to write

is HIGH, the outputs become high impedance and the inputs become

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SEMICONDUCTOR CORPORATION

High Performance 16x16 Serial Crosspoint Switch

disabled. All data transfer timing is asynch ronous to REF CLK. The Interrupt Control Register is written by the user to mask certain operations. If ICE is set HIGH, th e INT register. If RCE is set HIGH, the link will automatically start link initiali zation if any error bit is set in the CERR register. The corresponding pins can be used for the DERR, TERR and LERR registers. If the INT the Interrupt Status Register can be read to determine which of the four registers received an error.

The CDEL[3:0] bits are used to program a value for the cell clock delay (see section 3.0). The switch matrix status information can be read from the CN and FI registers. A serial link can be forced to reinitialize by writing a HIGH into the RSY register. A serial output can be logically disabled by writing a HIGH into the OE register. A serial input can be forced to loop back dir ectly to a serial ou tput b y wr iting a HI GH into th e LPBK re gister. All registers are cleared upon RESET. Also, the LERR, TERR, DERR and CERR registers are cleared on reading.

Figure 1: Status and Control Register Definition

CDATA[7:0] Bit Position

ADDR[5:0]R/W76543210

X 0 0 0 0 0 R CE DE TE LE Interrupt Status Register

output pin will go LOW i f any error bit is set in the C ERR

Data Sheet

VSC880

signal goes LOW,

X 0 0 0 0 1 R/W RCE RDE RTE RLE ICE IDE ITE ILE Interrupt Control Register X 0 0 0 1 0 R/W BIST CDEL[3:0] BIST and Count Register

X 0 0 0 1 1

X 0 0 1 0 0 R CERR[7:0] CCLK error register LSB X 0 0 1 0 1 R CERR[15:8] CCLK error register MSB X 0 0 1 1 0 R DERR[7:0] DRU error register LSB X 0 0 1 1 1 R DERR[15:8] DRU error register MSB X 0 1 0 0 0 R TERR[7:0] Error threshold register LSB X 0 1 0 0 1 R TERR[15:8] Error threshold register MSB X 0 1 0 1 0 R LERR[7:0] Link error register LSB X 0 1 0 1 1 R LERR[15:8] Link error register MSB

0 0 1 1 0 0 R/W C0[3:0] C8[3:0] Output0/Output8 Config 0 0 1 1 0 1 R/W C1[3:0] C9[3:0] Output1/Output9 Config 0 0 1 1 1 0 R/W C2[3:0] C10[3:0] Output2/Output10 Config 0 0 1 1 1 1 R/W C3[3:0] C11[3:0] Output3/Output11 Config 0 1 0 0 0 0 R/W C4[3:0] C12[3:0] Output4/Output12 Config 0 1 0 0 0 1 R/W C5[3:0] C13[3:0] Output5/Output13 Config 0 1 0 0 1 0 R/W C6[3:0] C14[3:0] Output6/Output14 Config

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Data Sheet

VSC880

CDATA[7:0] Bit Position

ADDR[5:0]R/W76543210

0 1 0 0 1 1 R/W C7[3:0] C15[3:0] Output7/Output15 Config

1 0 1 1 0 0 R S0[3:0] S8[3:0] Output0/Output8 Status 1 0 1 1 0 1 R S1[3:0] S9[3:0] Output1/Output9 Status 1 0 1 1 1 0 R S2[3:0] S10[3:0] Output2/Output10 Status 1 0 1 1 1 1 R S3[3:0] S11[3:0] Output3/Output11 Status 1 1 0 0 0 0 R S4[3:0] S12[3:0] Output4/Output12 Status 1 1 0 0 0 1 R S5[3:0] S13[3:0] Output5/Output13 Status

1 1 0 0 1 0 R S6[3:0] S14[3:0] Output6/Output14 Status 1 1 0 0 1 1 R S7[3:0] S15[3:0] Output7/Output15 Status X 1 0 1 0 0 R/W FI[7:0] Force IDLEs LSB

X 1 0 1 0 1 R/W FI[15:8] Force IDLEs MSB X 1 0 1 1 0 R/W RSY[7:0] Resynch LSB X 1 0 1 1 1 R/W RSY[15:8] Resynch MSB X 1 1 0 0 0 R/W OE[7:0] Output Enable LSB X 1 1 0 0 1 R/W OE[15:8] Output Enable MSB X 1 1 0 1 0 R/W LPBK[7:0] Loopback LSB X 1 1 0 1 1 R/W LPBK[15:8] Loopback MSB

High Performance 16x16

Serial Crosspoint Switch

Where: CE Cell clock errorRCE Resynch on cell errorICE Interrupt on cell error DE DRU error RDE Resynch on DRU errorIDE Interrupt on DRU error TE Threshold errorRTE Resynch on thresh errorITE Interrupt on threshold error LE Link error RLE Resynch on link errorILE Interrupt on link error BIST Set this bit HIGH to test the BIST circuitry CDEL[3:0] Cell clock delay CERR[15:0]Cell clock error register, bit 0 is channel 0 etc, Cleared on read DERR[15:0]DRU error register, bit 0 is channel 0 etc. Cleared on read TERR[15:0]Threshold error register, bit 0 is channel 0 etc. Cleared on read LERR[15:0]Link error register, bit 0 is channel 0 etc, Cleared on read CN[3:0]Switch configuration data. N is the output port number, [3:0] is the input port connected. Default = 0xF. SN[3:0]Output status data. N is the output port num ber, SN[3:2] = 00 for normal operation.

01 for out of synch 10 for word synch in progress 11 for cell synch in progress SN[1] = Output busy in pac ke t mo de SN[0] = Connection valid in packet mode

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High Performance 16x16 Serial Crosspoint Switch

FI[15:0]Force IDLE register, bit 0 is channel 0 etc RESY[15:0]Res ynch register, bit 0 is channel 0 etc OE[15:0]Output enable register, bit 0 is channel 0 etc LPBK[15:0]Facility loopback register, bit 0 is channel 0 etc

Data Sheet

VSC880

1.5 Parallel CPU Interface

There is a parallel 8 bit CPU interface on the VSC880 that can be used to read and write the status and control registers described above. This is an asynchronous interface that was design to operate with many common micro controllers that are available. The functional timing diagrams for a write and a read are shown in the following figures. Timing information can be found in the AC Characteristics section of this data sheet.

Figure 2: CPU Interface Functional Write Cycle Timing

CWEN

CSEL

ADDR

Valid Address

CDATA

Figure 3: CPU Interface Functional Read Cycle Timing

CWEN

CSEL

ADDR

CDATA

Valid Data

Valid Address

Valid Data

Hi-Z

1.6 Parallel Configuration Interface

In addition to reading and writing the switch configuration using the CPU interface as described above, the entire switch matrix can be reprogrammed in 4 word clocks by setting the CEN parallel interface DATA[15:0] contains a 16 bit switch configuration input port, the inpu ts FI[3:0] load the FI bits an d the WEN of switch configuration data an d 16 FI bits into holding register s. All data transfer timing is r elative to REFCLK. After data has been loaded, and if CCLK is HIGH, all 80 bits of data are strobed into the switch matrix and FI control logic. Otherwise, the configuration infor mation is stored in holding reg ist ers until th e next CCLK pulse s trobes it in. Since the CCLK signal is delayed internally in the switch, it can be asserted as early as the WEN strobe in the configuration information.

signal becomes a programming signal as shown in the fig ure below. It takes 4 word clocks to load all 64 bits

signal LOW. If CEN is set LOW, the

signal pulse to

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Data Sheet

VSC880

The switch configuration data for each port is as follows:

High Performance 16x16

Serial Crosspoint Switch

Figure 4: Switch Configuration Interface Functional Timing (CEN=0)

REFCLK

FI[3:0]

DATA[15:0]

WEN

CCLK

F0[3:0] = FI[port9], FI[port8], FI[port1], FI[port0] F1[3:0] = FI[port11], FI[port10], FI[port3], FI[port2] F2[3:0] = FI[port13], FI[port12], FI[port5], FI[port4] F3[3:0] = FI[port15], FI[port14], FI[port7], FI[port6] C0[15:0] = Port9[3:0], Port8[3:0], Port1[3:0], Port0[3:0] C1[15:0] = Port11[3:0], Port10[3:0], Port3[3:0], Port2[3:0] C2[15:0] = Port13[3:0], Port12[3:0], Port5[3:0], Port4[3:0] C3[15:0] = Port15[3:0], Port14[3:0], Port7[3:0], Port6[3:0]

Min. of 5 Cycles

F3F2 C3C2

Switch updated in this cycle

Where FI[portN] is the Force IDLE bit for port N and PortN[3:0] is the input port number to be connected to output

port N.

1.7 Built-in Self-Test

The switch has built-in self-test logic that can be used to verify the high-speed circuit ry as well as the switch matrix while operating at full speed. The built-in self-test mode is enabled by setting the built -in self-test enable (BSTEN) signal HIGH. If the signal BSTLPBK is set HIGH and TESTEN is set LOW, it loops all 16 serial outputs back to the Data Recovery Unit (DRU) at the serial inputs. An internal Pseudo Random Bit Sequence (PRBS) generator connected to the switch matrix at port 0. The random data is sent to port 0, passed through the switch matrix, looped back through the serial interface and returned to the data comparator. If this data matches the correct pattern, BSTPASS is set HIGH. By configuring port 0 to connect to other ports (ports 1 thro ugh 15) through the switch matrix using the parallel configuration interface, the rest of the serial channels (one port at a time) can be tested in turn. For example, port 0 can be connected to port 1 by configuring the switch matrix. The PRBS generator transmits the random data through port 0 to port 1, and the random data is th en l oop ed back from por t 1 to port 0 and the data comparator. To test all 16 ports, the user will need to configure the switch matrix 16 times to test all ports.

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High Performance 16x16 Serial Crosspoint Switch

Figure 5: Built-in Self-Test Functional Timing

REFCLK

ADDR[4:0]

BSTRST

BSTPASS

The signal BSTRST is used to reset the PRBS pattern, and there is a comparator that sets the signal BSTPASS HIGH if the test was successful. The functional timing diagram above shows a typical test sequence. The PRBS pattern generator can also be tested by itself by setting the control register bit BIST HIGH. This loops the output of the pattern generator directly back to the comparator circuit. This test will be typically run before running the tests described above. In this case, the signals BSTEN, BSTRST and BSTPASS will operate as shown in the Figure 5 above.

The BIST test can be run on no more than two ports at a time, for example: port 0→port 3→port 8→port 0.

< 10µS

Data Sheet

VSC880

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Data Sheet

VSC880

High Performance 16x16

Serial Crosspoint Switch

2.0 Packet Mode

2.1 Overview

In Packet Mode (CMODE=LOW), command words can be sent through the transceiver to the switch chip requesting connection to one or multiple outp ut channels. Acknowledge (ACK) informatio n will be returned to the transceiver from the switch allowing the port card to start transmitting data. In this mode of operation, no controller chip is connected to the switch chip as the switch chip handles all arbitration for connection requests. Details on how the transceiver operates in Packet Mode mode can be found in the VSC870 data sheet and the applications note 31: “Design Guide for a Packet Based Switch with Distributed Control”. A picture of a self routing system is shown below. The minimum packet size in this mode of operation is 4 words or 16 bytes.

Figure 6: Packet Mode System

Port Card

TXFIFO

RXFIFO

Trans

Switch Card

VSC870

Switch

Chip

Port Card

TXFIFO

Trans

RXFIFO

VSC870

VSC880

2.2 Data Encoding Format

The data word and command word formats are described in section 1.0. In this section the header word and Connection Request (CRQ) word format at the serial input and serial output of the switch are described.

2.2.1 Header word Format on the Serial Data Lines

The header word format as seen at the serial output of the transceiver or switch chip is shown below. Two overhead bits are added to designate a header word to the receiving chip. The serial data is transmitted with the MSB

If multiple headers are sent in a row, the VSC870 will convert all but the first one into IDLEs.

first.

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High Performance 16x16 Serial Crosspoint Switch

33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 A A

1 0

0 B B 1 1 0

--------------- Data Payload ----------------

0 1 1 0 D D D D

19 18 17 16

D D D D 15 14 13 12

D D D D 11 10 09 08

D D D D 07 06 05 04

D D D D 03 02 01 00

Data Sheet

VSC880

1 0 1 0

Where:

A[1:0]11=to switch chip, 00=from switch chip

B[1:0]00=Undefined,

01=Flow control channel, 10=Flow control channel, 11=Acknowledge to transceiver

D[19:0]20 bit data payload

2.2.2 CRQ Word Format on the Serial Data Lines to the Switch

The CRQ command word format as seen at the output of the transceiver is shown below. Two overhead bits are added by the transceiver to designate a CRQ word to the receiving switch chip. The signal ARB, AOA and BRK are used to control modes of operation in the switch chip. The serial data is transmitted with the MSB first.

33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

0 0 0 B B 1 0

1 0

A A B R O R

B A K ------ Connectio n Bits ------ --Data--

C C C C 00 01 02 03

C C C C 04 05 06 07

C C C C 08 09 10 11

C C C C 12 13 14 15

D D D D 03 02 01 00

1 0 1 0

Where:

B[1:0]00=Undefined,

01=Flow control channel, 10=Flow control channel,

11=Undefined ARB1=Multi Queue arbitration AOA1=Acknowledge on all connections granted, 0=Acknowledge on any connections granted BRK 1=Break previous connection, 0=Do not break previous connection C[0:15] Connection request bit map. Set bit high for each output reque s ted D[3:0] User defined data sent by transmitting port card

2.2.3 CRQ Word Format on the Serial Data Line From the Switch

The CRQ command word format as seen at the output of the switch chip is shown below. Two overhead bits are

added by the switch chip to designate a command word (00) to the transceiver. This word is sent on to the receiving port card when an ACK is sent to the transmitting port card. The command word contains the current active connections for this input in the switch chip. The serial data is transmitted with the MSB first.

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Data Sheet

VSC880

33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 0 0 0 B B 1 0 1 0

Where: B[1:0]00=Undefined,

01=Flow control channel,

10=Flow control channel,

11=Acknowledge BRK 1=This is the CRQ word for the next packet. This bit is used to break the current connection. M[0:15]Current outputs the transmitting channel is connected to D[3:0] User defined data sent by transmitting port card

1 0

BRM M M M

00 01 02 03

K --- --- Active Connectio ns ------ --Data--

M M M M 04 05 06 07

M M M M 08 09 10 11

M M M M 12 13 14 15

High Performance 16x16

Serial Crosspoint Switch

D D D D 03 02 01 00

1 0 1 0

2.3 Receiver Operation

In Packet Mode, the receiver looks for connection request (CRQ) words from the transceiver. All data words and

IDLE words are passed on directly to the switch matrix. If BRK is HIG H, the current connection will be broken before processing the new connection request word. When BRK is LOW, the switch does not break current connections when making a new request. When AOA is HIGH, the switch will send an ACK only if the current switch connections match the C[0:15] bit field. When AOA is LOW, an ACK is sent back to the transceiver when an y connection in the C[0:15] bit field is granted. In both cases, a response word is also returned to the transceiver from the switch. The response word can be embedded into an IDLE word or CRQ word that is sent back to the transceiver. If the transceiver makes a CRQ that requires a response (i.e., a multicast CRQ), the switch uses the flow control channel to force an IDLE word into the receiving data stream by forcing the internal ready to receive (RTR) signal low for one word clock (see the VSC870 data sheet).

The bit field C[0:15] is used to designate the output channels that are to be acted upon for a connection request

operation. To request an output to connect to, set the corresponding bit HIGH. Multiple bits can be set H IGH at the same time for multicast. The sending port card can include 4 bits of data (D[3:0]) in the CRQ word that will be passed on to the destination port card. Two example word sequences from the transceiver o n the serial interface are s hown in the Figure 7. The two overhead bits (BB) are used for signaling on data words (see the VSC870 date sheet).

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Figure 7: Packet Transmission Format from Transceiver

Example 1:

11 BB BB

BB 00 00 00 00

11 BB

Header

D0 D1

CRQ CRQ

CRQ

IDLEs

Header

Data Sheet

VSC880

Example 2:

Start of Packet

End of Packet

Zero or more IDLEs Zero or more IDLEs

11 BB

00 BB

BB 00

11 BB

Header

CRQ

D(N-D)

CRQ

IDLEs

Header

Start of Packet

D words before EOP

End of Packet

2.4 Arbitration

In Packet Mode, if multiple inputs request a connection to the same output, arbitration is performed. Connection

requests come into the switch chip on each word clock, and the arbitration process takes two word clock cycles. Arbitration is round-robin with the last connection to an output getting the lowest priority for that output. For multicast, if BRK is LOW, arbitration will only be perf ormed on the requested connections that are not currently granted. If a port is in the out of synch state, any connection request to this port will be always granted.

In order to improve bandwidth utilization, a system wide mode of operation can be used where the switch matrix

reconfiguration time is delayed D word clocks afte r the time arbitration results ar e determined. This allows the u ser logic to receive arbitration results ahead of time so the port cards do not have to block data wh ile waiting for these results. If the CRQ word is inserted into the current data packet D words before the end of the packet, arbitration results will be known at the port card just as the first word of the next data packet is ready for transmission, thus improving bandwidth utilization. The number D is s elected based on the round trip delay from the time the port submits a CRQ until an ACK is received and the FIFO is ready to send a data word. This value of D is a system wide value and must be used by all port cards. D should be set to a maximum value equal to the round trip delay (typically 8 word clocks).

For Multi Queue connection requests from the transceiv er (ARB = 1), the switch chip performs two levels of

arbitration during two word clock cycles. The first level determines which of the requested outputs are available and holds these outputs. The second level chooses one winner from the available outputs then releases the rest. Because outputs can be blocked during the first level of arbitration, all Muti Queue CRQ commands are held at the s witch chip and continue to request outputs until a co nnection is granted or a header word is detected. If a head er wo rd is detected at the transceiver, a repeated sequence of CRQ words is sent to the switch until a connection is granted. The port number of the granted output is returned to the port card using the two overhead bits (see VSC870 data sheet).

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Data Sheet

VSC880

High Performance 16x16

Serial Crosspoint Switch

2.5 Transmitter Operation

In Packet Mode, the transmitter sends out data words th at come from the switch matrix, adding the appr opriate

overhead bit information for acknowledges, response bits and flow control. Acknowledges are used to signal the transceiver that a connection request has been granted (see the VSC870 data sheet). The response bits are used with the Multi Queue connection request word. The flow control channel is used to pass state information from the receiving port card to the transmitting port card. The switch redirects the flow control signals to the correct output using the current switch connection state information. In the case of multicast where there is more than one receiver, these channels are logically ORed before being sent back to the transmitter. The flow control channel is also used to send response bits from the switch to the transceiver for multi queue mode (see VSC870 data sheet).

Response words are required by the transceiver in Packet Mode. These response words are simply IDLE words

or CRQ words in the data stream that are going back to the transceiver containing port connection status information. If the transceiver receives a connection request word that requires a response, it can use the flow control channel to force an IDLE word into the data stream. When this IDLE arrives at the switch, the switch adds the response data.

2.6 Disconnect Operation

A disconnect can be made to occur automatically after a packet is transmitted through the switch if the packet is

followed by either a CRQ (Connection Request) associated with a new packet, or a null CRQ followed by a null header word. The CRQ associated with the new packet typically has the BRK bit set. This breaks down the old connection before it tries to establish the new connection through arbitration. This new connection is made only when the switch receives the header word. When the old connection is broken, the associated output ports are freed up, becoming available for new connections. The null CRQ is a CRQ with the BRK bit set, and has no output port selected. In this case, the switch chip will break down the old connection(s) and will not establish any new connections. The null CRQ word must be followed by a null (empty) header word. The switch will send IDLE words to the transceivers which have not established a new connection. During the packet transmission, if the sendi ng link goes out of synch, the switch will terminate the connection and send an end of packet word (CRQ with the BRK bit set LOW) to the destination port followed by IDLE words. In this case, the receiving transceiver will receive only one CRQ instead of the two normally received.

2.7 Flow Control Channel

The VSC880 can support a back pressure mechanism by providing a flow control channel. The flow control

channel is time shared with the signaling between the switch chip and the transceiver for acknowledgment and response bits. Therefore, it can only guarantee to pass the state information from input pin at the receiving port card through the switch and to the output pin at the transmitting port card. The main application for this flow control channel is to prevent the FIFO on the receiving side from overflowing. By using this channel, when the receive FIFO is almost full, the transmit FIFO will be disabled from sending data. During the time the switch is sending an ACK or response bits back to the port cards, these flow control bits are dropped by the switch. During a multicast transmission, the flow control channels are ORed in the switch. If a port is in an out of synch state, no flow control back pressure is exerted from this output.

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Data Sheet

VSC880

3.0 Cell Mode

3.1 Overview

In Cell Mode (CMODE = HIGH), a more sophisticated arbitration scheme can be supported by using the

VSC870 and the VSC880 switch in conjunction with a central (user defined) sched uler. In this mode, only fixed length data packets (cells) can be supported. A cell clock is connected to the switch chip, and the switch chip distributes the cell clock to all connected transceivers. The transceivers adjust their transmit cell clocks so that all transceivers send the first word of a cell at such time that it arrives at the switch chip aligned to the switch cell clock (see serial link operation above). In this mode, messages containing port card queue information are sent to the central scheduler using an out of band control bus. Arbitration and flow control information are then sent back to the port cards through the out of band control bus. The scheduler then configures the switch matrix by using the parallel interface. A picture of a cell based system is shown below. Multiple switch chips can be used in parallel to increase system bandwidth (see Application Note 32 “Design Guide for a Cell Based Switch with Central Control”).

Figure 8: Cell Based System

Port Card

Queuing

System

Trans

VSC870

Switch Card

Switch

Chip

Scheduler/

Arbiter

Port Card

Queuing

System

Trans

VSC870

Out-of-band Control Bus

VSC880

3.2 Data Encoding Format

The data word and command word formats are described in section 1.0. Command words use the overhead bits

set to 00. Data words can have overhead bits 01, 10 or 11. The user can use these bits for signaling to the receiving port card. Information such as start of frame and end of frame can be passed through the switch in this manner.

3.3 Receiver Operation

If CMODE is HIGH, the receiver at each port examines the two overhead bits (B[1:0]) of the received word to

determine the word type. If the word is a command word sent from the port card, the switch will respond based on the type of command specified in the C[4:0] bit field. If an IDLE word arrives at the end of the cell clock period and it does not have an embedded cell clock, a cell clock error is flagge d. If it is a data w ord, it is sen t to the sw itch fabric to be routed to its destination along with the user defined overhead bits.

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Data Sheet

VSC880

High Performance 16x16

Serial Crosspoint Switch

3.4 Transmitter Operation

If CMODE is HIGH and the force IDLE register is set LOW, the transmitter sends data words from the switch

fabric. If the force IDLE register is set HIGH, IDLE words are transmitted. At the end of the cell clock period, bits B[1:0] in all IDLE words are set to 11 to embed the cell clock marker. For data words, user defined overhead bits are passed on to the destination as is.

3.5 Delaying The Cell Clock

If out-of-band messaging is used be tween the por t cards and the switch card , there will be a phas e offset between

the cell clock (CCLK) on the switch card, and the transmit cell clock (RTM/TCLK) on the port card. A cell clock delay value can be programmed into the control r egister CDEL[3:0] to set the time the switch is configured after receiving a cell clock. This ad ds 1- 14 word clock s worth of d elay b etween C CLK inpu t to the s witch ch ip an d the cell clock sent to the transceivers from the switch chip. In this way, the transmit cell clock (RTM/TCLK) on the transceivers can be aligned to the cell clock at the switch chip (CCLK). For a typical system design where the transceiver is less then 20” from the switch chip, the default value of 5 can be used. See Application Note 32 for more details.

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AC Characteristics

Table 1: LVDS and TTL Outputs

Parameters Description Min Typ Max Units Conditions

R,TTL

F,TTL

R,LVDS

F,LVDS

DATA[15:0], FI[3:0], WEN

TTL Output Rise Time TTL Output Fall Time LVDS Output Rise Time LVDS Output Fall Time

REFCLK

, CCLK,

CEN

Figure 9: Parallel Data Input Timing Diagram

2.5 ns

2.5 ns 100 ps 100 ps

REFCLK

INSU

INH

Data Sheet

VSC880

10-90% @ 50pF 10-90% @ 50pF 20-80% 20-80%

Table 2: Transmit Data Input Timing Table

Parameter Description Min Typ Max Units

REFCLK

INSU

INH

SKEW

Note: Duty cycle for T

Reference (word) clock period 16 ns Reference clock frequency stabi lit y 100 ppm Reference clock input jitter 7 ps RMS Parallel data setup time with respect to REFCLK 1 ns Parallel data hold time with respect to REFCLK 2 ns REFCLK to REFCLK skew using parallel switch chips 1 ns

is 50% +/- 10% worst case

REFCLK

Figure 10: Parallel Data Output Timing Diagram

INT

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Data Sheet

VSC880

High Performance 16x16

Serial Crosspoint Switch

Table 3: Receive Data Output Timing Table

Parameter Description Min Typ Max Units

RESET

INT

Interrupt pulse w idt h 15 ns RESET, RESYNEN pulse width 64 ns

Figure 11: CPU Interface Write Cycle Timing

CWEN

CSEL

ADDR[5:0]

CDATA[7:0]

Valid Address

Valid Data

Figure 12: CPU Interface Read Cycle Timing

CWEN

CSEL

ADDR[5:0]

CDATA[7:0]

Hi-Z

Valid Address

Valid Data

Hi-Z

Table 4: CPU Interface Timing Table

Parameter Description Min Typ Max Units

CSEL falling edge to valid address 5 ns CSEL inactive between read cycles 10 ns CWEN valid to CSE L falling edge 5 ns CSEL active to CWEN cha nge 5 ns Valid data and addr ess during a write 45 ns CSEL low time during a write 20 ns CSEL cycle time du ri ng a write 55 ns CSEL active to valid data 15 45 ns CSEL deactivate to high impedance data 5 ns CSEL active to low impedance data 0 ns

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DC Characteristics

Table 5: LVDS and TTL Inputs and Outputs

Parameters Description Min Typ Max Units Conditions

∆V

V V

∆V

OH OL

OCM

OUT

ICM

OZB

Output HIGH voltage (TTL) 2.4 ——VIOH = -6.0 mA Output LOW voltage (TTL) —— 0.4 V IOL = +6.0 mA O/P Common Mode Rang e ( LVDS) 1.2 — 2.1 V At Min ∆V Differential Output Voltage (LVDS) 400 — 1000 mV 100Ω across input I/P Common Mode Range (LVDS) 0.8 — 2.5 V At Min ∆V Differential Input Voltage (LVDS) 200 — 1600 mV — Input HIGH voltage (T TL) 2.0 — VDD+1.0 V — Input LOW voltage (TTL) 0 — 0.8 V — Input HIGH current (TTL) —— 500 µAVIN =2.4V Input LOW current (TTL) - 50 ——µAVIN = 0.4V Bi-directional (TTL) HIGH current

3-State Output OFF

500 µAV

Data Sheet

VSC880

OUT

=2.4V

OUT

Hot Swap

The LVDS input and output buffers are subject to hot swap events while being connected and disconnected from the passive backplane. If the input is powered down but still receiving a signal fro m an ou tput, the input mu st tolerate extra input current and power. If the input is powered up but has no input connection, it must go to a valid logic state. The Table 6 below lists the LVDS I/O parameters that relate to hot swap condition.

T a ble 6: Hot Swap LVDS I/O Parameters

Parameters Description Value Units Conditions

CDL

LVDS maximum curr ent delivered per out put pin 10 mA Normal Operation LVDS maximum curr ent allowed per input pin 40 mA VDD = 0V LVDS maximum added power per output pin 60 mW VDD = 0V on VSC870 LVDS input default logic state LOW — Input Open

Power Dissipation

Table 7: Power Supply Currents

Parameter Description (Max) Units

DDA

DDX

Power supply current from VDD, V Power supply current from V Power supply current from each serial data quadrant V Power supply current from VMM (VMM = 2.5V + 5%) 6800 mA Power dissipation (V Power dissipation (VDD = 3.3V+5%, VMM = 2.0V+5%, all quadrant s powered) 28.1 W

DDA (VDDA

= 3.3V+5%, V

(VDD, V

DDA

= 3.3V + 5%) 200 mA

= 2.5V+5%, all quadrant s powered) 30.7 W

= 3.3V + 5%) 1000 mA

DDA

DDX (VDDX

= 3.3V + 5%) 750 mA

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Data Sheet

VSC880

Absolute Maximum Ratings

Power Supply Voltage (VDD) Potential to GND.................................................................................-0.5V to +4V

Power Supply Voltage (V

DC Input Voltage (LVDS inputs) .......................................................................................... -0.5V to V

DC Input Voltage (TTL inputs) .........................................................................................................-0.5V to 5.5V

DC Input Voltage (TTL inputs for CDATA[7:0]).................................................................. -0.5V to V

DC Output Voltage (TTL outputs) ........................................................................................ -0.5V to V

Output Current (TTL outputs).................................................................................................................. +/-50mA

Output Current (LVDS outputs) ................................................................................................................+/-50mA

Case Temperature Under Bias......................................................................................................-55

Storage Temperature .....................................................................................................................-65

NOTE: (1) Caution: Stresses listed under “Absolute Maximum Ratings” may be applied to devices one at a time without causing

permanent damage. Functionality at or exceeding the values listed is not imp lied. Exposure to these values for extended periods may affect device reliability.

) Potential to GND................................................................................-0.5V to +4V

(1)

High Performance 16x16

Serial Crosspoint Switch

DD DD

C to +125oC

C to +150oC

Recommended Operating Conditions

Power Supply Voltage (VDD).................................................................................................................+3.3V %

Power Supply Voltage (V Extended Commercial Operating Temperature Range

)............................................................................ ..................(+2.0V to +2.5V) %

(1)

(T)...............................................................0oC to 85oC

+ 1.0V

+ 1.0V + 1.0V

5±

NOTE: (1) Lower limit of specification is ambient temperature and upper limit is case temperature.

G52191-0, Rev 4.2 Page 23 01/05/01

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Internet: www.vitesse.com

VITESSE

SEMICONDUCTOR CORPORATION

High Performance 16x16 Serial Crosspoint Switch

Package Pin Descriptions

Signal Pin Signal Pin Signal Pin Signal Pin

NC A01 FI[2] B15 VDDA D06 VDD1 G04 VSS A02 VMM B16 NC D07 VDD4 G20 VSS A03 BSTLPBK B17 VMM D08 RXS[14]- G21 VSS A04 NC B18 VDD D09 VSS G22

NC A05 NC B19 VMM D10 TXS[14]+ G23

REFCLK A06 NC B20 VMM D11 VDD1 H01

CCLK A07 VSS B21 VDD1 D12 TXS[1]- H02

VSS A08 VSS B22 VMM D13 VDD1 H03

DATA[2] A09 VSS B23 VMM D14 RXS[1]+ H04 DATA[5] A10 NC C01 VDD D15 RXS[14]+ H20

DATA[6] A11 VSS C02 VMM D16 VDD4 H21 DATA[10] A12 NC C03 BSTEN D17 TXS[14]- H22 DATA[13] A13 NC C04 VDD D18 VDD4 H23 DATA[14] A14 NC C05 VSS D19 RXS[2]- J01

FI[1] A15 VSS C06 NC D20 VSS J02

VSS A16 VMM C07 VDD4 D21 TXS[2]+ J03

WEN

BSTRST A18 DATA[0] C09 VMM D23 VDD4 J20

NC A19 DATA[4] C10 RXS[0]- E01 TXS[13]+ J21 VSS A20 DATA[7] C1 1 VSS E02 VSS J22 VSS A21 VMM C12 TXS[0]+ E03 RXS[13]- J23 VSS A22 DATA[12] C13 VDD1 E04 NC K01

NC A23 DATA[15] C14 VDD4 E20 RXS[2]+ K02 VSS B01 FI[3] C15 TXS[15]+ E21 VDD1 K03 VSS B02 CEN VSS B03 VMM C17 RXS[15]- E23 TXS[13]- K20

NC B04 VSS C18 VSS F01 VDD4 K21

NC B05 NC C19 RXS[0]+ F02 RXS[13]+ K22

NC B06 VSS C20 VDD1 F03 VSS K23

TCLKEN B07 NC C21 TXS[0]- F04 RXS[3]- L01

VMM B08 VSS C22 TXS[15]- F20 RXS[3]+ L02 DATA[1] B09 NC C23 VDD4 F21 NC L03 DATA[3] B10 VMM D01 RXS[15]+ F22 VSS L04 DATA[8] B11 NC D02 VSS F23 VSS L20 DATA[9] B12 VDD1 D03 TXS[1]+ G01 NC L21

DATA[11] B13 NC D04 VSS G02 RXS[12]+ L22

FI[0] B14 VSSA D05 RXS[1]- G03 RXS[12]- L23

A17 RESET C08 NC D22 VDD1 J04

C16 VSS E22 TXS[2]- K04

Data Sheet

VSC880

Page 24 G52191-0, Rev 4.2

Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com

Internet: www.vitesse.com

01/05/01

VITESSE

SEMICONDUCTOR CORPORATION

Data Sheet

VSC880

High Performance 16x16

Serial Crosspoint Switch

Signal Pin Signal Pin Signal Pin Signal Pin

VMM M01 RXS[10]- T23 VDD Y15 VMM AB08

VDD1 M02 VDD2 U01 VDD Y16 NC AB09

TXS[3]- M03 TXS[6]- U02 CDATA[4] Y17 FACLPBK AB10

TXS[3]+ M04 VDD2 U03 VDD Y18 RESYNEN AB11

TXS[12]+ M20 RXS[6]+ U04 VSS Y19 VSCTE AB12

TXS[12]- M21 RXS[9]+ U20 VMM Y20 ADDR[4] AB13

VDD4 M22 VDD3 U21 TXS[8]+ Y21 CSEL

VMM M23 TXS[9]- U22 NC Y22 NC AB15

VMM N01 VDD3 U23 RXS[8]- Y23 VMM AB16

VDD2 N02 TXS[6]+ V01 VMM AA01 CDATA[2] AB17

TXS[4]- N03 VS S V02 VDD2 AA02 CDATA[5] AB18

TXS[4]+ N04 RXS[6]- V03 VMM AA03 CDATA[7] AB19

TXS[11]+ N20 VDD2 V04 VSS AA04 NC AB20

TXS[11]- N21 VDD3 V20 VSCIPNC AA05 VSS AB21

VDD3 N22 RXS[9]- V21 VSS AA06 VSS AB22

VMM N23 VSS V22 VSS AA07 VSS AB23

RXS[4]- P01 TXS[9]+ V23

RXS[4]+ P02 VSS W01 NC AA09 VSS AC02

VSS P03 RXS[7]+ W02 SCANIN AA10 VSS AC03

NC P04 VDD2 W03 TESTEN AA11 VSS AC04

VSS P20 TXS[7]- W04 VMM AA12 NC AC05

NC P21 TXS[8]- W20 ADDR[3] AA13 BSTPASS AC06

RXS[11]+ P22 VDD3 W21 ADDR[0] AA14 INT

RXS[11]- P23 RXS[8]+ W22 NC AA15 VSS AC08

NC R01 VSS W23 CDATA[1] AA16 MEN AC09

RXS[5]+ R02 RXS[7]- Y01 VSS AA17 NC AC10

VDD2 R03 NC Y02 VSS AA18 CMODE AC11

TXS[5]- R04 TXS[7]+ Y03 NC AA19 ADDR[5] AC12

TXS[10]- R20 VMM Y04 NC AA20 ADDR[2] AC13

VDD3 R21 VSS Y05 VMM AA21 ADDR[1] AC14

RXS[10]+ R22 VDD Y06 VDD3 AA22 CWEN

VSS R23

RXS[5]- T01 VDD Y08 NC AB01 CDATA[0] AC17

VSS T02 VDD Y09 VSS AB02 CDATA[3] AC18

TXS[5]+ T03 VMM Y10 VSS AB03 CDATA[6] AC19

VDD2 T04 VMM Y11 NC AB04 VSS AC20 VDD3 T20 VSS Y12 VSCOPNC AB05 VSS AC21

TXS[10]+ T21 VMM Y13 NC AB06 VSS AC22

VSS T22 VMM Y14 WCLK AB07 VSS AC23

SCANOUT

Y07 VMM AA23 VSS AC16

LOCKDET

AA08 VSS AC01

AB14

AC07

AC15

G52191-0, Rev 4.2 Page 25 01/05/01

Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com

Internet: www.vitesse.com

VITESSE

SEMICONDUCTOR CORPORATION

High Performance 16x16 Serial Crosspoint Switch

Package Information

Data Sheet

VSC880

304 BGA Package

Page 26 G52191-0, Rev 4.2

Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com

Internet: www.vitesse.com

01/05/01

VITESSE

SEMICONDUCTOR CORPORATION

Data Sheet

VSC880

High Performance 16x16

Serial Crosspoint Switch

Package Thermal Characteristics

The VSC880 is packaged in a thermally enhanced 31mm 304TBGA with an embedded heat sink. The heat sink

surface configurations are shown in the package drawings. With natural convection, the junction to case thermal

resistance is estimated to be 0.45 Table 12.3. Note: The VSC880 is not guaranteed to operate under cold start conditions. If the ambient temperature is

C, 15 seconds after power is applied, the case temperature will be at least 30oC, at which point it will be at thermal

0 equilibrium and ready for operation.

Table 8: Theta Junction-to-Ambient versus Air Velocity

Junction-to-Ambient Thermal Resistance

Air Velocity

(LFPM)

0 17.5 13.0 100 15.0 11.0 200 13.0 10.0 400 11.0 9.0 600 10.0 8.0

Low Conductivity

2-Layer Board

C/W. The approximate air flow versus thermal resistance relationship is shown in

(

C/W)

High Conductivity

4-Layer Board

Ordering Informatio n

The order number for this product is formed by a combination of the device number and package type.

VSC880

Device Type

High Performance 16x16 Serial Crosspoint Switch

Notice

Vitesse Semiconductor Corporation (“Vitesse”) provides this docum ent for informational purposes on ly. All in formation in this docu ment, including descriptions of features, functions, performance, technical specifications and availability, is subject to change without notice at any time. Nothing contained in this docume nt shall be con strued as extendi ng any warran ty or promise , express or impl ied, that any Vitesse product will be available as described or will be suita bl e for or will accomplish any particular ta sk.

Vitesse products are not intended for use in life support appliances, devices or systems. Use of a Vitesse product in such applications without written consent is pr ohibited.

Package

TY: 304 BGA

Extended Commerical Temperature: 0°C ambient to +85°C case

G52191-0, Rev 4.2 Page 27 01/05/01

Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com

Internet: www.vitesse.com

VITESSE

SEMICONDUCTOR CORPORATION

High Performance 16x16 Serial Crosspoint Switch

Data Sheet

VSC880

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Page 28 G52191-0, Rev 4.2

Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com

Internet: www.vitesse.com

01/05/01

Datasheet VSC880TY Datasheet (VITESSE)

Specifications and Main Features

Frequently Asked Questions

User Manual