Datasheet VSC8169QR Datasheet (VITESSE)

VITESSE

SEMICONDUCTOR CORPORATION

Preliminary Data Sheet

VSC8169

OC-48 (FEC) 16:1 SONET/SDH

MUX with Clock Generator

Features

• 16:1 Multiplexer Up to 2.7Gb/s

• Targeted for SONET OC-48 / SDH STM-16 (FEC)
Applications

• Differential LVPECL Low-Speed Interface

• On-Chip PLL-Based Clock Generator

• 128-Pin 14x20mm PQFP Package

• Single +3.3V Supply

General Description

The VSC8169 is a 16:1 multiplexer with integrated clock generator for use in SONET/SDH systems oper-

ating at a standard 2.48832Gb/s data rate or a forward error correction (FEC) data rate up to 2.7Gb/s. The inter­nal clock generator uses a Phase-Locked Loop (PLL) to multiply either a 77.76MHz (up to 84.38MHz-FEC) or
a 155.52MHz (up to 168.75MHz -FEC ) reference clock in order to provide the 2.48832GH z (up to 2.7G Hz ­FEC) clock for internal logic and outp ut retiming. For use with th e VSC9210 FEC Encoder/ Decoder chipset
running at 2.654208Gb/s, a refer ence clo ck of 82.9 44MHz (seri al rate di vided by 32) should be used. The 16 -bit
parallel interface incorporates an on-board FIFO eliminating loop timing design issues by providing a flexible
parallel timing architecture. The device operates using a 3.3V power supply, and is packaged in a thermally­enhanced plastic package. The thermal performance of the 128-pin PQFP allows the use of the VSC8169 with­out a heat sink under most thermal conditions.

VSC8169 Block Diagram

CLK16I+

CLK16I-

D0+

D0-

D15+

D15-

REFCLKO+

REFCLKO-

Reset

CLK16O+

CLK16O-

REFCLK+

REFCLK-

F_FREQSEL

Input Register

Divide

by 2

Write

Pointer

16x5 FIFO

Read

Pointer

Divide by 16

2.6GHz
PLL

FIFO

Control

Output
Retime

DO+
DO-

CLKO+
CLKO-

FIFO_WAR

G52230-0, Rev 3.6 Page 1
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Internet: www.vitesse.com

VITESSE

SEMICONDUCTOR CORPORATION

OC-48 (FEC) 16:1 SONET/SD H

MUX with Clock Generator

Preliminary Data Sheet

VSC8169

Functional Description

Low-Speed Interface

The Upstream Device should use the CLK16O as the timing source for its final output latch (see Figure 1).
The Upstream Device should then generate a CLK16I that is phase aligned with the data. The VSC8169 will
latch D[15:0]

CLK16I (see Table 2). In addition to the CLK16O clock output, there also exi sts a utili ty REFCLKO output sig­nal, which is a clock with the same rate as that presented at the REFCLK input.

A FIFO exists within the VS C8169 to elimina te difficult system loop timing issues . Once the PLL h as
locked to the reference clock, RESET must be held low for a minimum of five CLK16 cycles to initialize the
FIFO, then RESET should be set high and held constant for continuous FIFO operation. For the transparent
mode of operation (no FIFO), simply hold RESET at a constant low state (see Figure 2).

The use of a FIFO permits the system designer to tolerate an arbitrary amount of delay between CLK16O
and CLK16I. Once RESET is asserted and the FIFO initialized, the delay betw een CLK16O and CLK16I can
decrease or increase up to one period of the low-speed clock (6.4ns). Should this delay drift exceed one period,
the write pointer and the read pointer could point to the same word in the FIFO, resulting i n a loss of transmitted
data (a FIFO overflow). In the event of a FIFO overflow, an active low FIFO_WARN signal is asserted (for a
minimum of five CLK16I cycles) which can be used to initiate a reset signal from an external controller.

The CLK16O
transmission line can be DC terminated with a split-end termin ation scheme (see Fig ure 3), or DC terminated by
50

Ω to V

substituted for the traditional 50
ods. Figure 5 illustrates an example AC-coupling method for the occasion when the downstream device pro­vides the bias point for AC-coupling. If the downstream device were to have interna l termination, the line to
line 100

± on the rising edge of CLK16I+. The da ta must meet setup and hold times with respect to

± output driver is a LVPECL output driver designed to drive a 50Ω transmission line. The

-2V on each line (see Figure 4). At any time, the equivalent split-end termination technique can be

CC

Ω to V

Ω resistor may not be necessary.

-2V on each line. AC-coupling can be achieved by a number of meth-

CC

Figure 1: Low-Speed Systems Interface

CLK16I

x16

Upstream

Device

CLK16O

REFCLK

2.6GHz
PLL

Page 2 G52230-0, Rev 3.6

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Write

Read

16 x 5 FIFO

VSC8169

Divide by 16

01/02/01

VITESSE

SEMICONDUCTOR CORPORATION

Preliminary Data Sheet

VSC8169

PLL locked to reference clock.

Minimum 5 CLK16 cycles

RESET

Holding RESET “low” for a minimum of 5 CLK16 cycles, then setting “high” enables FIFO operation.
Holding RESET constantly “low” bypasses the FIFO for transparent mode operation.

Figure 3: Split-End DC Termination of CLK16O+/-, REFCLKO+/-

VSC8169

Figure 2: Enabling FIFO Operation

FIFO Mode Operation

Transparent Mode Operation

Split-end equivalent termination is ZO to V

R1 = 125Ω R2 = 83Ω, Zo=50Ω, V

Z

o

TERM

TERM

= VCC-2V

OC-48 (FEC) 16:1 SONET/SDH

MUX with Clock Generator

V

CC

R1

R1

Z

o

R1||R2 = Z

VCCR2 + VEER1

R1+R2

O

= V

TERM

V

EE

R2

Figure 4: Traditional DC Termination of CLK16O+/-, REFCLKO+/-

VSC8169

Z

O

Z

O

50Ω

VCC-2V

R2

50Ω

G52230-0, Rev 3.6 Page 3
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VITESSE

SEMICONDUCTOR CORPORATION

OC-48 (FEC) 16:1 SONET/SD H

MUX with Clock Generator

Figure 5: AC Termination of CLK16O+/-, REFCLKO+/-

VSC8169

High-Speed Data and Clock Output

The high-speed data and clock outpu t driver s consist of a dif f erenti al pair desi gned to dri ve a 50Ω tran s mis-

sion line. The transmission line should be terminated with a 100
ment outputs (see Figure 6). Connection to a termination voltage is not required. The output driver is back
terminated to 50
driver must still be terminated differentially at the load with a 100
puts. The high-speed clock output can be powered down for additi onal power savi ngs. To power down the high­speed clock, tie the associated pins to V

Ω on-chip, providing a snubbing of any refl ect ion s . If used sin gle- ended , the high-speed output

Z

o

Z

o

50Ω

(see Table 3, Package Pin Id entifications, pins 5,6,7).

CC

50Ω

V

CC

Ω resistor at the load between true and comple-

Ω resistor between true and complement out-

Preliminary Data Sheet

VSC8169

100nF

100nF

-2V

downstream

bias point
generated
internally

Figure 6: High-Speed Output Termination

V

CC

50Ω

Pre-Driver

V

EE

Clock Generator

An on-chip PLL generates the 2.48832GHz (or up to 2.7GHz for FEC) transmit clock from the externally
provided REFCLK input. The on-chip PLL uses a low phase noise reactance-based Voltage Controlled Oscilla­tor (VCO) with an on-chip loop filter. The loop bandwidth of the PLL is within the SONET specified limit of
2MHz.

50Ω

100Ω

Z0 = 50Ω

Page 4 G52230-0, Rev 3.6

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01/02/01

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SEMICONDUCTOR CORPORATION

Preliminary Data Sheet

VSC8169

OC-48 (FEC) 16:1 SONET/SDH

MUX with Clock Generator

The customer can select to provide either a 77.76MHz (up to 84.38MHz- FEC) reference (recommended),
or the 2x of that reference, 155.52MHz (up to 168.75MHz-FEC). REF_FREQSEL is used to select the desired
reference frequency. REF_FREQSEL = “0” designates REFCLK

input as 77.76MHz (up to 84.38MHz-FEC),

REF_FREQSEL = “1” designates REFCLK input as 155.52MHz (up to 168.75MHz - FEC) . For use with the
VSC9210 FEC Encoder/Decoder chipset running at 2.654208Gb/s, REF_FREQSEL = “0” should be selected
with the REFCLK

input as 82.944MHz (serial rate divided by 32).

The REFCLK should be of high quality since noise on the REFCLK below the loop band width of the PLL
will pass through the PLL and appear as jitter on the output. Preconditioning of the REFCLK signal with a
VCXO may be required to avoid passing REFCLK noise with greater than 4ps RMS of jitter to the output. The
VSC8169 will output the REFC LK noise in add ition to the intr insic jitte r from the VSC816 9 itself duri ng such
conditions.

Low-Speed Inputs

The incoming low-speed data and reference clock input are received by LVPECL inputs D[15:0] and REF­CLK. Off-chip termination of these inputs is required. For AC-coupling, a bias voltage suitable for AC-cou­pling needs to be provided. See Figure 7 for external biasing resistor scheme..

In most situations these inputs will have high transition density and little DC offset. However, in cases
where this does not hol d, d irect DC con nect io n i s possi bl e. Al l ser ia l d at a i nputs have the same circuit topology,
as shown in Figure 7. If the input signal is dri ven dif feren tial ly and DC-cou pled to the part, t he mid-poi nt of the

V

input signal swing should be centered a bout this common mode reference voltage (

) and not exceed the

CMI

maximum allowable amplitude. For single -ended , DC-coupli ng operati ons, it is recommend ed that th e user pro­vides an external reference voltage. The external reference should have a nominal value equivalent to the com­mon mode switch point of the DC-coupled signal, and can be connected to either side of the differential gate.

Figure 7: AC Termination of Low-Speed LVPECL REFCLK, D[15:0] Inputs

Split-end equivalent te r m ination is ZO to V

Chip Boundary

VCC = 3.3V

V

CC

R1

Z

O

Z

C

IN

EE

CC

C

EE

R2

R1

IN

R2

VEE = 0V

V

V

O

V

R1 = 83Ω R2 = 125Ω, Zo=50Ω, V

R1||R2 = Z

VCCR2 + VEER1

O

R1+R2

TERM

= V

TERM

= VCC-2V

Term

CIN TYP = 100nF
for AC operation

G52230-0, Rev 3.6 Page 5
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Internet: www.vitesse.com

VITESSE

SEMICONDUCTOR CORPORATION

OC-48 (FEC) 16:1 SONET/SD H

MUX with Clock Generator

Supplies

Preliminary Data Sheet

VSC8169

The VSC8169 is specified as a LVPECL device with a single positive 3.3V supply. Should the user desire
to use the device in an ECL en viro nment wit h a n egat i ve 3.3 V su pply, then V

-3.3V. If used with V

tied to -3.3V, the TTL control signals are still referenced to VEE.

EE

will be ground and VEE will be

CC

Decoupling of the power supplies is a critical element in maintaining the proper operation of the part. It is
recommended that the V
on each V

power supply pin as close to the package as possible. If room permits, a 0.001µF capacitor should

CC

also be placed in parallel with the 0.1
low-inductance ceramic SMT X7R devices. For the 0.1

0.01

µF and 0.001µF capacitors can be either 0603 or 0402 packages.

Extra care needs to be taken when decoupling the analog power supply pins (labeled V

power supply be decoupled using a 0.1µF and 0.01µF capacitor placed in parallel

CC

µF and 0.01µF capacitors mentioned above. Recommended capacitors are

µF capacitor, a 0603 package should be used. The

). In order to

CCANA

maintain the optimal jitter and loop bandwidth characteristics of the PLL contained in the VSC8169, the analog
power supply pins sh ould be filtered fr om the main pow er supply with a 10
ferrite bead may be used to provide the isolation. The 0.1

µF and 0.01µF decoupling capacitors are still required

µH C-L-C pi filter. If preferred, a

and must be connected to the supply pins between the device and the C-L-C pi filter (or ferrite bead).

For low frequency decoupling, 47

µF tantalum low inductance SMT caps are sprinkled over the board’s

main +3.3V power supply and placed close to the C-L-C pi filter.

If the device is being used in an ECL environment with a -3.3V supply, then all references to decoupling
V

must be changed to VEE, and all references to decoupling 3.3V must be changed to -3.3V.

CC

Figure 8: PLL Power Supply Decoupling Scheme

10 H

V

CC

10 F

0.1 F

V

EE

V

EE_ANA

0.01 F0.1 F

V

CC_ANA

Page 6 G52230-0, Rev 3.6

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Preliminary Data Sheet

VSC8169

AC Characteristics

Figure 9: Parallel Input Data and Clock Timing Waveform

CLK16I+

Parallel Data Clock Input

TXIN[0:15]+, TXPRTYIN

Parallel Data Inputs

CLK16O+

Parallel Data Clock Output

Figure 10: Serial Data and Clock Output Phase Timing Waveform

t

DSU

Valid Data 1

= don't care

OC-48 (FEC) 16:1 SONET/SDH

MUX with Clock Generator

CLK16

PER

t

DH

Valid Data 2

Differential Serial Data Output

DO+

CLKO+

Differential Clock Output

CLKO

PER

D15

MSB

t

SET

NOTE: Bit 15 (MSB) is received first, Bit 0 (LSB) is received last.

D14

t

HOLD

D13

Time

D1 D0

LSB

G52230-0, Rev 3.6 Page 7
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SEMICONDUCTOR CORPORATION

OC-48 (FEC) 16:1 SONET/SD H

Preliminary Data Sheet

MUX with Clock Generator

Table 1: AC Characteristics

Parameters Description Min Typ Max Units Conditions

t

DSU

t

DH

t

DOR,tDOF

, t

t

CLKR

CLK16O
CLKI

D

RCK

D

CLKO

D

CLKO

PER

CLK16O

t

SET

t

HOLD

CLKF

D

PER

Data setup time to the rising
edge of CLK16I+

Data hold time after the rising
edge of CLK16+

DO± rise and fall time ——120 ps
CLK16O± rise and fall times ——250 ps S ee Figures 3 and 4

CLK16O± du t y cy cle 40 — 60 %
CLK16I± duty cycle 30 — 70 % Assuming 10% disto rtion of CLKO
Reference Clock duty cycle 40 — 60 %
CLKO duty cycle 40 — 60 %

CLKO period — 401.9 — ps

CLK16O period — 6.4 — ns
DO setup time with respect to

rising CLKO edge
DO hold time with respect to

rising CLKO edge

0.75 ——ns

1.0 ——ns

— 90 — ps

— 310 — ps

20% to 80% into 100Ω load
See Figure 6

SONET-based 77.76MHz or

155.52MHz reference clock
SONET-based 77.76MHz or

155.52MHz reference clock
Inverting CLKO will switch

(approx) t
Inverting CLKO will switch

(approx) tset and thold values.

SET

VSC8169

and t

HOLD

values.

Clock Multiplier Performance

T

DJ

T

CJ

Jitter

tol

Output data jitter —— 4ps

Output clock jitter —— 4ps

Jitter tolerance ————Exceeds SONET/SDH mask
Tuning Range -100 +100 ppm

Figure 11: Differential and Single-Ended Input/Output Voltage Measurement

b

a

b

a

* Differential swing (α) is specified as | b - a | ( or | a - b | ), as is the single-ended swing.

Differential swing is specified as equal in mag nitud e to sing le -end ed swing.

Single
Ended
Swing

Differential

Swing

=

=

rms, tested to SONET specification
(12kHz to 20MHz) with 2ps rms
jitter on REFCLK.

rms, tested to SONET specification
(12kHz to 20MHz) with 2ps rms
jitter on REFCLK.

α

α

Page 8 G52230-0, Rev 3.6

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SEMICONDUCTOR CORPORATION

Preliminary Data Sheet

VSC8169

OC-48 (FEC) 16:1 SONET/SDH

MUX with Clock Generator

T a ble 2: DC Characteristics (Over recommended operating conditions).

Parameters Description Min Typ Max Units Conditions

-

V

V

OH(DO)

V

OL(DO)

∆V

OD(DO)

∆V

OCLK(CLKO)

V

CMO

R

DO

V

OH

V

OL

V

IH

V

IL

I

IH

I

IL

R

i

∆V

I

V

CMI

V

OH

V

OL

V

IH

V

IL

I

IH

I

IL

V

CC

P

D

I

CC

Output HIGH voltage (DO)

Output LOW voltage (DO)
Data output differen tial voltage

(DO)
CLK output differential vo lta ge

(CLKO)

CC

0.825
V

CC

1.30
550 — 900 mV

500 — 900 mV

Output common-mode voltage 2.10 — 3.00 V
Back termination impedan ce 40 — 60 Ω Guaranteed, but not tested
Output HIGH voltage (CLK 16 O ,

REFCLKO±)
Output LOW voltage (CLK16O,

REFCLKO±)
Input HIGH voltage (LVPECL)

Input LOW voltage (LVPECL)

VCC-

1.020
VCC-

2.000
V

CC

1.100
V

CC

2.0
Input HIGH current (LVPECL) ——200 µA VIN=VIH(max)
Input LOW current (LVPECL) -50 ——µA VIN=VIL(min)
Input resistance (L VPECL ) 10k ——Ω
Input differential volta ge

(LVPECL)
Input common-mode voltage

(LVPECL)

200 ——mV

VCC-

1.5
Output HIGH voltage (TTL) 2.4 ——VI
Output LOW voltage (TTL) — 0.5 V I
Input HIGH voltage (TTL) 2.0 — 5.5 V
Input LOW voltage (TTL) 0.0 — 0.8 V
Input HIGH Current (TTL) ——500 µA V
Input LOW Current (TTL) ——-500 µA V
Supply voltage 3.14 — 3.47 V 3.3V± 5%
Power dissipation — 1.2 1.7 W Outputs open, VCC = VCC max
Supply current — 350 4 90 mA Ou tputs open, VCC = VCC max

-

-

-

— V

—

—

0.700

—

1.620

—

0.700

—

1.540

—

CC

V

CC

0.50

V

CC

VCC-

V

CC

V

CC

V

CC

0.5

V See Figure 12

­V See Figure 12

­V See Figure 12

V See Figure 12

­V

­V

­V

100Ω termination between DO±
at load

100Ω termination between DO±
at load

= -1.0 mA

OH

= +1.0 mA

OL

= 2.4V

IN

= 0.4V

IN

G52230-0, Rev 3.6 Page 9
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SEMICONDUCTOR CORPORATION

OC-48 (FEC) 16:1 SONET/SD H

MUX with Clock Generator

Figure 12: Parametric Measurement Information

PECL Rise and Fall Time

T

r

80%

20%

T

f

Parametric Test Load Circuit

High-Speed Data Output

Z0 = 50Ω

Preliminary Data Sheet

VSC8169

Parametric Test Load Circuit

Serial Output Load

Z0 = 50Ω

VCC-2V

50Ω

50Ω

V

CC

Absolute Maximum Ratings

Power Supply Voltage, (VCC)..........................................................................................................-0.5V to +3.8V

DC Input Voltage (Differential inputs)....................................................................................-0.5V to V

DC Input Voltage (TTL inputs) .......................................................................................................-0.5V to +5.5V

DC Output Voltage (TTL Outputs).........................................................................................-0.5V to V

Output Current (TTL Outputs)................................................................................................................... ±50mA

Output Current (Differential Outputs).........................................................................................................±50mA

Case Temperature Under Bias......................................................................................................-55

NOTE: (1) CAUTION: Stresses listed under “Absolute Maximum Ratings” may be applied to devices one at a time without caus-

ing permanent damage. Functionality at or above the values listed is not implied. Exposure to these values for extended
periods may affect device reliability.

(1)

+0.5V

CC

+ 0.5V

CC

o

C to +125oC

Recommended Operating Conditions

Power Supply Voltage, (VCC).................................................................................................................+3.3V+5%

Operating Temperature Range ........................................................... 0

o

C Ambient to +85oC Case Temperature

ESD Ratings

Proper ESD procedures should be us ed when han dling t his prod uct. T he VSC8169 i s rate d to the foll owing ESD
voltages based on the human body model:

1. All pins are rated at or above 1500V.

Page 10 G52230-0, Rev 3.6

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SEMICONDUCTOR CORPORATION

Preliminary Data Sheet

VSC8169

Package Pin Descriptions

VCC

128

NC
NC
NC

VCC
VEEP_CLK
VEEP_CLK
VEEP_CLK

VCC

CLKO+

CLKO-

VCC

VCC

NC

NC
VEE
VEE
VEE

VCC
DO+
DO–
VCC

NC

VCC
VCC
VCC

VEE
VEE
VEE
VEE
VEE

NC

NC

NC

NC

NC

NC

NC

REF_FREQSEL

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38

VEE

VEENCNC

127

126

Figure 13: Pin Diagram

Top View—128-Pin PQFP

VCC_ANA

VEE_ANA

REFCLKO–

REFCLKO+

VEE

VCC

REFCLK–

125

124

123

122

121

120

119

118

117

VSC8169

REFCLK+NCNCNCNCNCVEE

116

115

114

113

112

111

110

OC-48 (FEC) 16:1 SONET/SDH

MUX with Clock Generator

D15+

D15–

VCC

D14+

D14–NCVCC

109

108

107

106

105

104

103

VCC

102

D13+

101

D13–

100

VCC

99

D12+

98

D12–

97

VEE

96

D11+

95

D11–

94

VCC

93

D10+

92

D10–

91

VCC

90

D9+

89

D9–

88

VEE

87

D8+

86

D8–

85

VCC

84

D7+

83

D7–

82

VCC

81

D6+

80

D6–

79

VEE

78

D5+

77

D5–

76

VCC

75

D4+

74

D4–

73

VCC

72

D3+

71

D3–

70

VEE

69

D2+

68

D2–

67

VCC

66

NC

65

39404142434445464748495051525354555657585960616263

VEE

VCC

NCNCNCNCNC

RESET

Internet: www.vitesse.com

VCC

VEE

CLK16O+

VCC

CLK16O–

VEE

VCC

FIFO_WARN

G52230-0, Rev 3.6 Page 11
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CLKI–

CLKI+

VEE

D0–

D0+

VCC

D1–

D1+

NC

64

VCC

VITESSE

SEMICONDUCTOR CORPORATION

OC-48 (FEC) 16:1 SONET/SD H

MUX with Clock Generator

Table 3: Package Pin Identification

Pin # Name I/O Level Description

1NC——No connect, leave unconn ected
2NC——No connect, leave unconn ected
3NC——No connect, leave unconn ected
4VCC— +3.3V Positive power supply
5VEEP_CLK— GND High-speed clock VEE power supply (tie to VCC for power down)
6VEEP_CLK— GND High-speed clock VEE power supply (tie to VCC for power down)
7VEEP_CLK— GND High-speed clock VEE power supply (tie to VCC for power down)
8VCC— +3.3V Positive power supply

9 CLKO+ O HS High-speed clock output, true
10 CLKO- O HS High-speed clock ou tput, complement
11 VCC — +3.3V Positive power supply
12 VCC — +3.3V Positive power supply
13 NC ——No connect, leave unconnected
14 NC ——No connect, leave unconnected
15 VEE — GND Neg ative po wer supply
16 VEE — GND Neg ative po wer supply
17 VEE — GND Neg ative po wer supply
18 VCC — +3.3V Positive power supply
19 DO+ O HS High-speed data output, true
20 DO- O HS High-speed data output, complement
21 VCC — +3.3V Positive power supply
22 NC ——No connect, leave unconnected
23 VCC — +3.3V Positive power supply
24 VCC — +3.3V Positive power supply
25 VCC — +3.3V Positive power supply
26 VEE — GND Neg ative po wer supply
27 VEE — GND Neg ative po wer supply
28 VEE — GND Neg ative po wer supply
29 VEE — GND Neg ative po wer supply
30 VEE — GND Neg ative po wer supply
31 NC ——No connect, leave unconnected
32 NC ——No connect, leave unconnected
33 NC ——No connect, leave unconnected
34 NC ——No connect, leave unconnected

Preliminary Data Sheet

VSC8169

(1)
(1)
(1)

(1)
(1)

(1)

(1)
(1)
(1)
(1)

Page 12 G52230-0, Rev 3.6

© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012

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Internet: www.vitesse.com

01/02/01

VITESSE

SEMICONDUCTOR CORPORATION

Preliminary Data Sheet

VSC8169

Pin # Name I/O Level Description

35 NC ——No connect, leave unconnected
36 NC ——No connect, leave unconnected
37 NC ——No connect, leave unconnected
38 REF_FREQSEL I TTL Reference clock input select
39 VCC — +3.3V Positive power supply
40 VEE — GND Neg ative po wer supply
41
42 VEE — GND Neg ative po wer supply
43 VCC — +3.3V Positive power supply
44 RESET I TTL Reset to align FIFO Write and Read pointers
45 NC ——No connect, leave unconnected
46 NC ——No connect, leave unconnected
47 NC ——No connect, leave unconnected
48 NC ——No connect, leave unconnected
49 NC ——No connect, leave unconnected
50 VCC — +3.3V Positive power supply
51 VEE — GND Neg ative po wer supply
52 CLK16 O+ O LVPECL Low-speed cloc k ou tput, tr ue . A divi de -by-1 6 ve rsion of the PL L cloc k.

53 CLK16O- O LVPECL

54 VCC — +3.3V Positive power supply
55 CLKI+ I LVPECL Low-speed clock input for latching low-speed data, true
56 CLKI- I LVPECL Low-speed clock input for latching low-speed data, complement
57 VEE — GND Neg ative po wer supply
58 D0- I LVPECL Low-speed differential parallel data
59 D0+ I LVPECL Low-speed differential parallel data
60 VCC — +3.3V Positive power supply
61 D1- I LVPECL Low-speed differential parallel data
62 D1+ I LVPECL Low-speed differential parallel data
63 NC ——No connect, leave unconnected
64 VCC — +3.3V Positive power supply
65 NC ——No connect, leave unconnected
66 VCC — +3.3V Positive power supply
67 D2- I LVPECL Low-speed differential parallel data
68 D2+ I LVPECL Low-speed differential parallel data

FIFO_WARN

O TTL FIFO overflow warning

Low-speed clock output, complement. A divide-by-16 version of the
PLL clock.

OC-48 (FEC) 16:1 SONET/SDH

MUX with Clock Generator

(1)
(1)
(1)

(1)
(1)
(1)
(1)
(1)

(1)

(1)

G52230-0, Rev 3.6 Page 13
01/02/01

© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012

Tel: (800) VITESSE • FAX: [phone] • Email: [e-mail]

Internet: www.vitesse.com

VITESSE

SEMICONDUCTOR CORPORATION

OC-48 (FEC) 16:1 SONET/SD H

MUX with Clock Generator

Pin # Name I/O Level Description

69 VEE — GND Neg ative po wer supply
70 D3- I LVPECL Low-speed differential parallel data
71 D3+ I LVPECL Low-speed differential parallel data
72 VCC — +3.3V Positive power supply
73 D4- I LVPECL Low-speed differential parallel data
74 D4+ I LVPECL Low-speed differential parallel data
75 VCC — +3.3V Positive power supply
76 D5- I LVPECL Low-speed differential parallel data
77 D5+ I LVPECL Low-speed differential parallel data
78 VEE — GND Neg ative po wer supply
79 D6- I LVPECL Low-speed differential parallel data
80 D6+ I LVPECL Low-speed differential parallel data
81 VCC — +3.3V. Positive power supply
82 D7- I LVPECL Low-speed differential parallel data
83 D7+ I LVPECL Low-speed differential parallel data
84 VCC — +3.3V. Positive power supply
85 D8- I LVPECL Low-speed differential parallel data
86 D8+ I LVPECL Low-speed differential parallel data
87 VEE — GND Neg ative po wer supply
88 D9- I LVPECL Low-speed differential parallel data
89 D9+ I LVPECL Low-speed differential parallel data
90 VCC — +3.3V. Positive power supply
91 D10- I LVPECL Low-speed differential parallel data
92 D10+ I LVPECL Low-speed differential parallel data
93 VCC — +3.3V Positive power supply
94 D11- I LVPECL Low-speed differential parallel data
95 D11+ I LVPECL Low-speed differential parallel data
96 VEE — GND Neg ative po wer supply
97 D12- I LVPECL Low-speed differential parallel data
98 D12+ I LVPECL Low-speed differential parallel data
99 VCC — +3.3V Positive power supply

100 D13- I LVPECL Low-speed differential parallel data
101 D13+ I LVPECL Low-speed differential parallel data
102 VCC — +3.3V. Positive power supply
103 VCC — +3.3V Positive power supply

Preliminary Data Sheet

VSC8169

Page 14 G52230-0, Rev 3.6

© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012

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Internet: www.vitesse.com

01/02/01

VITESSE

SEMICONDUCTOR CORPORATION

Preliminary Data Sheet

OC-48 (FEC) 16:1 SONET/SDH

VSC8169

Pin # Name I/O Level Description

104 NC ——No connect, leave unconn ected
105 D14- I LVPECL Low-speed differential parallel data
106 D14+ I LVPECL Low-speed differential parallel data
107 VCC — +3.3V Positive power supply
108 D15- I LVPECL Low-speed differential parallel data
109 D15+ I LVPECL Low-speed differential parallel data
110 VEE — GND Negative power supply
111 NC ——No connect , leave unconnected
112 NC ——No connect, leave unconnected
113 NC ——No connect, leave unconnected
114 NC ——No connect, leave unconnected
115 NC ——No connect, leave unconnected
116 REFCLK+ I LVPECL Reference clock input, true
117 REFCLK- I LVPECL Reference clock input, complement
118 VCC — +3.3V Positive power supply
119 VEE — GND Negative power supply
120 REFCLKO+ O LVPECL Reference clock output, true
121 REFCLKO- O LVPECL Reference clock output, complement
122 VEE_ANA — GND Negative power supply pins for analog parts of CMU
123 VCC_ANA — +3.3V Positive power supply pins for analog parts of CMU
124 NC ——No connect, leave unconn ected
125 NC ——No connect, leave unconn ected
126 VEE — GND Negative power supply
127 VEE — GND Negative power supply
128 VCC — +3.3V. Positive power supply

(1)

(1)
(1)
(1)
(1)
(1)

(1)
(1)

MUX with Clock Generator

NOTE: (1) No connect (NC) pins must be left unconnected, or floating. Connecting any of these pins to either the positive or neg-

ative power supply rails may cause improper operation or failure of the device; or in extreme cases, cause permanent
damage to the device.

G52230-0, Rev 3.6 Page 15
01/02/01

© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012

Tel: (800) VITESSE • FAX: [phone] • Email: [e-mail]

Internet: www.vitesse.com

VITESSE

SEMICONDUCTOR CORPORATION

OC-48 (FEC) 16:1 SONET/SD H

MUX with Clock Generator

Package Information

PIN 128

PIN 1

RAD. 2.92 ± .50

EXPOSED
INTRUSION

0.127 MAX.

EXPOSED
HEATSINK

PIN 38

TOP VIEW

128-Pin PQFP Package Drawing

PIN 102

(2)

E

E

1

2.54 ± .50

D

1

D

PIN 64

Preliminary Data Sheet

VSC8169

Key mm Tolerance

A2.35 MAX
A1 0.25 MAX
A2 2.00 +.10

D 17.20 ±.20
D1 14.00 ±.10

E 23.20 ±.20
E1 20.00 ±.10

L.88+.15/-.10

e.50BASIC

b .22 ±.05
θ 0°-7°

R.30 TYP
R1 .20 TYP

A

2

Notes: 1) Drawing is not to scale

2) All dimensions in mm

3) Package represented is
also used for the 64,
80, & 100 PQFP packages.

Pin count drawn does

not reflect the 128 Package.

10° TYP .

A

A

1

10° TYP .

R

R1

θ

1

.25

A

θ

MAX.

0.17

L

e

b

STANDOFF

A

1

LEAD COPLANARITY

NOTES:

Package #: 101-322-5
Issue #: 2

Page 16 G52230-0, Rev 3.6

© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012

Tel: (800) VITESSE • FAX: [phone] • Email: [e-mail]

Internet: www.vitesse.com

01/02/01

VITESSE

SEMICONDUCTOR CORPORATION

Preliminary Data Sheet

VSC8169

OC-48 (FEC) 16:1 SONET/SDH

MUX with Clock Generator

Thermal Considerations

This package has been enhanced with a copper heat slug to provide a low thermal resistance path from the

die to the exposed surface of the heat spreader. The thermal resistance is shown in the Table 4.

T a ble 4: Thermal Resistance

Symbol Description

θ

JC

θ

CA

Thermal Resistance with Airflow

Thermal resistance from junction-to-case. 1.34
Thermal resistance from case-to-ambien t with no airflow, including conduc tion

through the leads.

Shown in the Table 5 is the thermal resistance with airflow. This thermal resistance value reflects all the
thermal paths including through the leads in an environment where the leads are exposed. The temperature dif­ference between the ambie nt airflow temper ature and the case temperature s hould be the worst cas e power of
the device multiplied by the thermal resistance.

°C/W

25.0

T a ble 5: Thermal Resistance with Airflow

Airflow θca (

100 lfpm 21
200 lfpm 18
400 lfpm 16
600 lfpm 14.5

Maximum Ambient Temperature without Heatsink

o

C/W)

The worst-case ambient temperature without use of a heatsink is given by the equation:

T

AMAX()TCMAX()

=

P–

MAX()

θ

CA

where:

θ

CA

Τ

A(MAX)

Τ

C(MAX)

P

(MAX)

Theta case-to-ambient at appropriate airflow
Ambient air temperature
Case temperature (85oC for VSC8169)
Power (1.7 W for VSC8169)

G52230-0, Rev 3.6 Page 17
01/02/01

© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012

Tel: (800) VITESSE • FAX: [phone] • Email: [e-mail]

Internet: www.vitesse.com

VITESSE

SEMICONDUCTOR CORPORATION

OC-48 (FEC) 16:1 SONET/SD H

MUX with Clock Generator

The results of this calculation are listed below:

Table 6: Maximum Ambient Air Temperature without Heatsink

Airflow Max Ambi ent Tempeature (

None 43
100 lfpm 49
200 lfpm 54
400 lfpm 58
600 lfpm 60

o

C)

Note that ambient air temperature varies throughout the system based on the positioning and magnitude of

heat sources and the direction of air flow.

Ordering Informatio n

The order number for this product is formed by a combination of the device number, and package type.

Preliminary Data Sheet

VSC8169

VSC8169

Device Type

OC-48 (FEC) 16:1 SONET/SDH
MUX with Clock Generator

otice

itesse Semiconductor Corporation (“Vitesse”) provides this document for informational purposes only. This document contains pre-production
nformation about Vitesse products in their c onc ept, development and /o r te sti ng phase. All information in th is doc ument, including descriptions of
eatures, functions, performance, technical specifications and availability, is subject to change without notice at any time. Nothing contained in this

ocument shall be c onstrue d as ex tendin g any wa rrant y or pro mise, expre ss or i mpl ied, t hat any Vitesse product wi ll be a vai lable as described or

ill be suitable for or will accomplish any particular task.

itesse products are not intended for use in life support appliances, devices or systems. Use of a Vitesse product in such applications without writ­en consent is pr ohibited.

xx

Package

QR: 128PQFP, 14x20mm Body

Page 18 G52230-0, Rev 3.6

© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012

Tel: (800) VITESSE • FAX: [phone] • Email: [e-mail]

Internet: www.vitesse.com

01/02/01