Datasheet VSC8115YA1, VSC8115YA, VSC8115YA2 Datasheet (VITESSE)

VITESSE

SEMICONDUCTOR CORPORATION

VSC8115

Target Specification

STS-12/STS-3 Multi Rate

Clock and Data Recovery Unit

Features

• Performs clock and data recovery for

622.08Mb/s (STS-12/OC-12/STM-4) or

155.52Mb/s (STS-3/OC-3/STM-1) NRZ data

• Meets Bellcore, ITU and ANSI Specifications
for Jitter Performance

• 19.44MHz reference frequency LVTTL Input

• Lock Detect output pin monitors data run length
and frequency drift from the reference clock

• Data is Retimed at the Output

• Active High Signal Detect LVPECL Input

• Low-jitter high speed outputs can be configured
as either LVPECL or low power LVDS

• Low power - 0.188 Watts Typical Power

• +3.3V Power Supply

• 20 Pin TSSOP Package

• Requires One External Capacitor

• PLL bypass operation facilitates the board
debug process

General Description

The VSC8115 functions as a clock and data recovery unit for SONET/SDH-based equipment to derive high
speed timing signals. The VSC8115 recovers the clock from the scrambled NRZ data operating at 622.08Mb/s
(STS-12/OC-12/STM-4) or 155.52Mb/s (STS-3/OC-3/STM-1). After the clock is recovered, the data is retimed
using an output flip-flop. Both recovered clock and retimed data outputs can be configured as LVDS or
LVPECL signals to facilitate a low-jitter and low power interface.

VSC8115 Block Diagram

STS12

BYPASS

DATAIN+/-

SD
LOCKREFN

REFCLK

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2

Divider

CAP+

Phase/

Freq

Detector

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Loop Filter

CAP-

VCO

0

1

2

2

LOCKDET
DATAOUT+/-

CLKOUT+/-±

VITESSE

VSC8115

SEMICONDUCTOR CORPORATION

STS-12/STS-3 Multi Rate
Clock and Data Recovery Unit

Functional Description

The VSC8115 contains an on-chip PLL consisting of a phase/frequency detector, a loop filter using one
external capacitor, a LC-based voltage-controlled oscillator (VCO), and a programmable frequency divider.
The phase/frequency detector compares the phase relationship between the VCO output and an external

19.44MHz LVTTL reference clock to make coarse adjustment to the VCO block so that its output is held within
+500ppm of the reference clock. The use of reference clock minimizes the PLL lock time during power up and
provides a stable output clock source in the absence of serial input data. The phase/frequency detector also com­pares the phase relationship between the VCO output and the serial data input to make fine adjustment to the
VCO block. The loop filter converts the phase detector output into a smooth DC voltage. This DC voltage is
used as the input to the VCO block whose output frequency is a function of the input voltage. A programmable
frequency divider down converts the VCO output signal and provides two modes of operation: 622.08Mb/s
mode if STS12 is HIGH, or 155.52Mb/s mode if STS12 is LOW.

Lock Detection

The VSC8115 features a lock detection for the PLL. The lock detect (LOCKDET) output goes HIGH to
indicate that the PLL is locked to the serial data inputs and that valid data and clock are present at the high speed
differential outputs. If LOCKDET output is LOW, then either the PLL is forced to lock to the REFCLK input or
the VCO has drifted away from the local reference clock by more than 500 ppm.

Target Specification

Signal Detection

The VSC8115 has a signal detect (SD) input and a lock-to-reference (LOCKREFN) input. The SD pin is a
LVPECL input, and the LOCKREFN pin is a LVTTL input. These two control pins are used to indicate a loss
of signal condition and they are connected inside the part as shown in Figure 1. If either one of these two inputs
goes LOW and BYPASS is LOW, the VSC8115 will enter the loss of signal (LOS) state, and it will hold the
DATAOUT+/- output at logic LOW state. During the LOS state, the VSC8115 also will hold the output clock
CLKOUT+/- to within +500ppm of the REFCLK. See Table 1.

Most of the optical module has a signal detect output. This signal detect output indicates that there is suffi­cient optical power, and it is typically active HIGH. If the signal detect output on the optical module is
LVPECL, it should be connected directly to the SD input on the VSC8115, and the LOCKREFN input needs to
be tied HIGH. If the signal detect output is LVTTL, it should be connected directly to the LOCKREFN input,
and the SD input needs to be tied HIGH.

The SD and LOCKREFN inputs also can be used for other applications when the users need to hold the
CLKOUT+/- output to within +500ppm of the reference clock and to force the DATAOUT+/- output to the
logic LOW state.

PLL Bypass Operation

The BYPASS pin is intended for use in production test, and it should be set at logic LOW in the normal
operation. If both BYPASS and MODE pins are set at logic HIGH, the VSC8115 will bypass the PLL and will
present an inverted version of the REFCLK to the clock output CLKOUT+/-. The REFCLK’s rising edge is
used to capture data at DATAIN+/- and transmit data at DATAOUT+/-. This bypass operation can be used to
facilitate the board debug process.

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VITESSE

SEMICONDUCTOR CORPORATION

VSC8115

Target Specification

Figure 1: Control Diagram for Signal Detection and PLL Bypass Operation

DATAIN+/-

REFCLK

STS12

BYPASS

LOCKREFN

SD

Table 1: Signal Detection and PLL Bypass Operation Control

2

PLL Clock
(on-chip)

0

1

LOS

(on-chip)

STS-12/STS-3 Multi Rate

Clock and Data Recovery Unit

2

DATAOUT+/-

2

CLKOUT+/-±

STS12 BYPASS LOCKREFN SD LOS DATAOUT CLKOUT

1 0 1 1 0 DATIN PLL Clock
1 0 1 0 1 LOW PLL Clock
1 0 0 1 1 LOW PLL Clock
1 0 0 0 1 LOW PLL Clock
1 1 X X 0 DATIN REFCLK
0 0 1 1 0 DATIN PLL Clock
0 0 1 0 1 LOW PLL Clock
0 0 0 1 1 LOW PLL Clock
0 0 0 0 1 LOW PLL Clock
0 1 X X 0 Not Allowed Not Allowed

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VITESSE

VSC8115

500

±

SEMICONDUCTOR CORPORATION

STS-12/STS-3 Multi Rate
Clock and Data Recovery Unit

AC Characteristics

Table 2: Performance Specifications

Parameters Min Typ Max Units Conditions

VCO Center Frequency

CRU’s Reference Clock Frequency

Tolerance

OC-12/STS12 Capture Range

Clock Output Duty Cycle

Acquisition Lock Time OC-12/STS-12

LVDS Output Rise & Fall Times

CLKOUT+/- Jitter Generation

OC-12/STS-12 Jitter Tolerance

— 622.08 — MHz

-250 — +250 ppm

— — ppm

45 — 55 % of UI

— — 16 µs

— — 600 ps

— 0.005 0.01 U.I.

0.5 — — U.I.

Target Specification

With respect to the fixed
reference frequency

20% Minimum transition
density

Valid REFCLK and device
already powered up

10% to 90%, with 100Ω & 5pF
capacitive equivalent load

No more than 14ps rms jitter on
DATAIN+/-

Sinusoidal input jitter of
DATAIN+/- from 250KHz to
5MHz

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SEMICONDUCTOR CORPORATION

VSC8115

Target Specification

STS-12/STS-3 Multi Rate

Clock and Data Recovery Unit

Jitter Tolerance

Jitter Tolerance is the ability of the Clock and Data Recovery Unit to track timing variation in the received
data stream. The Bellcore and ITU specifications allow the received optical data to contain jitter. The amount
that must be tolerated is a function of the frequency of the jitter. At high frequencies the specifications do not
require the VSC8115 to tolerate large amounts, whereas at low frequencies many unit intervals (bit times) of jit­ter have to be tolerated. Jitter tolerance is defined as the ratio of jitter on the output OC-N/STS-N signal to the
jitter applied on the input OC-N/STSN signal versus frequency. The VSC8115 is designed to tolerate this jitter
with margin over the specification limits, see Figure 2. The VSC8115 obtains and maintains lock based on the
data transition information. When there is no transition on the data stream, the recovered clock frequency will
be held to within +500ppm of the reference clock. The VSC8115 can maintain lock over 1000 bits of no switch­ing on data stream.

Figure 2: Input Jitter Tolerance Specification

JITTER(UI P-P)

150

15

1.5

0.15

Jitter Generation

Jitter generation is defined as the jitter of the serial clock and serial data outputs while rms jitter is presented
to the serial data inputs. Maximum jitter generation is 0.01 U.I. when rms jitter of less than 14ps (OC-12) or
56ps (OC-3) is presented to the serial data inputs.

Bellcore Requirement

24

10 30 300 25K 250K

2.4

1M

VSC8115 Typical
Jitter Tolerance

0.6

2.5M

JITTER FREQ(HZ)

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VITESSE

VSC8115

SEMICONDUCTOR CORPORATION

STS-12/STS-3 Multi Rate

Target Specification

Clock and Data Recovery Unit

Retimed Data and Clock Outputs AC Specification

As indicated in figure 3, it is recommended that the retimed data output be captured with the rising edge of
the clock output. Data valid time is larger for OC-3/STS-3 mode of operation than that of OC-12/STS-12. Data
valid time before the output clock’s rising edge is the available setup time (tsu) while the data valid time after
the clock’s rising edge is the available hold time (th).

Figure 3: Retimed Data and Clock Outputs Timing Diagram

DATAOUT+/-

CLKOUT+

t

su

t

h

Table 3: Retimed Data and Clock Outputs Timing

Parameters Description

t

su

t

h

High Speed Outputs

The high speed output buffers, DATAOUT+/- and CLKOUT+/-, can be terminated as either LVDS or
LVPECL outputs. If used as LVDS outputs, the transmission lines should be routed with 100-ohm differential
impedance, and they need to be terminated at the receive end with a 100-ohm resistor across the differential
pair. If used as LVPECL outputs, the transmission line should be 50-ohm terminated with 50-ohm pull down
resistors near the receiving end.

Minimum Available Setup Time 450 pS 2.0 nS

Minimum Available Hold Time 650 pS 3.0 nS

STS-12 Operation

(622.08MHz)

STS-3 Operation

(155.52MHz)

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VITESSE

SEMICONDUCTOR CORPORATION

VSC8115

Target Specification

STS-12/STS-3 Multi Rate

Clock and Data Recovery Unit

DC Characteristics

Table 4: LVPECL Single-ended Inputs and Outputs

Parameters Description Min Typ Max Units Conditions

V

IH

V

IL

I

IH

I

IL

V

OL

V

OH

Table 5: LVPECL Differential Inputs

Parameters Description Min Typ Max Units Conditions

V

IH

V

IL

∆V

IN

I

IH

I

IL

Input HIGH voltage

Input LOW voltage
Input HIGH current

Input LOW current
Output LOW voltage
Output HIGH voltage

Input HIGH
voltage

Input LOW
voltage

Differential
Input Voltage

Input HIGH
current

Input LOW
current

VDD - 1.125 — VDD - 0.5 V

VDD - 2.0 — VDD - 1.5 V

-0.5 — 10 µA

-0.5 — 10 µA

VDD - 2.0 — VDD - 1.8 V

VDD - 1.25 — VDD - 0.67 V

VDD - 1.75 — VDD - 0.45 V

VDD - 2.0 — VDD - 0.7 V

250 — — mV

-0.5 — 10 µA

-0.5 — 10 µA

Guaranteed Input HIGH
Voltage

Guaranteed Input LOW
Voltage

VIN = VDD - 0.5V
VIN = VDD - 2.0V
50Ω to (VDD - 2V)
50Ω to (VDD - 2V)

Guaranteed Input
HIGH Voltage

Guaranteed Input
LOW Voltage

—

∆V

∆V

= 0.5V

IN

= 0.5V

IN

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VSC8115

SEMICONDUCTOR CORPORATION

STS-12/STS-3 Multi Rate
Clock and Data Recovery Unit

Table 6: LVDS Differential Outputs

Parameters Description Min Typ Max Units Conditions

V

OCM

∆V

OUT

Table 7: LVPECL Differential Outputs

Parameters Description Min Typ Max Units Conditions

V

OCM

∆V

OUT

Table 8: LVTTL Inputs

Common Mode
voltage

Differential
Output Swing

Common Mode
voltage

Differential
Output Swing

Target Specification

1.0 1.35 1.7 V

350 500 750 mV

1.12 - 2.0 V

400 - 800 mV

100Ω PAD to
PADN

100Ω PAD to
PADN

50Ω to (VDD - 2V)

50Ω to (VDD - 2V)

Parameters Description Min Typ Max Units Conditions

V

IH

V

IL

I

IH

I

IL

Input HIGH voltage
Input LOW voltage
Input HIGH current
Input LOW current

2.0 — VDD V
0 — 0.8 V

-50 --- 50 µA

-50 --- 50 µA

—
—
VIN = 2.7V, VDD=MAX
VIN = 0.5V, VDD=MAX

Power Dissipation

Table 9: Power Supply Currents

Parameter Description (Typ) (Max) Units

I

DD

P

D

Power supply current from V
Power dissipation 188.1 277 mW

DD

57 80 mA

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SEMICONDUCTOR CORPORATION

VSC8115

5

±

Target Specification

STS-12/STS-3 Multi Rate

Clock and Data Recovery Unit

Absolute Maximum Ratings

Power Supply Voltage (VDD) Potential to GND.................................................................................-0.5V to +4V

DC Input Voltage (LVPECL Inputs)..................................................................................... -0.5V to VDD + 0.5V

DC Input Voltage (LVTTL Inputs)....................................................................................... -0.5V to VDD + 0.5V

Output Current (LVDS or LVPECL Outputs).......................................................................................... +/-50mA

Case Temperature Under Bias.........................................................................................................-55o to +125oC

Storage Temperature ....................................................................................................................-65oC to +150oC

Maximum Input ESD (Human Body Model)

High Speed Outputs (pins 11, 12, 13, & 14) .................................................................................... 500V

All Other Pins ................................................................................................................................. 1500V

Note: Caution: Stresses listed under “Absolute Maximum Ratings” may be applied to devices one at a time without causing

permanent damage. Functionality at or exceeding the values listed is not implied. Exposure to these values for extended
periods may affect device reliability.

(1)

Recommended Operating Conditions

Power Supply Voltage (VDD)................................................................................................................+3.3V%

Industrial Operating Ambient Temperature Range under Bias ......................................................... -40o to 85oC

Commercial Operating Ambient Temperature Range under Bias ....................................................... 0o to 70oC

Package Pin Descriptions

Figure 4: Pin Diagram

VDDA

DATAIN+

DATAIN-

VSSA

LOCKDET

STS12

REFCLK

LOCKREFN

VSS

VDD

1
2
3
4
5
6
7
8
9
10

20
19
18
17
16
15
14
13
12
11

VDDA
VSSA
CAP+
CAP­BYPASS
SD
DATAOUT+
DATAOUT­CLKOUT+
CLKOUT-

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VSC8115

SEMICONDUCTOR CORPORATION

STS-12/STS-3 Multi Rate

Target Specification

Clock and Data Recovery Unit

Table 10: Pin Identification

Signal I/O Level Pin Description

DATAIN+/- I LVPECL

DATAOUT+/- O LVDS/LVPECL

CLKOUT+/- O LVDS/LVPECL

STS12 I LVTTL

LOCKREFN I LVTTL

SD I LVPECL

REFCLK I LVTTL

LOCKDET O LVPECL

BYPASS I LVTTL Used for production test. Set to VSS for normal operation.

CAP+/CAP- I Analog

VDD +3.3V

VSS GND Ground pin for low speed I/O’s and on-chip digital CMOS blocks
VDDA +3.3V +3.3V Power Supply for high speed I/O’s and on-chip PLL blocks.
VSSA GND Ground pins for high speed I/O’s and on-chip PLL blocks.

Receive data in. The high speed output clock (CLKOUT+/-) is
recovered from this high speed differential input data.

High speed differential data out. This is the retimed version of the
receive data input (DATAIN+/-). Can be configured as either LVDS
or LVPECL signal.

High speed differential clock out This clock is recovered from the
receive data input (DATAIN+/-). Can be configured as either LVDS
or LVPECL signal.

STS-12 or STS-3 mode selection. Set HIGH to select the STS-12
operation. Set LOW to select the STS-3 operation.

Lock to REFCLK input. When set LOW, it holds the CLKOUT+/­output to within +500ppm of the REFCLK input, and it forces the
DATAOUT+/- output to the LOW state.

Signal Detect. SD should be connected to the SD output on the
optical module. SD is active HIGH. When SD is set HIGH, it means
that there is sufficient optical power. When SD is set LOW to
indicate loss of signal condition, the CLKOUT+/- output signal will
be held to within +500ppm of the REFCLK input; in additions, the
DATAOUT+/- will be held in the LOW state.

19.44 MHz local reference clock input for the CRU. REFCLK is used
for the PLL phase adjustment during power up, and it also serves as a
stable clock source in the absence of serial input data.

Active HIGH to indicate that PLL is locked to serial data input, and
valid clock and data are present at the serial outputs (DATAOUT+/­and CLKOUT+/-). The LOCKDET will go inactive under the
following conditions:
(1). If SD is set LOW.
(2). If LOCKREFN is set LOW.
(3). If the VCO has drifted away from the local reference
clock REFCLK by more than 500 ppm.

External loop filter pins. The loop filter capacitor should be
connected to these pins. The capacitor value should be 1.0uF +10%
tolerance.

+3.3V Power Supply for low speed I/O’s and on-chip digital CMOS
blocks.

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VSC8115

Target Specification

Package Information

STS-12/STS-3 Multi Rate

Clock and Data Recovery Unit

TSSOP Package Drawings

Key Min Nom Max

A − − 1.10

A1 0.05 − 0.15

A2 0.85 0.90 0.95
aaa 0.076

b 0.19 − 0.30

b1 0.19 0.22 0.25

bbb 0.10

c 0.09 − 0.20

c1 0.09 0.127 0.16

E1 4.30 4.40 4.50

e 0.65 BSC
E 6.40 BSC
L 0.50 0.60 0.70

θ 0° − 8°

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VITESSE

VSC8115

SEMICONDUCTOR CORPORATION

STS-12/STS-3 Multi Rate
Clock and Data Recovery Unit

Package Thermal Characteristics

The VSC8115 is packaged in a Thin Shrink Small Outline Package (TSSOP). This package conforms to
JEDEC package outline standards. It has hi-conductivity copper lead frames and a very low-stress mold com­pound. The junction to case thermal resistance is 80oC/W for multi-layer PCB applications and 126oC/W for
single-layer PCB applications. The air flow versus thermal resistance relationship for multi-layer PCB applica­tions is shown in Table 11.

Table 11: Theta Case to Ambient versus Air Velocity

Target Specification

Case to Air

Air Velocity

(LFPM)

0 55.0 15.4 to 59.6 15.4 to 87.6 -55.4 to 69.6
100 52.0 14.6 to 60.4 14.6 to 88.4 -54.6 to 70.4
200 49.0 13.7 to 61.3 13.7 to 89.3 -53.7 to 71.3
400 46.0 12.9 to 62.1 12.9 to 90.1 -52.9 to 72.1

Thermal

Resistance

(oC/W)

YA YA1 YA2

(0oC to 75oC ) Tcase (0oC to 103oC ) Tcase (-40oC to 85oC ) Tcase

Ta (Ambient Temperature) Range (oC)

Ordering Information

The order number for this product are:

Part Number Device Type
VSC8115YA: STS-12/STS-3 Multi-Rate Clock and Data Recovery Unit in a 20 Pin TSSOP

Commercial Temperature, 0°C ambient to 70°C case

VSC8115YA1 STS-12/STS-3 Multi-Rate Clock and Data Recovery Unit in a 20 Pin TSSOP

Extended Temperature, 0°C ambient to 110°C case

VSC8115YA2 STS-12/STS-3 Multi-Rate Clock and Data Recovery Unit in a 20 Pin TSSOP

Industrial Temperature, -40°C ambient to 85°C case

Notice

This document contains information about a proposed product during its design phase of development and
is subject to change without notice at any time. All features and specification are design goals only. Please con­tact Vitesse Semiconductor to obtain the latest product status and most recent versions of this specification.

Warning

Vitesse Semiconductor Corporation’s product are not intended for use in life support appliances, devices or
systems. Use of a Vitesse product in such applications without the written consent is prohibited.

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