Datasheet VSC8114QB1, VSC8114QB2, VSC8114QB Datasheet (VITESSE)

VITESSE

V

SEMICONDUCTOR CORPORATION

Data Sheet

SC8114

ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux

with Integrated Clock Generation and Clock Recovery

Features

• Operates at STS-12/STM-4 (622.08Mb/s)

Data Rate

• Compatible with Industry ATM UNI Devices

• On Chip Clock Generation of the 622.08MHz
High Speed Clock (Mux)

• On Chip Clock Recovery of the 622.08MHz
High Speed Clock (Demux)

• 8-Bit Parallel TTL Interface with Parity Error
Detection and Generation

• SONET/SDH Frame Recovery

• Loss of Signal (LOS) Input & LOS Detection

• +3.3V/5V Programmable PECL Serial Interface

• Provides Equipment, Facilities and Split Loop­back Modes as well as Loop Timing Mode

• Provide PECL Reference Clock Inputs

• Meets Bellcore, ITU and ANSI Specifications
for Jitter Performance

• Low Power - 0.9Watts Typical

• 100 PQFP Package

General Description

The VSC8114 is an ATM/SONET/SDH compatible transceiver integrating an on-chip Clock Multiplication
Unit (PLL) for high speed clock generation as well as a Clock and data Recovery Unit (CRU) with 8-bit serial­to-parallel and parallel-to-serial data conversion. The PLL clock is used for serialization in the transmit direc­tion (Mux). The recovered clock is used for deserialization in the receive direction (Demux). The demultiplexer
contains SONET/SDH frame detection and recovery. In addition, the device provides both facility and equip­ment loopback modes and a loop time mode. The part is packaged in a 100PQFP with an integrated heat
spreader for optimum thermal performance and reduced cost. The VSC8114 provides an integrated solution for
ATM physical layers and SONET/SDH systems applications.

Functional Description

The VSC8114 is designed to provide a SONET/SDH compliant interface between the high spee d optical
networks and the lower speed User Network Interface devices such as the PM5355 S/UNI-622. The VSC8114
conv ert s 8 bi t pa ra llel d a ta at 7 7.76 Mb/s t o a serial bit stream at 62 2.08 Mb/ s. T he device also provides a Facilit y
Loopback function which loops the received high speed data and clock (optionally recovered on-chip) directly
to the high speed transmit outputs. A Clock Multiplier Unit (CMU) is integrated into the transmit circuit to gen­erate the high speed clock for the serial output data stream from input reference f requencies of 19.44 or 77.76
MHz. The CMU can be bypassed with the received/recovered clock in loop timing mode, thus synchronizing
the entire part to a single clock. The block diagram on page 2 sho ws the maj or function al blocks associ ated with
the VSC8114.

The receive se ction pro vid es the serial-to -parallel co n v ersi on, converting 62 2Mb/s bit st ream to an 8 bi t par­allel output at 77.76MHz. A Clock Reco v ery Unit (CRU) is integrated int o th e recei v e ci rcuit to reco ver t he hi gh
speed clock from the recei ved serial data stream. Th e receive section provides an Equipment Loopback funct i on
which will loop the low speed transmit data and clock back through the receive section to the 8 bit parallel out-

puts. The VSC8114 also provides the option of selecting between either its internal CRU’s clock and data sig­nals, or optics containing a CRU clock and data sign al s. The receive section al so co nt ains a SONE T/SDH frame

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4

SEMICONDUCTOR CORPORATION

ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux
with Integrated Clock Generation and Clock Recovery

Data Sheet

VSC811

detector circuit which is used to provide frame pluses during the A1, A2 boundary in the serial to parallel con­verter. This only occurs when OOF is high. Both internal and external LOS functions are supported.

The VSC8114 provides the parity error detection and generation for the 8 bit data bus. On the receive side,
the parity of the 8 bit data outputs is generated. On the transmit side, the parity of the 8 bit data input is calcu­lated and compared with the received parity input.

VSC8114 Block Diagram

EQULOOP

RESET

TXDATAOUT+/-

FACLOOP

DQ

DQ

FRAMER

0
1

0
1

1
0

1
0

1:8

DEMUX

Divide-by-8

Parity Chk

8:1

MUX

Divide-by-8

Parity/
REG

REG

8

8

OOF
FP

RXOUT[7:0]
RXOUTP

RXLSCKOUT
TXPERR

TXINP

TXIN[7:0]

TXLSCKIN
TXLSCKOUT

LOOPTIM0

REFCLKP+/-

REFSEL

LOSPECL
LOSTTL

LOSDETEN_

CRUREFCLK
CRUREFSEL

RXDATAIN+/-

CRUEQLP

RXCLKIN+/-

DSBLCRU

01

10

1
0

REC-DATA

CRU

REC-CLK

losdet

1
0

0
1

CMU

0
1

Transmit Section

Byte-wide data is presented to TXIN[7:0] and is clocked into the part on the rising edge of TXLSC KIN.
See Figure 1. The data is th en seria lized (M SB le ading) a nd pr esente d to the TXDATAOUT+/- pins. Th e seria l
output stream is synchronized to the CMU generated clock whic h is a phase locked and frequency scaled ver-

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Data Sheet

SC8114

sion of the input referen ce clock. Ex ternal control in put REFSEL se lects the mult iply ratio of th e CMU (see
table 11). A divide-by-8 version of the CMU clock (TXLSCKOUT) should be used to synchronize the transmit
interface of the UNI device to the transmit input registers on the VSC8114 (see Application Notes, p. 20).

Figure 1: Data and Clock Transmit Block Diagram

TXDATAOUT+

TXDATAOUT-

REFCLK

Receive Section

High speed Non-Return to Zero (NRZ) serial data at 622M b/s are received by the RXDATAIN inputs. The
CRU recovers the high speed clock from the seria l data i n put. T h e seri al d ata is co nverted to byte-wid e pa rall e l
data and presented on RXOUT[7:0] pins. A divide-by-8 version of the high-speed clock (RXLSCKOUT)
should be used to synchronize the byte-serial RXOUT[7:0] data with the receive portion of the UNI device. The
on-chip CRU is by-passed by setting the DSBLCRU input high. In this mode, the serial input data and corre­sponding clock are received by the RXDATAIN and RXCLKIN inputs respectively. RXDATAIN is clocked in
on the rising edge of RXCLKIN+. See Figure 2.

The receive section also includes frame detection a nd recovery circuitry which detec ts the SONET/SDH
frame, aligns the received serial data on byte boundaries, and initiates a frame pulse on FP coincident with the
byte aligned data. The frame recovery is initiated when OOF is held high which must occur at lea s t 4 byte clock
cycles before the A1A2 boundary. The OOF input control is a level-sensitive signal, and th e VSC8114 will con­tinually perform frame detection and recovery as long as this pin is held high even if 1 or more frames has been
detected. Frame detection and recovery occurs when a series of three A1 bytes followed by three A2 bytes has
been detected. The paralle l outp ut data on R XOUT[7:0] wil l be b yt e alig ned startin g on the thi rd A2 b yte. Wh en
a frame is detected, a single byte clock pe riod long pulse is g enerated o n FP which i s synchronize d with the
byte-aligned third A2 byte on RXOUT[7:0]. The frame detector sends an FP pulse only if OOF is high.

ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux

with Integrated Clock Generation and Clock Recovery

VSC8114 PM5355

DQDQ

Divide-by-8CMU

TXIN[7:0]

TXLSCKIN

TXLSCKOUT

DQ

Loss of Signal

The VSC8114 features Loss of Signal (LOS) detection. Loss of Signal is detected if the incoming serial
data stream has no transition continuously for more than 128 bits. During an LOS condition, the VSC 8114
forces the receive data low which is an indication for an y do wnstre am equipment that an optical interfac e fail ure
has occurred. The receive section continues to be clocked by the CRU as it is now locked to the CRUREFCLK
unless DSBLCRU is active, in which case it will be clocked by the CMU. This LOS condition will be removed
when the part detects more than 16 transitions in a 128 bit time window. This LOS detection feature can be dis­abled by applying a high level to the LOSDETEN_ input. The VSC8114 also has a TTL input LOSTTL and a

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ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux
with Integrated Clock Generation and Clock Recovery

Data Sheet

VSC811

PECL input LOSPECL to force the part into a Loss of Signal stat e. Most optics have a PECL outpu t usually

called “SD” or “FLAG” indicating the presence or lack of optical power. Depending on the optics manufacturer
this signal is either active high or active low. The LOSTTL and LOSPECL inputs are XNOR’d to generate an
internal LOS control signal. See Figure 2. The optics “SD” output should be connect ed to LOSPECL. The
LOSTTL input should be tied to low if the optics “SD” is active high. If it’s active low tie LOSTTL to a high.
The inverse is true if the optics use “FLAG” for loss of signa l

Figure 2: Data and Clock Receive Block Diagram

PM5355

LOSPECL

LOSTTL

LOSDETEN_

DSBLCRU

RXDATAIN+/-

RXCLKIN+/-

Losdet

CRU

1
0

0
1

VSC8114

0
1

DQ

Divide-by-8

DQ

DQ

RXOUT[7:0]

FP

RXLSCKOUT

DQ

DQ

CMU

Facility Loopback

The Facility Loopback function is controlled by the FACLOOP signal. When the FACLOOP signal is set
high, the Facility Loopback mode is activated and the high speed serial receive data (RXDATAIN) is presented
to the high speed transmit output (TXDATAOUT). See Figure 3. In Facility Loopback mode the high speed
receive data (RXDATAIN) is also converted to parallel data and presented to the low speed receive data output
pins (RXOUT[7:0]). The receive clock (RXCLKIN) is also divided down and presented to the low speed clock
output (RXLSCKOUT).

Figure 3: Facility Loopback Data Path

D

RXDATAIN

RXCLKIN

TXDATAOUT

Recovered

Clock

CRU

Q

0
1

Q

1

D

0

1
0

1:8
Serial to
Parallel

8:1
Parallel to
Serial

PLL

D

Q

Q

D

RXOUT[7:0]

TXIN[7:0]

FACLOOP

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Data Sheet

SC8114

ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux

with Integrated Clock Generation and Clock Recovery

Equipment Loopback

The Equipment Loopback function is controlled by the EQULOOP signal. When the EQULOOP signal is
set high, the Equipment Loopback mode is activated and the high speed transmit data generated from the paral­lel to serial conversion of the low speed data (TXIN[7:0]) is selected and converted back to parallel data in the
receiver section and presented to the low speed parallel o utputs (RXOUT[7:0]). S ee Figure 4. The inte rnally
generated 622MHz clock is used to generate the low speed receive cl ock output (RXLSCKOUT). In Equipment
Loopback mode the transmit data (TXIN[7:0]) is serialized and presented to the high spee d output
(TXDATAOUT) using the clock generated by the on-chip clock multiplier unit.

CRU Equipment Loopback

Exactly the same as equipment loopback, the point where the transmit data is looped back is moved all the
way back to the high speed I/O. When the CRUEQLP signal is set high, transmit data is looped back to the

CRU, replacing RXDATAIN±

Figure 4: Equipment Loopback Data Path

D

RXDATAIN

EQULOOP

Q

0
1

1:8
Serial to
Parallel

÷

8

D

Q

RXOUT[7:0]

RXLSCKOUT

TXDATAOUT

Q

D

8:1
Parallel to
Serial

PLL ÷

Q

D

8

TXIN[7:0]
TXLSCKIN

TXLSCKOUT

Split Loopback

Equipment and facility loopback modes can be enabled simultaneously. In this case, high-speed serial data
received (RXDATAIN) is mux’d through to the high-speed serial outpu ts (TXD ATA OUT). The lo w-spee d trans­mit byte-wide bus (TXIN[7:0]) and (TXLSCKIN) is mux’d into the low-speed byte-wide receive output bus
(RXOUT[7:0]) and (RXLSCKOUT). See Figure 5.

Figure 5: Split Loopback Datapath

D

RXDATAIN

RXCLKIN

DSBLCRU

TXDATAOUT

Recovered

Clock

CRU

Q

0
1

Q

D

1:8
Serial to
Parallel

8:1
Parallel to
Serial

D

Q

Q

D

RXOUT[7:0]

RXLSCKOUT

TXIN[[7:0]

TXLSCKIN

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ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux
with Integrated Clock Generation and Clock Recovery

Loop Timing

LOOPTIM0 mode bypasses the CMU when the LOOPTIM0 input is asserted high. In this mode the CMU
is bypassed by using the receive clock (RXCLKIN), and the entire part is synchronously clocked from a single
external source.

Parity

An even parity in put (TXINP) is pr o v id ed fo r the b yt e- wid e transmi t data. Thi s inpu t, along wit h b yt e- wi de
data, is clock ed int o th e VSC 8114 on the r ising edge of TXLSCKIN. P a rit y i s cal cul at ed on t he c lo ck e d in byte­wide data and compared to the clocked in parity input. A parity error is reported on the next TXLSCKIN rising
edge on TXPERR. For no parity errors to result, TXINP must be logic 1 when on an odd number of bits in the
TXIN[7:0] are logic 1; otherwise, it must be logic 0.

Even parity is calculated and clocked out along with byte-wide receive data (RXOUT[7:0]) on RXOUTP.
RXOUTP is a logic 1 when an odd number of bits on RXOUT[7:0] are logic 1; ohterwise, it is logic 0.

Clock Synthesis

The VSC8114 uses an integrated phase-locked loop (PLL) for c lock synthesis of the 622MHz hig h speed
clock used for serialization in the transmitter section. The PLL is comprised of a phase-frequency detector
(PFD), an integrating operation amplifier and a voltage controlled oscillator (VCO) configured in classic feed­back system. The PFD compares the selected divided down version of the 622MHz VCO (select pin REFSEL
selects divide-by ratios of 8 and 32, see Table 11) and the reference clock. The integrator provides a transfer
function between input phase error and ou tput voltage control. The V CO portion of the PLL is a voltage con­trolled ring-oscillator with a center frequency of 622MHz.

The reactive elements of the integrator are located off-chip and are connected to the feedback loop of the
amplifier through the CP1, CP2, CN1 and CN2 p ins. The configuration of thes e external surface moun ted
capacitors is shown in Figure 6. Table 1 shows the recommended external capacitor values for the configurable
reference frequencies.

Good analog design practices should be applied to the board design for these external components. Tightly
controlled analog ground and power planes should be provided for the PLL portion of the circuitry. The dedi­cated PLL power (VDDANA) and ground (VSSANA) pins should have quiet supply planes to minimize jitter
generation within the clock synthesis unit. This is accomplished by either using a ferrite bead or a C-L-C choke
(π filter) on the (VDDANA) power pins. Note: Vitesse recommends a (π filter) C-L-C choke over using a ferrite
bead. All ground planes should be tied together using multiple vias.

Data Sheet

VSC811

Reference Clocks

Note that the CMU uses a differential PECL reference clock input to achieve optimum jitter performance.

The CRU has the option of either using the CMU’s reference clock or its own independent reference clock
CRUREFCLK. This is accomplished with the control signal CRUREFSEL. The CRUREFCLK should be used
if the system is being operate d in ei t her a r e ge ner at io n or loo p ti mi ng mode . In either of t hese modes the qu ali t y
of the CR UREFCLK is not a concer n, t hus it can be dr i v en b y a si mple 7 7.76MHz cryst al, t he k ey is it s inde pen­dence from the CMU’s reference clock.

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Data Sheet

SC8114

Figure 6: External Integrator Capacitor

Table 1: Recommended External Capacitor Values

Reference

Frequency

[MHz]

19.44 32 0.1 0.1 X7R 0603/0803 +/-10%

77.76 8 0.1 0.1 X7R 0603/0803 +/-10%

Divide Ratio CP CN Type Size Tol.

ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux

with Integrated Clock Generation and Clock Recovery

CP = 0.1 µF

CP1

+

-

CN1 CN2

CP2

CN = 0.1 µF

Clock Recovery

The fully monolithic Clock Recovery Unit (CRU) consists of a Phase Detector, a Frequency Detector, a
Loop Filter and a Voltage Controlled Oscillator (VCO). The phase detector compares the phase information of
the incoming data with the recovered clock. The frequency detector compares the frequency component of the
data input with the recovered clock to provide the pull in energy during lock acquisition. The Loop Filter inte­grates the phase information from the phase and frequency detectors and provides the control voltage to the
VCO.

Jitter Tolerance

Jitter Tolerance is the ability of the Clock Recovery Unit to track timing variations in the received data
stream. The Bellcore and ITU specifications allow the received optical data to co ntain jitter. The amount that
must be tolerated is a fun ction of the fr equ ency of the jitter. The CRU is designed to to lerat e jitter with ma rgin
over the specification limits, see F igure 7. T he CRU obtains and main tains lock based on the data transi tion
information. When there is no transition on the data stream, the recovered clock frequency can drift. The
VSC8114 can maintain lock over 100 bits of no switching on the data stream.

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ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux
with Integrated Clock Generation and Clock Recovery

Figure 7: Jitter Tolerance

JITTER(UI P-P)

150

15

1.5

0.15

Bellcore Requirement

60

Data Sheet

VSC811

VSC8114 Guaranteed
Jitter Tolerance

6

0.6

10 30 300 25K 250K

Data Latency

The VSC8114 contains several operating modes, each of which exercise different logic paths through the
part. Table 2 bounds the data latency through each path with an associated clock signal.

Table 2: Data Latency

Circuit Mode Description

Receive MSB at RXDATAIN to data on RXOUT [7:0] RXCLKIN 25-35

Facilities

Loopback

MSB at RXDATAIN to MSB at TXDATAOUT RXCLKIN 2-4

2.5M

JITTER FREQ(HZ)

Clock

Reference

Range of Clock

cycles

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Data Sheet

SC8114

ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux

with Integrated Clock Generation and Clock Recovery

AC Timing Characteristics

Figure 8: Receive High Speed Data Input Timing Diagram

T

RXCLK

RXCLKIN+

RXCLKIN-

RXDATAIN+

RXDATAIN-

Table 3: Receive High Speed Data Input Timing T ab le

Parameter Description Min Typ Max Units

T

RXCLK

T

RXSU

T

RXH

Receive clock period - 1.608 - ns
Serial data setup time with respect to RXCLKIN 250 - - ps
Serial data hold time with respect to RXCLKIN 250 - - ps

T

RXSU

T

RXH

Figure 9: Receive Data Output Timing Diagram

T

RXCLKIN+

RXCLKIN-

RXLSCKOUT

RXOUT [7:0]

RXOUTP

FP

RXCLKIN

T

RXLSCK

A1 A2 A2 A2 A2

T

RXVALID

Table 4: Receive Data Output Timing Table

Parameter Description Min Typ Max Units

T

RXCLKIN

T

RXLSCK

T

RXVALID

T

PW

Receive clock period - 1.608 - ns
Receive data output byte clock period - 12 .86 - ns
Time data on RXOUT [7:0], FP, and RXOUTP is valid

before and after the rising edge of RXLSCKOUT
Pulse width of fram e detection pulse FP - 12.86 - ns

4.0 - - ns

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ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux
with Integrated Clock Generation and Clock Recovery

Figure 10: Transmit High Speed Data Timing Diagram

T

TXDAT

TXDATAOUT+

TXDATAOUT-

Table 5: Transmit High Speed Data Timing Table

Parameter Description Min Typ Max Units

T

TXDAT

Transmit data width - 1.608 - ns

Figure 11: Transmit Data Timing Diagram

T

PROP

Data Sheet

VSC811

TXLSCKOUT

T

CLKIN

TXLSCKIN

T

INH

T

ERR

TXIN [7:0]

TXINP

TXPERR

T

INSU

Table 6: Transmit Data Input Timing Table

Parameter Description Min Typ Max Units

T

CLKIN

T

INSU

T

INH

T

PROP

T

ERR

Note: Duty cycle for TXLSCKOUT is 50% +/- 10% worst case

Transmit data input byte clock period - 12.86 - ns
Transmit data and parity setup time with respect to

TXLSCKIN
Transmit data and parity hold time with respect to

TXLSCKIN
Maximum allowable pro pagation delay for connecting

TXLSCKOUT to TXLSCKIN
Propagation delay from TXLSCKI N to TXPER R 3.2 - 9.0 ns

1.0 - - ns

1.0 - - ns

--3.5ns

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Data Sheet

SC8114

ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux

with Integrated Clock Generation and Clock Recovery

AC Characteristics

Table 7: PECL and TTL Outputs

Parameter Description Min Typ Max Units Conditions

T

R,TTL

T

F,TTL

T

R,PECL

T

F,PECL

TTL Output Rise Time
TTL Output Fall Time
PECL Output Rise Time
PECL Output Fall Time

—2—ns
—1.5—ns
—350— ps
—350— ps

10-90%
10-90%
20-80%
20-80%

DC Characteristics

Table 8: PECL and TTL Inputs and Outputs

Parameter Descr ipt ion Min Typ Max Units Conditions

∆V

∆V

V

V

V

OCM

OUT75

OUT50

V

V

∆V

V

V

V

V

OH

OL

IH

IL

IN

ICM

OH

OL

IH

Output HIGH
voltage (PECL)

Output LOW
voltage (PECL)

O/P Common
Mode Range
(PECL)

Differential Output
Voltage (PECL)

Differential Output
Voltage (PECL)

Input HIGH voltage
(PECL)

Input LOW voltage
(PECL)

Differential Input
Voltage (PECL)

I/P Common Mode
Range (PECL)

Output HIGH
voltage (TTL)

Output LOW
voltage (TTL)

Input HIGH voltage
(TTL)

——V

0.7 —— V

1.1 —V

600 —1300mV

600 —1300mV

V

– 0.9V — V

DDP

0—V

400 — 1600 mV

1.5 – ∆V

/2 — V

IN

2.4 —— V

—— 0.5 V

2.0 — 5.5 V

DDP

– 0.9V V

DDP

– 1.3V V

DDP

– 0.3V V

DDP

– 1.72V V

DDP

– 1.0 – ∆V

IN

/2 V

—

—

—

75Ω to V

50Ω to V

For single ended

For single ended

—

—

IOH = -1.0 mA

IOL = +1.0 mA

—

DDP

DDP

– 2.0V

– 2.0V

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ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux
with Integrated Clock Generation and Clock Recovery

Parameter Description Min Typ Max Units Conditions

V

IL

I

IH

I

IL

Input LOW voltage
(TTL)

Input HIGH current
(TTL)

Input LOW current
(TTL)

0 —0.8 V

—50 500 µA

—— -500 µA

—

2.0V< VIN < 5.5V,

Typical@2.4V

-0.5V< VIN <0.8V

Data Sheet

VSC811

Power Dissipation

Table 9: Power Supply Currents

Parameter Description Max Units

I

DD

I

DDP

P

D

Absolute Maximum Ratings

Power Supply Voltage (VDD) Potential to GND.................................................................................-0.5V to +4V

PECL I/O Supply Voltage (V

DC Input Voltage (PECL inputs).......................................................................................... -0.5V to V

DC Input Voltage (TTL inputs).........................................................................................................-0.5V to 5.5V

DC Output Voltage (TTL Outputs)........................................................................................ -0.5V to V

Output Current (TTL Outputs)................................................................................................................. +/-50mA

Output Current (PECL Outputs)................................................................................................................+/-50mA

Case Temperature Under Bias.........................................................................................................-55

Storage Temperature.....................................................................................................................-65

Maximum Input ESD (Human Body Model).............................................................................................. 1500 V

Power supply current from V
Power supply current from PECL I/O Supply V
Power dissipation (Worst Case) (I

DD

DD + IDDP

) x 3.45V = 1.51 1.51 W

(1)

) Potential to GND..........................................................................-0.5V to +6V

DDP

410 mA

(output unloaded) 30 mA

DDP

o

DDP

DD

o

to +125oC

C to +150oC

+0.5V

+ 0.5V

Note: Caution: Stresses listed under “Absolute Maximum Ratings” may be applied to devices one at a time without causing

permanent damage. Functionality at or exceeding the values listed is not implied. Exposure to these values for extended
periods may affect device reliability.

Recommended Operating Conditions

Power Supply Voltage (VDD).................................................................................................................+3.3V %

PECL I/O Supply Voltage (V

Commercial Operating Temperature Range..................................................................... 0

Extended Operating Temperature Range.........................................................................0

Industrial Operating Temperature Range ......................................................................-40

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).......................................................................................... +3.3V or +5.0V %

DDP

VITESSE SEMICONDUCTOR CORPORATION

o

ambient to 70oC case

o

ambient to 115oC case

o

ambient to 85oC case

G52185-0, Rev 4.0

5±
5±

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V

SEMICONDUCTOR CORPORATION

Data Sheet

SC8114

ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux

with Integrated Clock Generation and Clock Recovery

Clock Recovery Unit

Table 10: Reference Frequency for the CRU

CRUREFSEL

1X77.76 ± 500ppm 622.08
0 Uses CMU’s Reference Clock (See Table 11 below)

REFSEL

CRUREFCLK

Frequency

[MHz]

Clock Multiplier Unit

Table 11: Reference Frequency Selection and Output Frequency Control

Reference

REFSEL

1 19.44 622.08
0 77.76 622.08

Frequency

[MHz]

Output

Frequency

[MHz]

Output

Frequency

[MHz]

Table 12: Clock Multiplier Unit Performance

Name Description Min Typ Max Units

RCd Reference clock duty cycle 40 60 %

RCj Reference clock jitter (RMS) @ 77.76 MHz ref
RCj Reference clock jitter (RMS) @ 19.44 MHz ref
RC

f

OCj TXDATAOUT+/- jitter (RMS) @ 77.76 MHz ref
OCj TXDATAOUT+/- jitter (RMS) @ 19.44 MHz ref

OCf

range

(1) T he se Reference Clock Jitter limits are required for the outputs to meet SONET system level jitter requirement s

(< 10 mUIrms)
(2) Needed to meet SONET output frequency stability requirements
(3) Measured

Note: Jitter specification is defined utilizing a 12KHz - 5MHz LP-HP single pole filter.

Reference clock frequency tolerance

Output frequency ( a lternating 10 pattern) 620 624 Mb/s

(2)

(1)
(1)

-20 +20 ppm

(3)
(3)

13 ps

5ps

8ps

15 ps

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ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux
with Integrated Clock Generation and Clock Recovery

Package Pin Description

Table 13: Pin Definitions

Signal Pin I/O Level Pin Description

F ACLOOP 1 I TTL Facility loopback, loops high-sp eed da ta
VDD 2 +3.3V +3.3V Power Supply

CRUEQLP 3 I TTL

RESET 4 I TTL Resets frame detection, dividers, controls; active high
LOOPTIM0 5 I TTL Enable loop timing operation; active high
N/C 6 No connection
REFSEL 7 I TTL Reference clock select, refer to table 11
N/C 8 No connection
VDDP 9 +3.3/+5V +3.3V or +5V Power Supply for PECL I/Os
TXDATAOUT+ 10 O PECL Transmit outp ut, high speed differential data +
TXDATAOUT- 1 1 O PECL Transmit output, high speed differential data ­VSS 12 GND Ground
N/C 13 No connection
N/C 14 No connection
VDDP 15 +3.3/+5V +3.3V or +5V Power Supply for PECL I/Os
N/C 16 No connection
LOSDETEN_ 17 I TTL Enables internal LOS detection (acti ve low).
VSS 18 GND Ground
RXCLKIN+ 19 I PECL Receive high speed differential clock input+
RXCLKIN- 20 I PECL Receive high speed different ial clock input­VDDP 21 +3.3/+5V +3.3V or +5V Power Supply for PECL I/Os
OOF 22 I TTL Out Of Frame; Frame detection initiated with high level
DSBLCRU 23 I TTL Disable on-chip clock recovery unit; active high
RXDATAIN+ 24 I PECL Receive high speed differential data input+
RXDATAIN- 25 I PECL Receive high speed differential data input­NC 26 No connection
NC 27 No connection
VDD 28 +3.3V +3.3V Power Supply
REFCLKP+ 29 I PECL PECL reference clock input+
REFCLKP- 30 I PECL PECL reference clock input­VDD 31 +3.3V +3.3V Power Supply

CRU equipment loopback, loops TXDATAOUT to the CRU
replacing RXDATAIN+/-

Data Sheet

VSC811

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Data Sheet

SC8114

Signal Pin I/O Level Pin Description

N/C 32 No connection
RXOUTP 33 O TTL
VSS 34 GND Ground
RXOUT0 35 O TTL Receive output data bit0
RXOUT1 36 O TTL Receive output data bit1
VSS 37 GND Ground
RXOUT2 38 O TTL Receive output data bit2
RXOUT3 39 O TTL Receive output data bit3
VSS 40 GND Ground
RXOUT4 41 O TTL Receive output data bit4
RXOUT5 42 O TTL Receive output data bit5
VSS 43 GND Ground
RXOUT6 44 O TTL Receive output data bit6
RXOUT7 45 O TTL Receive output data bit7
VSS 46 GND Ground
RXLSCKOU T 47 O TTL Receive byt e clock output
FP 48 O TTL Frame detection pulse
VDD 49 +3.3V +3.3V Power Supply
TXPERR 50 O TTL Transmit input data parity error
CRUREFCLK 51 I TTL Optional external CRU reference clock @ 77.76MHz
LOSTTL 52 I TTL Loss of Signal Control - TTL input
LOSPECL 53 I PECL Loss of Signal Control- Single ended PECL input
VDD 54 +3.3V +3.3V Power Supply
VSS 55 GND Ground
N/C 56 No connection
N/C 57 No connection
VDD 58 +3.3V +3.3V Power Supply
VSSA 59 GND Analog Ground (CMU)
VSSA 60 GND Analog Ground (CMU)
N/C 61 No connection
VDDA 62 +3.3V Analog Power Supply (CMU)
CP1 63 Analog CMU external ca pacitor (see Figure 6, and Table 1)
CN1 64 Analog CMU external capacitor (see Figure 6, and Table 1)
CN2 65 Analog CMU external capacitor (see Figure 6, and Table 1)

ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux

with Integrated Clock Generation and Clock Recovery

Receive output data even parity

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SEMICONDUCTOR CORPORATION

ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux
with Integrated Clock Generation and Clock Recovery

Signal Pin I/O Level Pin Description

CP2 66 Analog CMU external ca pacitor (see Figure 6, and Table 1)
VDDA 67 +3.3V Analog Power Supply (CMU)
VDDA 68 +3.3V Analog Power Supply (CRU)
VDDA 69 +3.3V Analog Power Supply (CRU)
VSSA 70 GND Analog Ground (CRU)
VSSA 71 GND Analog Ground (CRU)
VSS 72 GND Ground
N/C 73 No connection

N/C

VSS 75 GND Ground
VDD 76 +3.3V +3.3V Power Supply
N/C 77 No connection
N/C 78 No connection
N/C 79 No connection

N/C

VDD 81 +3.3V +3.3V Power Supply
TXLSCKOUT 82 O TTL Transmit byte clock out
TXLSCKIN 83 I TTL Transmit byte clock in
VSS 84 GND Ground
TXIN7 85 I TTL Transmit input data bit7
TXIN6 86 I TTL Transmit input data bit6
VSS 87 GND Ground
TXIN5 88 I TTL Transmit input data bit5
TXIN4 89 I TTL Transmit input data bit4
N/C 90 No connection
TXIN3 91 I TTL Transmit input data bit3
TXIN2 92 I TTL Transmit input data bit2
VSS 93 GND Ground
TXIN1 94 I TTL Transmit input data bit1
TXIN0 95 I TTL Transmit input data bit0
N/C 96 No connection
TXINP 97 I TTL Transmit input data even parity
CRUREFSEL 98 I TTL Selects between CMU’s or CRU’s reference clock

VDD 99 +3.3V +3.3V Power Supply
EQULOOP 100 I TTL Equipment loopback, loops low-speed byte-wide data

74 No connection

80 No connection

Data Sheet

VSC811

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G52185-0, Rev 4.0

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Data Sheet

SC8114

Package Information

PIN 100

PIN 1

EXPOSED
HEATSINK

(NOTE 2)

9.0 X 9.0
(N0TE 2)

PIN 30

TOP VIEW

D

D1

(NOTE 2)

RAD 2.92 ± .50

(2X)

ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux

with Integrated Clock Generation and Clock Recovery

100 PQFP Package Drawings

Key mm Tolerance

A3.40 MAX

A1 0.25 MIN.
A2 2.7 ±.10

D 17.20 ±.20

D1 14.00 ±.10

E 23.20 ±.20

E1 20.00 ±.10

L0.80 ±.2

e 0.65 NOM
b0.30 ±.10
θ 0°-7°

R.30 +0/-.1

R1 .2 NOM

θ2 15°
θ3 15°

(NOTE 2)

2.54±.50
(2X)

PIN 50

E

E1

A

2

NOTES:
(1) Drawings not to scale.

(2) Two styles of exposed heat spreaders

may be used; square or oval.

(3) All units in millimeters unless otherwise noted

G52185-0, Rev 4.0 

e

A

0.17 MAX

VITESSE SEMICONDUCTOR CORPORATION

R

0.25

R

1

6° ± 4°

L

θ

2

A

1

θ

θ

3

b

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Package #: 101-202-4
Issue #: 1

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ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux
with Integrated Clock Generation and Clock Recovery

The VSC8114 is manufact ur ed i n a 100 PQFP package which is supplied by two diff erent vendors. The crit­ical dimensions in the drawing represent the superset o f dimensions for both pac kages. The s ignificant differ­ence between the two packages is in the shape and size of the heatspreader which needs to be considered when
attaching a heatsink.

Data Sheet

VSC811

Package Thermal Characteristics

The VSC8114 is packaged in a thermally enhanced 100PQFP with an embe dded heat s ink. The heat sink
surface configurat ions are shown in the package drawi ngs. With natural convection, the c ase to air th ermal re sis­tance is estimated to be 27.5

Junction to case thermal resistance is 1.2

o

C/W. The air flow versus thermal resistance relationship is shown in Table 14.

Table 14: Theta Case to Ambient versus Air Velocity

Air Velocity

(LFPM)

027.5
100 23.1
200 19.8
400 17.6
600 16

o

C/W

Case to air thermal resistance

o

C/W

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G52185-0, Rev 4.0

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Data Sheet

SC8114

Ordering Information

The order number for this product are:

Part Number Device Type
VSC8114QB: 622Mb/s Mux/Dmux with CMU and CRU in 100 Pin PQFP

VSC8114QB1 622Mb/s Mux/Dmux with CMU and CRU in 100 Pin PQFP

VSC8114QB2 622Mb/s Mux/Dmux with CMU and CRU in 100 Pin PQFP

ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux

with Integrated Clock Generation and Clock Recovery

Commercial Temperature, 0°C ambient to 70°C case

Extended Temperature, 0°C to 85°C ambient (equivalent to 0°C ambient to

115°C case)

Industrial Temperature, -40°C ambient to 85°C case

Notice

This document contains preliminary information about a new product in the preproduction phase of devel­opment. The information in this docume nt is based on i niti al pr oduct characterization. Vitesse reserv es th e right
to alter specifications, features, capabilities, functions, manufacturing release dates, and even general availabil­ity of the product at any time. The reader is cautioned to confirm this datasheet is current prior to using it for

.

design

Warning

Vitesse Semiconductor Corporation’s product are not intended for use in life support appliances, devices or sys­tems. Use of a Vitesse product in such applications without the written consent is prohibited.

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ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux
with Integrated Clock Generation and Clock Recovery

Data Sheet

VSC811

Application Notes

Interconnecting the Byte Clocks (TXLSCKOUT and TXLSCKIN)

The byte clock (TXLSCKOUT and TXLSCKIN) on the VSC8114 has been brought off-chip to allow as
much flexibility in system-level clocking schemes as po ssible. Sin ce the b yte clo ck (TXLSCK OUT) clock s both
the VSC8114 and the UNI devices, it is important to pay close attention to the routing of this signal. The UNI
device in general is a CMOS part which can have very wide spreads in timing (1-11ns clock in to parallel data
out for the PM5355), which utilizes most of the 12.86ns p eriod (at 78MH z), leaving little for the trace delays
and set-up times required to interconnect the 2 devices.

The VSC8114 and the UNI device should be placed as close to each other as possible to provide maximum
setup and hold time margin at the inputs of the VSC8114. Figure 12 suggests two different ways of routing the
TXLSCKOUT-to-TXLSCKIN clock trace when used in a 622 MHz mode, which ever method is used the trans­mission line trace impedance should be no lower than 75 ohms.

Figure 12: Interconnecting the Byte Clocks

VSC8114

TXIN[7:0]

PM5355

POUT[7:0]

TXLSCKIN

(1) (2)

TXLSCKOUT

T

trace

TCLK

(1) TXLSCKOUT and TXLSCKIN are tied together at the pins of the VSC8114. This provides a setup and
hold time margin for the TXIN input of

• T

su,margin

• T

hold,margin

- T

clk

= T

TCLK-POUT,min

TCLK-POUT,max

(PM5355) - T

(PM5355) - T

su,min

hold,min

(VSC8114) - 2xT

(VSC8114) + 2xT

trace

trace

= 2xT

= 0.86ns - 2xT

trace

trace

= T

(2) TXLSCKOUT is daisy chained to the UNI device and then routed back to the VSC8114 along with the
byte data. This interface provides a setup and hold time margin for the TXIN input of

= T

• T

su,margin

• T

hold,margin

- T

clk

= T

TCLK-POUT,min

TCLK-POUT,max

Option (2) does not provide an y hold ti me mar gin , while optio n (1) requ ires the one-w ay t race delay (T

(PM5355) - T

(PM5355) - T

su,min

hold,min

(VSC8114) = 0.86ns

(VSC8114) = 0ns

trace

to be less than 0.43ns (~3 inches).

The general recommendation is to apply option (1) and place the VSC8114 and PM5355 as close to each
other as possible. If the one-way trace delay canno t be kept less than 0.43ns with a 50pf load , daisy-chaining
(option 2) should be applied - close attention must be paid to signal routing in this case because of the lack of
hold time margin.

)

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Data Sheet

SC8114

Important note: The 11 ns max Tpd on the PM5355 assumes a 50pf load @ 6 0ps/pf, therefore 3 ns of the
max delay is due to loading . The VSC811 4 inpu t (TXLSCKIN) plus pac kage is a bout 6p f. Assumin g about 1 p f/
inch of 75 ohm trace on FR4 plus the VSC8114 6pf load, the user would in most cases choose option 1.

DC Coupling and Terminating High-speed PECL I/Os

The high speed signals on the VSC8114 (RXDATAIN, RXCLKIN, TXDATAOUT, REFCLKP, LOSPECL)
use 3.3/5V programmable PECL I/Os which can be direct coupled to either +3.3V PECL or +5V PECL signals
from the optics. Thes e PECL levels are esse ntially EC L levels shifted positive by 3.3 volts or 5 volts. T hese
PECL I/Os are referenced to the V
either 3.3V or 5V interface, the 3 V
accordingly.

AC Coupling and Terminating High-speed PECL I/Os

If the optics modules provide ECL level interface, the high speed sig nals can be AC coupled to the
VSC8114 as well. The PECL receiver inputs of the VSC8114 are internally biased at VDD/2. The refore, AC­coupling to the VSC8114 inputs is accomplished by providing the pull-down resistor for the open-source PECL
output and an AC-coupling capacitor used to eliminate the DC component of the output signal. This capacitor
allows the PECL receivers of the VSC8114 to self-bias via its internal resistor divider network (see Figure 14).

The PECL output drivers are capable of sourcing current but not sinking it. To establish a LOW output
level, a pull-down resistor, traditionally connected to VDD-2.0V, is needed when the output FET is turned off.
Since VDD-2.0V is usually not present in the system, the resistor should be terminated to ground for conve­nience. The VSC8114 output drivers should be either AC-coupled to the 5.0V PECL inputs of the optics mod­ule, or translated (DC le v el shift ). Appropr iate bia sing techniques f or setti ng the DC-l e v el of th ese input s should
be employed.

The dc biasing and 50 ohm termination requirements can easily be integrated together using a thevenin
equivalent circuit as shown in Figure 14. The figure shows the appropria te termin ation values wh en interfac ing

3.3V PECL to 5.0V PECL. This network provides the equivalent 50 ohm termination fo r the high speed I/Os
and also provides the requi red dc biasin g for the rec ei v ers of the opt ics modu le. Table 15 contains recommended
values for each of the components.

supply (VDDP) and are terminated to ground. To program these I/Os for

DDP

DDP

ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux

with Integrated Clock Generation and Clock Recovery

pins (pin 9, 15, 21) are required to connect to 3.3V or 5V supplies

TTL Input Structure

The TTL inputs of the VSC8114 are 3.3V TTL which can accept 5.0V TTL levels within a given set of tol­erances (see Table 8). The input structure, shown in Figure 14, uses a current limiter to avoid overdriving the
input FETs.

Initialization

The VSC8114 contains a “RESET” cap’s pin which is only needed for VLSI production test requirements
at Vitesse. The chip will initialize on its own as data is clocked through the device. The receive section will
frame align on the A1, A2 boundary of the incoming SONET/SDH data stream. (See R eceive section on page

3).

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ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux
with Integrated Clock Generation and Clock Recovery

Layout of the High Speed Signals

Data Sheet

VSC811

The routing of the High Speed signals should be done using good high speed design practices. This would
include using controlle d impedance lines and keep ing the distance between com ponents to an absolu te mini­mum. In addition, stubs should be kept at a minimum as well as any routing discontinuities. This will help min­imize reflections and ringing on the high sp eed lines and insur e the maximum eye opening. I n addition the
output pull down resistor should be placed as close to the VSC8114 pin a s possible while the AC-coupling
capacitor and the biasing resistors should be placed as close as possible to the optics input pin. The same is true
on the receive circuit side. Using small outline components and minimum pad sizes also helps in reducing dis­continuities.

Ground Planes

The ground plane for the components used in the High Speed interface should be continuous and not sec­tioned in an attempt to provide isolation to various components. Sectioning of the ground planes tends to inter­fere with the ground return currents on the signal lines. In addition, the smaller the ground plane s the less
effecti ve they are in redu cin g ground bounce noise and the more dif ficult to decouple. Sect ion in g of the positive
supplies can provide some isolation benefits.

Figure 13: AC Coupled High Speed I/O

+3.3V

DRIVER
(Optics Module)

PC Board Trace PC Board Trace

R1

GND

Table 15: AC Coupling Component Values

Component Value Tolerance

R1 270 ohms 5%
R2 75 ohms 5%
R3 68 ohms 1%
R4 190 ohms 1%

C1, C2, C3, C4 .01uf High Frequency

GND

Note: Only one side of a differential signal is shown.

VSC8113

VSC8114

PECL I/O

R2 R4

GND

C2C1

+5.0V

GND

RECEIVER
(Optics Module)

R3

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G52185-0, Rev 4.0

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Data Sheet

SC8114

INPUT

+3.3 V

V

DD

Current

Limit

R

R

GND

REFCLK and TTL Inputs

ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux

with Integrated Clock Generation and Clock Recovery

Figure 14: ¥Input Structures

V

DDP

+3.3 /+5 V

INPUT

INPUT

GND

High Speed Differential Input

(RXDATAIN+/RXDATAIN-)

(RXCLKIN+/RXCLKIN-)

All Resistors

3.3K

+3.3 V

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SEMICONDUCTOR CORPORATION

ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux
with Integrated Clock Generation and Clock Recovery

Data Sheet

VSC811

Page 24 

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G52185-0, Rev 4.0