The VSC7940 is a single 5V supply laser diode driver specially designed for SONET/SDH applications up
to 3.125Gb/s. External resistors set a wide range of bias and modulation currents for driving the laser. Data and
clock inputs accept differential PECL signals. The Automatic Power Control (APC) loop maintains a constant
average optical power over temperature and li fetime. The domi nant pole of t he APC loop can be c ontrol led with
an external capacitor. Other features include enable/disable control, programmable slow-start circuit to set laser
turn-on delay, and failure-monitor output to indicate when the APC loop is unable to maintain the average optical power. The VSC7940 is available in die form or in a 32-pin TQFP package.
AC specifications are guaranteed by design an d characterization. Typical values are for 5V operation.
SymbolParameterMinTypMaxUnitsConditions
t
SU
t
H
t
R
t
F
PWDPulse Width Distortion1050psSee Notes 1, 2
CID
t
J
NOTES: (1) Measured with 622Mb/s 0-1 pattern , LATCH=high. (2) P WD = (wi der pulse - narrower pulse) / 2).
Input Latch Setup Time100psLATCH=high
Input Latch Hold Time100psLATCH=high
Enable/Start-up Delay250ns
Output Rise TimeTBDTBDps20% to 80%
Output Fall TimeTBDTBDps20% to 80%
Maximum Consecu tive Identical D igits80bits
MAX
Jitter Generation720ps
p-p
Jitter BW=12kHz to 20MHz,
0-1 pattern.
VSC7940
Table 2: DC Specifications
SymbolParameterMinTypMaxUnitsConditions
V
SS
I
CC
I
BIAS
I
BIAS-OFF
S
BIAS
VR
MD
I
MD
I
MOD
I
MOD-OFF
Power Supply Voltage4.755.05.25V
R
Power Supply CurrentTBD45mA
Bias Current Range1100mAVoltage at BIAS pin=(VCC-1.6)
Bias Off Current100µA
Bias Current Stability
Bias Current Absolute Accuracy±15%Refers to part-to-part variation
Monitor Diode Reverse Bias Voltage1.5V
Monitor Diode Reverse Current Range181000µA
Monitor Diode Bias Setpoint Stability
Monitor Diode Bias Absolute Accuracy-1515%Refers to part-to-part variation
Modulation Current Range5100mA
Modulation Off Current200µA
Modulation Current Absolute Accuracy±15%See Not e 2
will turn off if any of the current set pins are grounded. (2) Assume s l ase r di ode t o monitor diode transfer func-
MOD
ppm/°C
I
=60mA
MOD
=5mA
MOD
BIAS/IBIASMON
MOD/IMODMON
Table 3: PECL and TTL/CMOS Input/Output Specifications
SymbolParameterMinTypMaxUnitsConditions
V
ID
V
ICM
I
IN
V
IH
V
IL
Differential Input Voltag e1001600mV
-
CC
1.49
VCC -
1.32
V
Common-Mode Input Voltage
Clock and Data Input Current-110mA
TTL Input High Voltage (ENABLE, LATCH)2.0V
TTL Input Low Voltage (ENABLE, LATCH)0.8V
TTL Output High Voltage (FAIL
TTL Output Low Voltage (FAIL
)2.4
)0.10.44VSinking 100µA
V
CC
0.3
VCC V
ID
V
CC
VPECL-compatible
/4
VSourcing 50µA
(DATA+)-(DATA-)
p-p
Absolute Maximum Ratings
(1)
Power Supply Voltage (VCC).............................................................................................................-0.5V to +7V
Current into BIAS.....................................................................................................................-20mA to +150mA
Current into OUT+, OUT-...............................................................................................................................TBD
Current into MD.............................................................................................................................-5mA to +5mA
Current into FAIL
Voltage at DATA+, DATA-, CLK+, CLK-, ENABLE, LATCH.........................................-0.5V to (V
Voltage at APCFILT, MODSET, BIASMAX, APCSET, MD, FAIL
Voltage at OUT+, OUT- ..................................................................................................... -0.5V to (V
Voltage at BIAS.................................................................................................................. -0.5V to (V
Continuous Power Dissipation (T
......................................................................................................................... -10mA to 30mA
+ 0.5V)
CC
.............................................-0.5V to +3.0V
Operating Junction Temperature Range...................................................................................... -55°C to +150°C
Storage Temperature Range ........................................................................................................ -65°C to +165°C
NOTE: (1) CAUTION: Stresses listed under “Absolute Maximum Ratings” may be applied to devices one at a time without caus-
ing permanent damage. Functionality at or above the values listed is not implied. Exposure to these values for extended
periods may affect device reliability.
Recommended Operating Conditions
Positive Voltage Rail (VCC)..............................................................................................................................+5V
Negative Voltage Rail (GND) ............................................................................................................................ 0V
Ambient Temperature Range (T
)..................................................................................................-40°C to +85°C
SONET/SDH 3.125Gb/s
Laser Diode Driver with Automatic Power Control
Bare Die Pad Descriptions
Figure 1: Pad Assignments
1773
µm (0.0698")
Pad 10
GND1
Pad 11
LATCH
Pad 12
ENABLE
Pad 13
DISABLE
Pad 14
GND1
Pad 15
BIASMON
Pad 9
VCC1
(Pin 8)
(Pin 9)
(Pin 10)
(Pin 11)
Pad 8
CLK-
Pad 7
CLK+
(Pin 5)
Pad 6
VCC1
Pad 5
GND1
Pad 4
VCC1
Pad 3
DATA-
Pad 2
DATA+
Preliminary Data Sheet
VSC7940
Pad 1
Pad 48
VCC1
GND1
(Pin 1)(Pin 2)(Pin 3)(Pin 4)(Pin 6)(Pin 7)
(Pin 32)
(Pin 31)
(Pin 30)
(Pin 29)
Pad 47
GND2
Pad 46
VCC2
Pad 45
BIASMAX
Pad 44
MODSET
Pad 43
GND2
Pad 42
APCSET
20
µm
(0.0008")
Pad 16
(Pin 12)
2233
µm
(0.0879")
MODMON
Pad 17
FAIL
Pad 18
GND4
Pad 19
PB_GND
Pad 20
APCFILT
Pad 21
GND4
Pad 22
VCC4
Pad 23
BIAS
(Pin 13)
(Pin 14)
(Pin 15)
(Pin 16)
(Pin 17)
Pad 24
PB_GND1
(Pin 18)(Pin 19)(Pin 20)(Pin 21)(Pin 22)(Pin 23)(Pin 24)
Pad 25
VCC4
Pad 26
DB_OUT+
Pad 27
OUT+
VSC7940
Pad 28
OUT-
Die Size:1773µm x 2233µm (0.0698" x 0.0879")
Die Thickness:625µm (0.0246")
Pad Pitch:115µm (0.0045")
Pad to Pad Clearance:20µm (0.0008")
Pad Passivation Opening: 95µm x 95µm (0.0037" x 0.0037")
DATA+2Positive Data Input (PECL)
DATA-3Negative Data Input (PECL)
CLK+5Positive Clock Input (PECL). Connect to V
CLK-6Negativ e Clock Input (PECL). Leave unconn ected if LATCH function is not used.
LATCH8Latch Input (TTL/CMOS). Connect to VCC for data retiming and GND for direct data.
ENABLE9
DISABLE10
BIASMON11Bias Current Monitor. Sink current source that is proportional to the laser bias current.
MODMON12
FAIL13Output (TTL/CMOS). When low, indicates APC failure.
APCFILT14No effect on dev ice operation.
BIAS17Laser Bias Current Output
OUT+19Positive Modulation-Current Output. I
OUT-20Negative Modulation-Current Output. I
MD24
CAPC26Capacitor to GND sets dominant pole of the APC feed back loop.
RESERVED28Do not connect.
APCSET29
MODSET30Connect resistor to GND to set desired modulation current.
BIASMAX31
10, 15, 22,
23, 27
1, 4, 7, 16, 18,
21, 25, 32
Ground
Power Suppl y
if LATCH function is not used.
CC
Enable Input (TTL/CMOS). If used, connect DISABLE to GND. Connect to V
normal operation and GND to disable laser bias and modulation currents.
Disable Input (TTL/CMOS). If used, leave ENABLE pin floating. Connect to GND for
normal operation and V
Modulation Current Monitor. Sink current source that is proportional to the laser
modulation current.
Monitor Diode Input. Connect to monitor photodiode anode. Connect capacitor to GND to
filter high-speed AC monitor photocurrent.
Resistor to GND sets desired average optical power. If APC is not used, connect 100kΩ
resistor to GND.
Connect resistor to GND to set maximum bias current. The APC function can subtract from
this value, but cannot add to it.
SONET/SDH 3.125Gb/s
Laser Diode Driver with Automatic Power Control
Preliminary Data Sheet
VSC7940
Detailed Description
The VSC7940 is a high-speed l aser dri ver with Automatic Power Con trol. The device is desig ned to operate
up to 3.125Gb/s with a 5V supply. The data and clock inputs support PECL inputs as well as other inputs that
meet the common-mode voltage and differential voltage swing specifications. The differential pair output stage
is capable of sinking up to 100mA into the laser with ty pical rise and fall times of 60ps. The VSC79 40 is
designed to be DC-coupled . The k e y feat ures of the VSC7940 are its Automatic Power C ontr ol , l ow po wer supply current, and fast rise and fall times. The VSC7938 and VSC7939 are similar Vitesse laser drivers designed
for 60mA maximum output modula ti on cur rent s. T hese laser drivers may be powered from a 3.3V or 5V suppl y
and may be AC- or DC-couple d t o t he laser diode. The VSC7939 is available in the same 32-pin TQFP package
as the VSC7940. The VSC7938 is available in a 48-pin TQFP package.
Automatic Power Control
To ensure constant average optical power, the VSC7940 utilizes an Automatic Power Control (APC) loop.
A photodiode mounted in the laser package provides optical feedback to compensate for changes in average
laser output power due to changes that affect laser performance such as temperature and laser lifetime. The laser
bias current is adjusted by the APC loop according to the reference current set at APCSET by an external resistor. An external capacitor at CAPC controls the time constant for the APC feedback loop. The recommended
value for CAPC is 0.1
and guarantees stability. Because the APC loop noise is internally filtere d, APCFILT is not i nternal l y conn ect ed
and does not need to be connect ed to any external components. The device’s performance will not be affected if
a capacitor is connected to APCFILT. If the APC loop cannot adjust th e bias current to track th e desired monit or
current, FAIL
The device may be operated with or without APC. To utilize APC, a capacitor must be connected at CAPC
µF) and a resistor must be connected at APCSET to set the average optical power. For open-loop operation
(0.1
(no APC), a 10 0k
loop operation. In both mo des of o peratio n, resist ors to ground sho uld be p laced at BIASMAX and MODSET to
set the bias and modulation currents.
is set low.
µF. This value reduces pattern-dependent jitter associated with the APC feedback loop
Ω resistor should be connected between APCSET and GND. CAPC has no effect on open-
Data Retiming
The VSC7940 provides inpu ts for differential PECL cl ock signals for data ret iming to minim ize jitter at
high speeds. To incorporate this function, LATCH shou ld be connected to V
CLK+ should be connected to V
GND.
Short-Circuit Protection
If BIASMAX or MODSET are shorted to ground, the output mo dulation and bias currents will be turned
off.
Modulation and Bias Current Monitors
The VSC7940 provides monitoring of the modulation and bias currents vias BIASMON and MODMON.
These pins sink a current proportiona l to the actual modu lation and bias curren ts. MODMON sinks approximately 1/29th of the amount of modulation current and BIASMON sink approximately 1/37th of the amount of
the bias current. These pins should be tied through a pull-up resistor to V
that the voltage at MODMON is greater than V
Two pins are provided to a llow either EN ABLE or DISABLE contr ol. If ENABLE is used, co nnect DISABLE to ground. Is DISABLE is used, leave ENABLE floating. Both modulation and bias currents are turned
off when ENABLE is low or DISABLE is high. Typically, ENABLE or DISABLE responds to within approximately 250ns.
Controlling the Modulation Current
The output modulation current may be determined from the following equation where P
peak optical power, P
is the average power, r
AVE
I
MOD
= P
A resistor at MODSET controls the output bias current. Graphs of I
is the extinction ratio, and η is the laser slope efficiency:
e
/ η= 2 * P
p-p
* (re-1) / (re+1) / η
AVE
MODSET
vs. R
MODSET
is the peak-to-
p-p
in Typical Operat-ing Characteristics describe the relationship between the resistor at MODSET and the output modulation current at 25
°C. After determining the desired output modulation current, use the graph to determine the
appropriate resistor value at MODSET.
Controlling the Bias Current
A resistor at BIASMAX should be used to control the output bias current. Graphs of I
BIASMAX
vs. R
in Typical Operating Characte rist i cs describ e the relation ship between the resistor at BIASMAX and the out put
bias current at 25
°C. If the APC is not used, the appropriate resistor value at BIASMAX is determined by first
selecting the desired output bias current, and then using the graph to determine the appropriate resistor value at
BIASMAX. When using APC, BIASMAX sets the maximum allowed bias current. After determining the maximum end-of-life bias current at 85
°C for the laser, refer to the graph of I
BIASMAX
vs. R
BIASMAX
in Typical Oper-
ating Characteristics to select the appropriate resistor value.
BIASMAX
Controlling the APC Loop
To select the resistor at APCSET, use the graph of IMD vs. R
The graph relates the desired monitor current to the appropriate resistance value at APCSET. I
late from the desired optical average power, P
, and the laser-to-monitor transfer, ρ
AVE,
in Typical Operating Characteristics.
APCSET
MD
, for a specific laser
MON
may be calcu-
using the following equa tion:
Laser Diode Interface
I
MD
= P
AVE
* ρ
MON
An RC shunt network should be placed at the laser outpu t interface. Th e sum of the re sistor placed at the
output and the laser diode resistance should be 25
Ω resistor should be placed in series with the laser. For optimal performance, a bypass capacitor should be
20
Ω. For exam ple, if t he lase r diode ha s a resis tance of 5Ω, a
placed close to the laser anode.
A “snubber network” consisting of a capacitor C
minimize reflections from the laser (see Block Diagram). Suggested values for these components are 80
and resistor RF should be placed at the laser output to
F
Ω and
2pF, respectively, however, these values should be adjusted until an optical output waveform is obtained.
SONET/SDH 3.125Gb/s
Laser Diode Driver with Automatic Power Control
Reducing Pattern-Dependent Jitter
Preliminary Data Sheet
VSC7940
Three design values significantly affect pattern-dependent jitter; the capacitor at CAPC, the pull-up inductor at the output (L
value for the capacitor at CAPC is 0.1
), and the AC-coupling c apaci t or at t he out put (CD). As previously stated, the recommended
P
µF. This results in a 10kHz loop bandwidth which makes the pattern-
dependent jitter from the APC loop negligible.
For 2.5Gb/s data rates, the recommended value for C
nated by L
. The variation in the peak vo ltage should be less that 12% of the average voltage over the maximum
P
is 0.056µF. The time constant at the output is domi-
D
consecutive identical digit (CID) period. The following equation approximates this time constant for a CID
period, t, of 100UI = 40ns:
τ
= -t / ln(1-12%) = 7.8t = LP / 25Ω
LP
Therefore, the inductor LP should be a 7.8µH SMD ferrite bead inductor for this case.
Input/Output Considerations
Although the VSC7940 is PECL-compatible, this is not required to drive the device. The inputs must only
meet the common-mode voltage and differential voltage swing specifications.
Power Consumption
The following equation provides the device supply current (IS) in terms of quiescent current (IQ), modulation current (I
), and bias current (I
MOD
BIAS
):
I
= 19mA + 0.4 * I
S
+ 0.16 * I
MOD
BIAS
This equation may be used to determine the estimated power dissipation:
P
= VCC * I
DIS
S
For example, if the device were operated at 5V with a 30mA modulation current and a 10mA bias current,
the supply current would be:
= 19mA + 0.4 * 30mA + 0.16 * 10mA = 33mA
I
S
This corresponds to a power dissipation of 5V * 33mA = 165mW.P
Assuming the modulation and bias currents never exceed 120mA, the following equations provide values
for the resistor at MODMON, R
Standard values for these values are R
MODMON would indicate a modulation current of:
Wire Bonding
For best performance, gold ball-bonding techniques are recommended. Wedge bonding is not recommended. For best performance and to minimize inductance keep wire bond lengths short.
MODMON
I
MOD
, and the resistor at BIASMON, R
R
MODMON
R
BIASMON
= 1.6V * 35 / 120mA = 467Ω
MODMON
= (5.2V - 4.8V) * 28 / 232mA = 48mA
Laser Diode Driver with Automatic Power Control
BIASMON
= 1V * 28 / 120mA = 233Ω
= 232Ω and R
BIASMON
SONET/SDH 3.125Gb/s
:
= 464Ω. A voltage of 4.8V at
PCB Layout Guidelines
Use high frequency PCB layout techniques with solid ground planes to minimize crosstalk and EMI. Keep
high speed traces as short as possible for signal integrity. The output traces to the laser diode must be short to
minimize inductance. Short output traces will provide best performance.
The order number for this product is formed by a combination of the device type and package type.
Device Type
SONET/SDH 3.125Gb/s
Laser Diode Driver with Automatic Power Control
VSC7940
SONET/SDH 3.125Gb/s
Laser Diode Driver with Automatic Power Control
xx
Package
RP: 32-Pin TQFP
W:Dice Waffle Pack
otice
itesse Semiconductor Corporation (“Vitesse”) provides this document for informational purposes only. This document contains pre-production information
bout Vitesse products in the ir co ncept, developm ent a nd/or tes tin g phase. Al l infor matio n in this docume nt, in cludi ng desc ripti ons of features, functions,
erformance, technica l s p ecifications and availability, is subject to chan g e wit h o ut n ot i ce at any time. Nothing contained in t his document shall be construed
s extending any warr anty or p romise , expr ess or impl ied, t hat a ny Vitesse prod uct will be a vaila ble as desc rib ed or wi ll be sui table for or will accomplish
ny particular task.
itesse products are not intended for use in life support appliances, devices or systems. Use of a Vitesse product in such applications without written consent