Datasheet VSC7182TW Datasheet (VITESSE)

VITESSE

®

Quad Transceiver

SEMICONDUCTOR CORPORATION

Advance Product Information

for Gigabit Ethernet and Fibre Channel

Features

• Four Complete Transmitter/ Receiver Functions
in a Single Integrated Circuit

• Full Fibre Channel (T11) and Gigabit Ethernet
(IEEE 802.3z) Compliance

• 1.05Gb/s to 1.36Gb/s Operation per Channel

• Common or Per-Channel Transmit Byte Clocks

• TTL or PECL Reference Clock Input

• Receiver Squelch Circuit

• Common and Per-Channel, Serial and Parallel
Loopback Controls

• Common Comma Detect Enable Inputs

• Per-Channel Comma Detect Outputs

• Cable Equalization in Receivers

• Replacement For Agilent’s HDMP-1682

• 3.3V Power Supply, 2.67 W Max Dissipation

• 208-Pin, 23mm BGA Packaging

General Description

The VSC7182 is a full-speed quad Fibre Channel and Gigabit Ethernet transceiver IC. Each of the four
transmitters has a 10-bit wide bus, running up to 136MHz, which accepts 8B/10B encoded transmit characters
and serializes the data onto high-speed differential outputs at speeds up to 1.36Gb/s. The transmit data can be
synchronous to the reference clock, a common transmit byte clock or a per-channel transmit byte clock. Each
receiver samples serial receive data, recovers the clock and data, deserializes it into 10-bit receive characters,
outputs a recovered clock and detects “Comma” characters. The VSC7182 contains on-chip Phase-Lock Loop
(PLL) circuitry for synthesis of the baud-rate transmit clock and extraction of the clocks from the received serial
streams. The VSC7182 also includes a receiver squelch circuit to control the parallel data bus in the absence of
serial input.

VSC7182 Block Diagram (1 of 4 Channels)

RXi[0:9]

RCM

RCi1
RCi0

SYNi

SYNC

PLUP
SLPN

LPNi

TXi[0:9]

TCi
RFCT
RFC+
RFC-

RFCM

LTCN

CAP0

CAP1

G52307-0, Rev 2.2 Page 1
10/10/00

10

4

10

4

© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012

Q D

Comma

Detect

Loopback

Control

Clock

Multiply

x10/x20

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Q D

4

Unit

Serial to

Parallel

÷

SEL

÷

10/

÷

20

Internet: www.vitesse.com

10

Parallel

to Serial

Q D

Clock

Recovery

0

1

0

D QD Q

1

SI+
SI-

SO+
SO-

RFCO0
RFCO1

VITESSE

®

VSC7182

SEMICONDUCTOR CORPORATION

Quad Transceiver

Advance Product Information

for Gigabit Ethernet and Fibre Channel

Functional Description

Notation

In this document, each of the four channels are identified as Channel A, B, C or D. When discussing a sig­nal on any specific channel, the signal will have the Channel letter embedded in the name, for example,
“TA[0:9]”. When referring to the common behavior of a signal which is used on each of the four channels, a
lower case “x” is used in the signal name, i.e. TXi[0:9]. Differential signals, such as RA+ and RA-, may be
referred to as a single signal, i.e. RA, by dropping reference to the “+” and “-”. “RFC” refers to either the TTL
input RFCT, or the PECL differential inputs RFC+/RFC-, whichever is used.

Clock Synthesizer

The VSC7182 clock synthesizer multiplies the reference frequency provided on the RFC input by 10 or 20
to achieve a baud rate clock between 1.05GHz and 1.36GHz. The RFC input can be either TTL or PECL. If
TTL, connect the TTL input clock to RFCT. If PECL, connect the PECL inputs to RFC+ and RFC-. The inter­nal clock presented to the clock synthesizer is a logical XNOR of RFCT and RFC+/-. The reference clock will
be active HIGH if the unused input is HIGH. The reference clock is active LOW if the unused input is LOW.
RFCT has an internal pull-up resistor. Internal biasing resistors set the proper DC level on RFC+/- so AC-cou­pling may be used.

The TTL outputs, RFCO0 and RFCO1, provide a clock that is frequency-locked to the RFC input. This
clock is derived from the clock synthesizer and is always 1/10th the baud rate, regardless of the state of the
RFCM input.

The on-chip PLL uses a single external 0.1µF capacitor, connected between CAP0 and CAP1, to control the
loop filter. This capacitor should be a multilayer ceramic dielectric, or better, with at least a 5V working voltage
rating and a good temperature coefficient (NPO is preferred but X7R may be acceptable). These capacitors are
used to minimize the impact of common-mode noise on the Clock Multiplier Unit (CMU), especially power
supply noise. Higher value capacitors provide better robustness in systems. NPO is preferred because if an X7R
capacitor is used, the power supply noise sensitivity will vary with temperature.

For best noise immunity, the designer may use a three capacitor circuit with one differential capacitor
between CAP0 and CAP1, C1, a capacitor from CAP0 to ground, C2, and a capacitor from CAP1 to ground,
C3. Larger values are better but 0.1µF is adequate. However, if the designer cannot use a three capacitor
circuit, a single differential capacitor, C1, is adequate. These components should be isolated from noisy traces.

Figure 1: Loop Filter Capacitors (Best Circuit)

VSC7182

Page 2 G52307-0, Rev 2.2

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CAP0

C1

CAP1

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C2

C3

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C1=C2=C3= >0.1µF
MultiLayer Ceramic
Surface Mount
NPO (Preferred) or X7R
5V Working Voltage Rating

10/10/00

VITESSE

®

Quad Transceiver

SEMICONDUCTOR CORPORATION

Advance Product Information

for Gigabit Ethernet and Fibre Channel

Serializer

The VSC7182 accepts TTL input data as a parallel 10-bit character on the TXi[0:9] bus which is latched
into the input register on the rising edge of either RFC or TCi. Three clocking modes are available and automat­ically detected by the VSC7182. If TCC is static and RFCM is HIGH, then all four TXi[0:9] busses are latched
on the rising edges of RFC. If TCC is static and RFCM is LOW, then RFC is multiplied by 20 and the input bus­ses are latched on the rising edges of RFC and at the midpoint between rising edges. If TCC is toggling but TCB
is static, then all four TXi[0:9] busses are latched on the rising edges of TCC. If TCB and TCC are both toggling
then the rising edge of each TCi latches the corresponding TXi[0:9] bus.

The active TCC or TCi inputs must be frequency-locked to RFC. There is no specified phase relationship.
Prior to normal data transmission, LTCN must be asserted LOW so the VSC7182 can lock to TCi, which may
result in corrupted data being transmitted. Once LTCN has been raised HIGH, the transmitters remain locked to
RFC and can tolerate +/-2 bit times of drift in TCi relative to RFC.

The 10-bit parallel transmission character will be serialized and transmitted on the TXi PECL differential
outputs at the baud rate with bit TXi0 (bit A) transmitted first. User data should be encoded using 8B/10B or an
equivalent code. The mapping to 10B encoded bit nomenclature and transmission order is illustrated below,
along with the recognized comma pattern.

Table 1: Transmission Order and Mapping of a 10B Character

Data Bit TXi9 TXi8 TXi7 TXi6 TXi5 TXi4 TXi3 TXi2 TXi1 TXi0

10B Bit Position j h g f i e d c b a

Comma Character x x x 1 1 1 1 1 0 0

Clock Recovery

The VSC7182 accepts differential high-speed serial input from the selected source (either the PECL SI+/
SI- pins or the internal TXi+/- data), extracts the clock and retimes the data. Equalizers are included in the
receiver to open the data eye and compensate for InterSymbol Interference (ISI) which may be present in the
incoming data. The serial bit stream should be encoded so as to provide DC balance and limited run length by
an 8B/10B encoding scheme. The digital Clock Recovery Unit (CRU) is completely monolithic and requires no
external components. For proper operation, the baud rate of the data stream to be recovered should be within
+200 ppm of ten times the RFC frequency. For example, Gigabit Ethernet systems would use 125MHz oscilla­tors with a +100ppm accuracy resulting in +200 ppm between VSC7182 pairs.

Deserializer

The recovered serial bit stream is converted into a 10-bit parallel output character. The VSC7182 provides
complementary TTL recovered clocks, RCi0 and RCi1, which are at 1/20th of the serial baud rate (if
RCM=LOW) or 1/10th (if RCM=HIGH). The clocks are generated by dividing down the high-speed recovered
clock which is phase-locked to the serial data. The serial data is retimed, deserialized and output on RXi[0:9].

If serial input data is not present, or does not meet the required baud rate, the VSC7182 will continue to
produce a recovered clock so that downstream logic may continue to function. The RCi0/RCi1 output frequency
under these circumstances will differ from its expected frequency by no more than +1%. A receiver squelch cir­cuit forces the parallel data output bus to all ones if the serial receiver input level is less than 100mV differential
peak-to-peak.

G52307-0, Rev 2.2 Page 3
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VITESSE

®

VSC7182

SEMICONDUCTOR CORPORATION

Quad Transceiver

Advance Product Information

for Gigabit Ethernet and Fibre Channel

Word Alignment

The VSC7182 provides 7-bit comma character recognition and data word alignment. Word synchronization
is enabled on all channels by asserting SYNC HIGH. When synchronization is enabled, the receiver examines
the recovered serial data for the presence of the “Comma” pattern. This pattern is “0011111XXX”, where the
leading zero corresponds to the first bit received. The comma sequence is not contained in any normal 8B/10B
coded data character or pair of adjacent characters. It occurs only within special characters, known as K28.1,
K28.5 and K28.7, which are defined for synchronization purposes. Improper comma alignment is defined as
any of the following conditions:

1) The comma is not aligned within the 10-bit transmission character such that RXi(0...6) = “0011111.”

2) The comma straddles the boundary between two 10-bit transmission characters.

3) The comma is properly aligned but occurs in the received character presented during the rising edge of

RCi0 rather than RCi1.

When SYNC is HIGH and an improperly aligned comma is encountered, the recovered clock is stretched,
never slivered, so that the comma character and recovered clocks are aligned properly to RXi[0:9]. This results
in proper character and word alignment. When the parallel data alignment changes in response to a improperly
aligned comma pattern, data which would have been presented on the parallel output port prior to the comma
character, and possibly the comma character itself, may be lost. Possible loss of the comma character is data
dependent, according to the relative change in alignment. Data subsequent to the comma character will always
be output correctly and properly aligned. When SYNC is LOW, the current alignment of the serial data is main­tained indefinitely, regardless of data pattern.

On encountering a comma character, SYNi is driven HIGH. The SYNi pulse is presented simultaneously
with the comma character and has a duration equal to the data. The SYNi signal is timed such that it can be cap­tured by the adjoining protocol logic on the rising edge of RCi1. Functional waveforms for synchronization are
given in Figure 2. The first K28.5 shows the case where the comma is detected, but it is misaligned so a change
in the output data alignment is required. Note that up to three characters prior to the comma character may be
corrupted by the realignment process. The second K28.5 shows the case when a comma is detected and no
phase adjustment is necessary. It illustrates the position of the SYNi pulse in relation to the comma character on
RXi[0:9].

Figure 2: Misaligned and Aligned K28.5 Characters

RCi0

(RCM LOW)

RCi1

RCi0

([RCM HIGH)

RCi1

SYNi

RXi[0:9]

Page 4 G52307-0, Rev 2.2

© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012

Corrupt Corrupt Corrupt

Misaligned Comma: Stretched

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K28.5

Data1 Data2 Data3

K28.5Data

Aligned Comma

10/10/00

VITESSE

®

Quad Transceiver

SEMICONDUCTOR CORPORATION

Advance Product Information

for Gigabit Ethernet and Fibre Channel

Loopback Operation

Loopback operation is controlled by the PLUP (Parallel Loopback), SLPN (Serial Loopback) and LPNi
inputs as shown in Table 2. LPNi enables PLUP/SLPN on a per-channel basis when LOW. If LPNi is HIGH,
PLUP/SLPN have no impact on Channel x. When SLPN and PLUP are both HIGH the transmitter output is
held HIGH. When RXx is looped back to TXx, the data goes through a clock recovery unit so much of the
input jitter is removed. However, the TXx outputs may not meet jitter specifications listed in the “Transmitter
AC Specifications” due to low frequency jitter transfer from RXx to TXx.

Table 2: Loopback Selection

LPNi PLUP SLPN Tranmitter Source Receiver Source

LOW LOW LOW Receiver Receiver
LOW LOW HIGH Transmitter Receiver
LOW HIGH LOW Transmitter Transmitter
LOW HIGH HIGH HIGH Transmitter

HIGH X X Transmitter Receiver

JTAG Access Port

A JTAG Access Port is provided to assist in board-level testing. Through this port most pins can be
accessed or controlled and all TTL outputs can be tri-stated. A full description of the JTAG functions on this
device is available in “VSC7182 JTAG Access Port Functionality.”

G52307-0, Rev 2.2 Page 5
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Internet: www.vitesse.com

VITESSE

®

VSC7182

SEMICONDUCTOR CORPORATION

Quad Transceiver
for Gigabit Ethernet and Fibre Channel

AC Characteristics

Figure 3: Transmit Timing Waveforms

RFC

TCi

TXi[0:9]

10-Bit Data

+/-TXi

RFC
TCi

Data Valid

T

1

Data Valid

T

RLAT

T

TLAT

Advance Product Information

T

2

Data Valid

TXi0 TXi1 TXi2

Table 3: Transmitter AC Characteristics

Parameter Description Min Typ Max Units Conditions

T

1

T

2

T

SDR,TSDF

T

RLAT

T

TLAT

RJ Random jitter (rms) — 5 8 ps

DJ

TXi[0:9] setup time to the rising edge
of TCi or RFC

TXi[0:9] hold time after the rising
edge of TCi or RFC

TXi+/TXi- rise and fall time — — 300 ps

Latency from rising edge of RFC to
TXi0 appearing on TX+/TX-

Latency from rising edge of TCi to
TXi0 appearing on TX+/TX-

Transmitter Output Jitter

Serial data output deterministic jitter
(pk-pk)

1.5 — — ns

1.0 — — ns

7bc +

0.66ns
5bc +

0.66ns

— 35 80 ps

—

—

7bc +

1.46ns
11bc

+

1.46ns

Measured between the valid
data level of TXi[0:9] to the

1.4V point of TCi or RFC

20% to 80%, 75Ω load to
VDD/2, tested on a sample
basis

bc = bit clocks
ns = nanoseconds

bc = bit clocks

ns

ns = nanoseconds

Measured at SO+/-, 1 sigma
deviation of 50% crossing
point

IEEE 802.3Z Clause 38.68,
tested on a sample basis

Page 6 G52307-0, Rev 2.2

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®

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Advance Product Information

Figure 4: Receive Timing Waveforms

RCi0

(RCM=LOW)

RCi1

RCi0

(RCM=HIGH)

RCi1

RXi[0:9]

T

1

VALID VALID

for Gigabit Ethernet and Fibre Channel

T

2

VALID

SYNi

+/-RXi

RXi0 RXi1 RXi2

R

LAT

RCi1

Table 4: Receive Timing Waveforms

Parameters Description Min Typ Max Units Conditions

T

T

T

T

TR, T

R

LAT

T

LOCK

4.0

TTL outputs valid prior to RCi1/RCi0 rise

1

3.0

TBD

3.0

TTL outputs valid after RCi1 or RCi0 rise

2

2.0

TBD

Delay between rising edge of RCi1 to

3

rising edge of RCi0
Period of RCi1 and RCi0

4

TTL Output rise and fall time — 2.4 ns

F

Latency from serial bit RXi0 to rising edge
RCi1

Data acquisition lock time

(1)

10 x T

RX

-500

1.98 x
T

RFC

12bc +

2.77ns
— 1400

—
—
—

—
—
—

10 x T

+500

2.02 x
T

RFC

13bc +

7.28ns

RX

At 1.0625Gb/s

ns

At 1.25Gb/s
At 1.36Gb/s

At 1.0625Gb/s

ns

At 1.25Gb/s
At 1.36Gb/s

TRX is the bit period of the

ps

incoming data on RXi.
Whether or not locked to

ps

serial data.
Between V

V

IH(MIN)

bc = bit clock
ns = nanosecond

bit

8B/10B IDLE pattern.

times

Tested on a sample basis.

IL(MAX)

, into 10 pf load.

and

NOTE: (1) Probability of recovery for data acquisition is 95% per Section 5.3 of FC-PH rev. 4.3.

G52307-0, Rev 2.2 Page 7
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®

VSC7182

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Quad Transceiver

Advance Product Information

for Gigabit Ethernet and Fibre Channel

Figure 5: RFC and TCi Waveforms

T

L

RFC

TCi

RFCO0
RFCO1

T

P

Table 5: Reference Clock Requirements

Parameters Description Min Typ Max Units Conditions

FR Frequency range 105 136 MHz

FO Frequency offset -200 200 ppm

T

P

DC RFC0/1 duty cycle 40 60 %

TR, T

DC RFC/TCi duty cycle 35 65 % Measured at 1.4V

T

RCR,TRCF

Delay from RFC to RFCO0/1 1.97 3.58 ns

RCF0/1 rise and fall time 0.25 1.5 ns Between V

F

RFC/TCi rise and fall time — 1.5 ns Between V

T

H

V

V

Range over which both transmit
and receive reference clocks on
any link may be centered.

Maximum frequency offset
between transmit and receive
reference clocks on one link.

IH(MIN)

IL(MAX)

IL(MAX)

IL(MAX)

and V

and V

IH(MIN)

IH(MIN)

Page 8 G52307-0, Rev 2.2

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Advance Product Information

for Gigabit Ethernet and Fibre Channel

DC Characteristics

Parameters Description Min. Typ Max. Units Conditions

TTL Outputs

V

OH

V

OL

I

OZ

TTL Inputs

V

IH

V

IL

I

IH

I

IL

PECL Input (RFC+/RFC-)

V

IH

V

IL

I

IH

I

IL

∆V

IN

High Speed Outputs

∆V

OUT75

∆V

OUT50

High-Speed Inputs

(1)

∆V

IN

Miscellaneous

V

DD

P

D

I

DD

I

DDA

TTL output HIGH voltage 2.4 — — V I
TTL output LOW voltage — — 0.5 V I

TTL output Leakage current — — 50 µA

= -1.0mA

OH

= +1.0mA

OL

When set to high-impedance
state through JTAG.

TTL input HIGH voltage 2.0 — 5.5 V 5V tolerant inputs
TTL input LOW voltage 0 — 0.8 V
TTL input HIGH current — 50 500 µA V
TTL input LOW current — — -500 µA V

PECL input HIGH voltage

PECL input LOW voltage

-

DD

1.1

V

-

DD

2.0

—

—

V

-

DD

0.7

V

-

DD

1.5

V

PECL input HIGH current — — 200 µA V
PECL input LOW current - 50 — — µA V
PECL input differential peak-to-

peak voltage swing

TX output differential peak-

(1)

to-peak voltage swing
TX output differential peak-

(1)

to-peak voltage swing

PECL differential peak-to-peak
input voltage swing

400 — — mV V

1200 — 2200

1000 — 2200

200 — 2600 mV SI+ - SI-

V

V

mVp-

p

mVp-

p

IN
IN

IN
IN

IH(MIN)

75Ω to VDD – 2.0 V
(TX+) - (TX-)

50Ω to VDD – 2.0 V
(TX+) - (TX-)

Power supply voltage 3.14 — 3.47 V 3.3V + 5%
Power dissipation — 2.2 2.67 W Maximum at 3.47V, outputs

Supply current (all supplies) — — 770 mA
Supply current on V

DDA

— 100 — mA

open, 25oC, 136MHz Clk,
PRBS 27-1 parallel input pattern

= 2.4V
= 0.5V

= V

IH(MAX)

= V

IL(MIN)

- V

IL(MAX)

NOTE: (1) Refer to Application Note, AN-37, for differential measurement techniques.

G52307-0, Rev 2.2 Page 9
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Quad Transceiver

Advance Product Information

for Gigabit Ethernet and Fibre Channel

Absolute Maximum Ratings

Power Supply Voltage, (VDD)............................................................................................................-0.5V to +4V

DC Input Voltage (PECL inputs) ........................................................................................... -0.5V to VDD +0.5V

DC Input Voltage (TTL inputs)......................................................................................................... -0.5V to 5.5V

DC Output Voltage (TTL outputs)........................................................................................ -0.5V to VDD + 0.5V

Output Current (TTL outputs).................................................................................................................... +50mA

Output Current (PECL outputs)...................................................................................................................+50mA

Case Temperature Under Bias...................................................................................................... -55oC to +125oC

Storage Temperature ....................................................................................................................-65oC to +150oC

Maximum Input ESD (human body model).................................................................................................2000V

NOTE: (1) CAUTION: Stresses listed under “Absolute Maximum Ratings” may be applied to devices one at a time without caus-

ing permanent damage. Functionality at or above the values listed is not implied. Exposure to these values for extended
periods may affect device reliability.

(1)

Recommended Operating Conditions

Power Supply Voltage, (VDD)................................................................................................................+3.3V+5%

Operating Temperature Range .......................................................... 0oC Ambient to +100oC Case Temperature

Page 10 G52307-0, Rev 2.2

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Advance Product Information

Table 6: Pin Table

RD0

RD4

17

VSST

RCD1

16

VDDT

VSST

RCD0

RD6

RD3

RD5

for Gigabit Ethernet and Fibre Channel

TC3

VSS

VDDT

TC0

RD9

TC7

TC4

TC8

TD0

TD4

TCC

TD1

VDD

TD8

TCD

SYNC

TD5

TD9

RFCO0

VDDTR

VSS

TCK

VSS

VSSTR

TC1

TC5

TC9

VSS

TD2

15

VSST

SYNCD

RC8

14

13

12

11

10

9

8

RC9

RC5

VDDT

RC1

RC2

RC0

VSST

VDD

SYNCC

VSS

VDDT

RB6

RB7

RD2

VDDT

RD1

VDD

RC6

RC7

RC3

RC4

VSST

VDDT

RCC0

RCC1

TMS

SLPN

RB8

RB9

RD8

VSST

TC2

RD7

VDDT

TC6

VSS

VDD

TD6

TD3

TD7

NOT POPULATED

7

RB4

VDDT

6

RB0

RB1

5

RCB0

RCB1

RB5

VSST

RB2

RB3

LPND

VDDT

TDI

VDD

PLUP

RFCO1

TD+

VSS

TC+

VSS

CAP0

VSS

TB-

VSS

TA-

VSS

TRSTN

VDD

TD-

VSS

TC-

VSS

CAP1

VSSA

TB+

VSS

TA+

VSS

RD+

VDD

RD-

VDDPD

VSS

VSS

RC+

VDDPC

RC-

VSS

VSS

VDDA

VSS

VSS

RB+

VDDPB

RB-

VSS

VDD

VDDPA

4

3

2

1

G52307-0, Rev 2.2 Page 11

VSST

SYNCB

RA9

VSST

RA8

VDD

RA7

VSST

B

A

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10/10/00

TB7

RA3

VSST

VDDT

RA6

RA5

RA4

C

RA2

VDDT

RA1

RCA1

RA0

RCA0

E

D

VDD

VSST

VSS

VDDT

TB9

SYNCA

TB8

TCB

F

G

TB3

LPNC

TB6

TB2

VSS

TB5

TB1

TDO

TB4

TB0

TCA

J

H

K

TA7

TA6

TA5

TA4

M

TA3

TA2

TA1

TA0

N

VDD

VSS

TA9

TA8

L

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VDD

LPNB

RFC-

LPNA

RFC+

RFCM

RFCT

LTCN

P

R

RA+

VDD

RA-

VDD

VSS

VSS

VSS

RCM

T

U

VITESSE

®

VSC7182

SEMICONDUCTOR CORPORATION

Quad Transceiver
for Gigabit Ethernet and Fibre Channel

Table 7: Pin Descriptions

Pin Name Description

N1, N2, N3

N4, M1, M2,

M3, M4, L1

L2

J1, J2, J3

J4, H1, H2

H3, H4, G1

G2

G16, G15, G14
H17, H16, H15

H14, J17, J16

J15

L17, L16, L15
L14, M17, M16
M15, M14, N17

N16

R2

P3

R1 RFCT

P2 RFCM

P16
P14

K1, F1

K17, P17

P1 LTCN

TA0, TA1, TA2
TA3, TA4, TA5
TA6, TA7, TA8

TA9

TB0, TB1, TB2
TB3, TB4, TB5
TB6, TB7, TB8

TB9

TC0, TC1, TC2
TC3, TC4, TC5
TC6, TC7, TC8

TC9

TD0, TD1, TD2
TD3, TD4, TD5
TD6, TD7, TD8

TD9

RFC+

RFC-

RFCO0
RFCO1

TCA, TCB
TCC, TCD

INPUT - TTL: 10-Bit Transmit Bus for Channel A. Parallel data on this bus is latched
on the rising edge of RFC, TCC or TCA. TA0 is transmitted first.

INPUT - TTL: 10-Bit Transmit Bus for Channel B. Parallel data on this bus is latched
on the rising edge of RFC, TCC or TCB. TB0 is transmitted first.

INPUT - TTL: 10-Bit Transmit Bus for Channel C. Parallel data on this bus is latched
on the rising edge of RFC or TCC. TC0 is transmitted first.

INPUT - TTL: 10-Bit Transmit Bus for Channel D. Parallel data on this bus is latched
on the rising edge of RFC, TCC or TCD. TD0 is transmitted first.

INPUT - Differential PECL or TTL: This rising edge of RFC+/- provides the reference
clock, at 1/10th or 1/20th of the baud rate (depending on RFCM) to the Clock
Multiplying PLL. If RFC+/- is used, either leave RFCT open or set RFCT HIGH.
Internally biased to VDD/2. If all TCi inputs are HIGH, the rising edge of RFC will
latch TXi[0:9] on all four channels.

INPUT - TTL: TTL Reference Clock. This rising edge of RFCT provides the
reference clock, at 1/10th or 1/20th of the baud rate (depending on RFCM) to the Clock
Multiplying PLL. If RFCT is used, set RFC+ HIGH and leave RFC- open. If all TCi
inputs are HIGH, the rising edge of RFCT will latch TXi[0:9] on all four channels

INPUT - TTL: Reference Clock Mode Select. When LOW, RFC is at 1/20th of the
transmit baud rate (i.e., 62.5MHz for 1.25Gb/s). When HIGH, RFC is at
1/10th the baud rate (i.e., 125MHz for 1.25Gb/s).

OUTPUT - TTL: These are identical copies of the transmit baud rate clock divided by

10.
INPUT - TTL: Per Channel Transmit Byte Clock for Channel x. All four channels’

parallel TXi[0:9] inputs may be timed to RFC, TCC, or independently to TCi. Refer to
the Serializer description.

INPUT - TTL: Latch Transmit Byte Clocks. When LOW, internal PLLs align clocks
with each of the transmit byte clocks, if present. Data may be corrupted when LOW.
When HIGH, alignment will remain static regardless of actual TCi location.

Advance Product Information

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®

Quad Transceiver

SEMICONDUCTOR CORPORATION

Advance Product Information

Pin Name Description

for Gigabit Ethernet and Fibre Channel

R5, P5

R7, P7
P11, R11
P13, R13

D1, D2, E3

E4, C1, C2
C3, B1, B2

B3

A6, B6, C6
D6, A7, D7
A8, B8, C8

D8

B11, A12, B12
C12, D12, B13
C13, D13, A14

B14

C17, D14, D15
D16, D17, E16

E17, F14, F15

F16

T1 RCM

E1
E2

A5

B5

C10

D10

B16
B17

U4, U3

U7, U6
U11, U10
U14, U13

TA+, TA­TB+, TB­TC+, TC­TD+, TD-

RA0, RA1, RA2
RA3, RA4, RA5
RA6, RA7, RA8

RA9

RB0, RB1, RB2
RB3, RB4, RB5
RB6, RB7, RB8

RB9

RC0, RC1, RC2
RC3, RC4, RC5
RC6, RC7, RC8

RC9

RD0, RD1, RD2
RD3, RD4, RD5
RD6, RD7, RD8

RD9

RCA0
RCA1

RCB0
RCB1

RCC0
RCC1

RCD0
RCD1

RA+, RA­RB+, RB­RC+, RC­RD+, RD-

OUTPUT - Differential PECL (AC-coupling recommended):
These pins output the serialized transmit data for Channel x when PLUP is LOW.
When PLUP is HIGH, TXi+ is HIGH and TXi- is LOW.

OUTPUT - TTL: 10-Bit Receive Bus for Channel A. Parallel data on this bus is
synchronous to RCA0 and RCA1. RA0 is the first bit received.

OUTPUT - TTL: 10-Bit Receive Bus for Channel B. Parallel data on this bus is
synchronous to RCB0 and RCB1. RB0 is the first bit received.

OUTPUT - TTL: 10-Bit Receive Bus for Channel C. Parallel data on this bus is
synchronous to RCC0 and RCC1. RC0 is the first bit received.

OUTPUT - TTL: 10-Bit Receive Bus for Channel D. Parallel data on this bus is
synchronous to RCD0 and RCD1. RD0 is the first bit received.

INPUT - TTL: Recovered Clock MODE Control. When LOW, RCi0/RCi1 is 1/20th of
the incoming baud rate. When HIGH, RCi0/RCi1 is 1/10th the incoming baud rate.

OUTPUT - Complementary TTL: Recovered Complementary Clocks for Channel A
at 1/10th the Incoming Baud Rate (RCM=HIGH) or 1/20th (RCM=LOW).
Synchronous to the RA(0:9) and SYNCA bus.

OUTPUT - Complementary TTL: Recovered Complementary Clocks for Channel B at
1/10th the Incoming Baud Rate (RCM=HIGH) or 1/20th (RCM=LOW). Synchronous
to the RB(0:9) and SYNCB bus.

OUTPUT - Complementary TTL: Recovered Complementary Clocks for Channel C at
1/10th the Incoming Baud Rate (RCM=HIGH) or 1/20th (RCM=LOW). Synchronous
to the RC(0:9) and SYNCC bus.

OUTPUT - Complementary TTL: Recovered Complementary Clocks for Channel D
at 1/10th the Incoming Baud Rate (RCM=HIGH) or 1/20th (RCM=LOW).
Synchronous to the RD(0:9) and SYNCD bus.

INPUT - Differential PECL (AC-coupling recommended): Serial Receive Data Inputs
for Channel x. These are selected when PLUP is LOW (internally biased to VDD/2).

G52307-0, Rev 2.2 Page 13
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®

VSC7182

SEMICONDUCTOR CORPORATION

Quad Transceiver
for Gigabit Ethernet and Fibre Channel

Pin Name Description

INPUT - TTL: Parallel Loopback Enable Input. RXi is input to the CRU for Channel x

N14 PLUP

C9 SLPN

R3

P4
K4
D5

R17 SYNC

F2
A4

B10
B15

P9

R9

T17 TCK INPUT - TTL: JTAG Test Clock

D9 TMS INPUT - TTL: JTAG Test Mode Select

R15 TRSTN INPUT - TTL: JTAG Test Reset, Active LOW
P15 TDI INPUT - TTL: JTAG Test Data Input

K2 TDO OUTPUT - TTL: JTAG Test Data Output

T9 VDDA Analog Power Supply

R8 VSSA Analog Ground. Tie to common ground plane with VSS.

A2,A10,C14

G4,J14,K16

L4,N15,R4

R14,T3

T4,T14,U5

C4, D3,F3

A9, B7, C5
A13, A16, C11
C15, E14, G17

T5

T7
T11
T13

LPNA
LPNB
LPNC
LPND

SYNCA
SYNCB
SYNCC
SYNCD

CAP0
CAP1

VDD Digital Logic Power Supply

VDDT TTL Output Power Supply

VDDPA
VDDPB
VDDPC
VDDPD

(normal operation) when PLUP is LOW. When HIGH, internal loopback paths from
TXi to RXi are enabled. Refer to Table 2.

INPUT - TTL: Serial Loopback Enable Input. Normal operation when HIGH. When
LOW, SI+/- is looped back to TXi+/- internally for diagnostic purposes. Refer to Table
2 and related description.

INPUT - TTL: Loopback Enable Pins. When LPNi is LOW, PLUP/SLPN impact
Channel x. When HIGH, PLUP/SLPN have no effect on Channel x.

INPUT - TTL: Enables SYNi and Word Alignment when HIGH. When LOW, keeps
current word alignment and disables SYNi (always LOW).

OUTPUT - TTL: Comma Detect for Channel x. This output goes HIGH for half of an
RCi1 period to indicate that RXi[0:9] contains a “comma” character
(‘0011111XXX’). SYNi will go HIGH only during a cycle when RCi0 is rising. SYNi
is enabled when SYNC is HIGH.

ANALOG: Loop Filter capacitor for the Clock Multiply Unit. Typically 0.1µF
connected between CAP0 and CAP1. Amplitude is less than 3.3V.

PECL I/O Power Supply for Channel x.

Advance Product Information

Page 14 G52307-0, Rev 2.2

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®

Quad Transceiver

SEMICONDUCTOR CORPORATION

Advance Product Information

Pin Name Description

R16 VDDTR TTL Output Power Supply for RFCO0 and RFCO1.
T16 VSSTR TTL Ground for RFCO0 and RFCO1.

A1,A3,A11,A15

A17,B4,C7

C16,D4,D11

E15,F4

B9,F17,G3,K3,

K14,K15,L3,P6,

P8,P10,P12

R6,R10,R12,T2

T6,T8,T10,T12

T15,U1,U2,U8,

U9,U12,U15

U16, U17

VSST Ground for TTL Outputs

VSS

Ground

for Gigabit Ethernet and Fibre Channel

G52307-0, Rev 2.2 Page 15
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VITESSE

®

VSC7182

SEMICONDUCTOR CORPORATION

Quad Transceiver

Advance Product Information

for Gigabit Ethernet and Fibre Channel

Package Thermal Characteristics

The VSC7182 is packaged in a 23mm BGA package with 1.27mm eutectic ball spacing. The construction

of the package is shown in Figure 6.

Figure 6: Package Cross Section

Copper Heat Spreader

Adhesive

Polyimide Dielectric

Die Attach Epoxy

Encapsulant Eutectic Solder Balls

The VSC7182 is designed to operate with a case temperature up to 100oC. In order to comply with this tar­get, the user must guarantee that the case temperature specification of 100oC is not violated. With the thermal
resistances shown in Table 8, the VSC7182 can operate in still air ambient temperatures of 40oC [40oC =
100oC - 2.5W * 24oC/W]. If the ambient air temperature exceeds these limits, some form of cooling through a
heatsink or an increase in airflow must be provided.

Die

Wirebond

Table 8: Thermal Resistance

Symbol Description Value Units

θ

jc

θ

ca

θ

ca-100

θ

ca-200

θ

ca-400

θ

ca-600

Thermal resistance from junction-to-case 4.3
Thermal resistance from case-to-ambient in still air including conduction

through the leads.
Thermal resistance from case-to-ambient with 100 LFM airflow 21

Thermal resistance from case-to-ambient with200 LFM airflow 18.5
Thermal resistance from case-to-ambient with 400 LFM airflow 17
Thermal resistance from case-to-ambient with 600 LFM airflow 15

24

Moisture Sensitivity Level

This device is rated at with a Moisture Sensitivity Level 3 rating. Refer to Application Note AN-20 for
appropriate handling procedures.

o

C/W

o

C/W

o

C/W

o

C/W

o

C/W

o

C/W

Page 16 G52307-0, Rev 2.2

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VITESSE

®

Quad Transceiver

SEMICONDUCTOR CORPORATION

Advance Product Information

Package Information

for Gigabit Ethernet and Fibre Channel

1.27 Typ

1.55 Typ

1716151413121110987654321

23.0

BOTTOM VIEW

Pin A1 Indicator

A
B
C
D
E
F
G
H
J

23.0

K
L
M
N
P
R
T
U

TOP VIEW

G52307-0, Rev 2.2 Page 17
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Internet: www.vitesse.com

VITESSE

®

VSC7182

SEMICONDUCTOR CORPORATION

Quad Transceiver
for Gigabit Ethernet and Fibre Channel

Ordering Information

The order number for this product is formed by a combination of the device type and package type.

VSC7182

Device Type

Quad Gigabit Transceiver

Advance Product Information

TW

Package

TW: 208-Pin, 23mm BGA

Notice

This document contains information about a new product during its fabrication or early sampling phase of development. The
information in this document is based on design targets, simulation results or early prototype test results. Characteristic data and
other specifications are subject to change without notice. Therefore the reader is cautioned to confirm that this data sheet is current
prior to design or order placement.

Warning

Vitesse Semiconductor Corporation’s products are not intended for use in life support appliances, devices or systems. Use of
a Vitesse product in such applications without written consent is prohibited.

Page 18 G52307-0, Rev 2.2

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10/10/00