Datasheet VSC6511RC Datasheet (VITESSE)

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A

V

SEMICONDUCTOR CORPORATION

dvance Product Information

SC6511

SMPTE-292M Serializer, Deserializer, and

Deserializer/Reclocker at 1.485Gb/s

Features

• Compliant with SMPTE-292M @ 1.485Gb/s

• Multiple Functions: Serializer, Deserializer,
and Deserializer with Reclocker

• 20 Bit TTL Interface @ 74.25 MHz

• Scrambler / Descrambler with ENABLE

• CRC Generator/Checker with ENABLE

• Data Framer aligns data and provides TRS on
SAV/EAV events

• Clock Multiplier and Recovery Units

• 2 or 4 configurable 75ohm cable driver o/ps

• 3.3V , Low power -- 700-1500mW typical

• 64-pin, 10x10x1.0mm Exposed Pad TQFP

General Description

The VSC6511 multi function SMPTE-292M compatible IC with Serializer, Deserializeror, or Deserializer
with reclocker modes which operate at 1.485Gb/s. As a Serializer, 20-bits of data (D19:0) are latched into the
part on the rising edge of REFCLK the n scrambled and serialize d out SDO0/SDO 0
optional CRC Generator may be enabled. As a Deserializer, serial data on SDI/SDI
and deserialized onto D[19:0]. Frame align ment on SAV/EAV, line detection and frame dete ction outputs are
provided. As a Deserializer with reclocker, the device functions as ain the deserializer mode above and serial
data on SDI/SDI

is recovered and retransmitted on SDO0/SDO0 and/or SDO1/SDO1.

and/or SDO1/SDO1. An

is recovered, de-scrambled

VSC6511 Block Diagram

OE0

SDO0

Draft Copy

D[19:0]

SCREN

CRC

IP
IN

MODE0
MODE1

REFCLK

74.25 MHz

D Q

Clock/

Recovery

Unit

Clock

Multiply

x20

CRC Gen

1.485 GHz

1.485 GHz

/20

/20

NRZI Decoder

Descrambler

SerializerScrambler

Framer

CABLE DRIVER

CRC CheckDeserializer

D Q

SDO0

ISET0
OE1

SDO1
SDO1

ISET1

OUTPUTS

SIGDET

1001
LINE

FRAME
HANC

RCLK

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Page 1

VITESSE

SEMICONDUCTOR CORPORATION

SMPTE-292M Serializer, Deserializer, and

Deserializer/Reclocker at 1.485Gb/s

Functional Description

The VSC6511 is a multifunction SMPTE-292M device which can be configured for different modes of
operation: Serializer , Deseri alizer, or Deserializer/Reclocker. Only one mode is available at a time. A discussion
of the individual building blocks of the device will be followed with specific configurations.

Clock Multiplier Unit (CMU)

The CMU generates the internal 1.485 GHz baud rate clock from the 74.25 MHz TTL REFCLK input. The
rising edges of the REFCLK are used by a PLL which multiplies the frequency by a factor of 20. This internal
baud rate clock is used by the Serializer, D eserializer and Reclocker. An off-chip 0.1uF capacitor sets the loop
bandwidth of the CMU. REFCLK should be a high quali ty, low jitter signal with sharp rise times in order to
minimize the amount of jitter transferred from the REFCLK through the CMU to the serializer. This optimizes
the signal quality at the output of the serializer.

A secondary function of the CMU is to divide the baud rate clock by 20 to produce an internal 74.25 MHz
clock which is frequency locked and phase aligned to REFCLK. This internal clock is used to latch the 20-bit
data bus D[19:0] into the input r egister o f the Serializer.

REFCLK is also buffered onto the RCLK output when in Serializer or Reclocker mode. This allows multi­ple devices to be daisy-chained in order to simplify REFCLK distribution to an array of devices.

CRC Generator

The twenty bits of transmit data from the input register is fed into a CRC Generator which calculates the
CRC and substitutes the value into the proper location within the video line. The CRC polynomial is CRC(X)=

18

+ X5 + X4 + 1). A controller monitors SAV/EAV position and uses this to control the CRC generator and

(X
insertion of the CRC result into the line. The CRC Generator is enabled only in Serializer Mode when CRC is

Draft Copy

HIGH. In other modes, or if CRC is LOW, the CRC Generator is disabled and powered down. CRC is a bidi­rectional pin.

Advance Product Information

VSC6511

Scrambler and NRZI Encoder

The twenty bits out of the CRC Generator are sent to the parallel Scrambler where the data is scrambled and
NRZI encoded using the combined generator polynomial of G(x)=(x
only when in Serializer Mode if SCREN is HIGH. Scrambling is disabled when SCREN is LOW and in other
modes.

Serializer

The data from the Scrambler is converted from 20-bits at 74.25 Mb/s t o 1 bit at 1.4 85 Gb/ s b y the S eria lizer
with D0 being transmitted first. Two differential PECL-style serial outputs are provided for transporting the

1.485 Gb/s signal. These out puts SDO0/ SDO0
izer mode) or the CRU of the Reclocker (in Deserializer/Reclocker mode). Each output, SDO0 and SDO1,
have independent TTL inputs, OE0 and OE1, which when HIGH enabl e the outputs and when LO W disab le t he
outputs. When disabled, the output buffer will be powered down and both legs will float HIGH.

Each output is compliant with the SMPTE-292M cable driver specification when driving 75 ohm loads. In
this application, a TBD ohm resistor should be connected from the ISET0/ISET1 pin to ground in order to con­trol the current in the differential output amplifier. By low ering the ISET resistor, higher output swings may be
realized.

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and SDO1/SDO1 are supplied data fro m th e seriali zer (i n S eria l-

9

+ x4 +1)(x+1). Scrambling is enabled

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dvance Product Information

SC6511

Serial Input

The differential PECL-style input, SDI/SDI, is the input source for 1.485 Gb/s SMPTE-292M data in the
Deserializer and Reclocker modes. This input is ignored in Serializer mode.

Clock Recovery Unit

The serial data on the SDI/SDI inpu t is sent to the digital Clock Re covery Unit (CRU) which extracts the
clock and retimes the data. This digital CRU is completely m onolithic an d requires no external comp onents.
Furthermore, it automatically l ocks onto d ata when p resent and lo cks to REFCLK when data i s not presen t. This
eliminates the need for the system to control the CRU. The CRU is enabled only in the Deserializer and Deseri­alizer/Reclocker modes.

Deserializer

The reclocked serial bit stream is deserialized into a 20-bit parallel charact er. D0 is serially receiv ed prio r to
D1. The VSC6511 provides a TTL recovered clock, RCLK at one t went ieth of t he serial b aud rate. This clock is
generated by dividing down the high-speed clock from the CRU which is phase locked to the serial data. The
deserializer is enabled only in the Deserializer and Deserializer/Reclocker modes.

If serial input data is not present, or do es not m eet the required baud rate, the VSC6511 will continue to
produce a recovered clock so that downstream logic may continue to function. The RCLK output frequency
under these circumstances will differ from their expected frequency by less than +

SMPTE-292M Serializer, Deserializer, and

Deserializer/Reclocker at 1.485Gb/s

1%.

Descrambler and NRZI Decoder

The VSC7152 contains a descrambler/NRZI Decoder wh ich processes the r ecovered serial data and out­puts unscrambled and NRZI decod ed serial data from th e deserializ er. The serial scrambled data is descrambled/
NRZI decoded assuming data has been scrambled/NRZI encoded with the following combined generator poly-

Draft Copy

nomial: G(x)=(x
LOW. The descrambler is enabled only in the Deserializer mode.

CRC Checker

The 20-bit data from the Descrambler is sent to the CRC Checker where a running CRC checksum is con­tinuously calculated. As 20-bit data is sent out of the chip, the CRC output pin is asserted if the checksum did
not meet the val ue expect ed. This error is asse rted from the f i rst CRC Error until the end of the li ne. A controll er
monitors the 20-bit da ta out of the se rializer for S AV/EAV frames in order to control t he CRC Checker. The
CRC Checker is enabled only in Deserializer and Deserializer/Reclocker modes.

Frame Aligner

The VSC6511 monitors the serial data stream for SAV/EAV characters. These characters should be located
within each line of video data. If SAV/EAV is not det ected wi th in t he pe riod of one line, the Framer sends a sig­nal to the Deserializer to shift the data o ne bit. The Fram er then lo oks for SAV/EAV and the process repea ts
until properly detected. Without these patterns, serial data is not aligned in any way with the parallel outputs.
The Framer outputs a once-per-li ne (LINE) , Horizo nt al ANCill iary period (HANC), 1.001/ 1. 000 ou tpu t (1.0 01)
and a once-per-frame (FRAME) signal indicating the detection of the proper synchronization pulse in the data.
Framing is enabled only in Deserializer mode.

The Frame Aligner also outputs the L INE, FR AME an d HANC output s si gnals . Th e ti mi ng of t hese si gnals
is indicated below.

9+x4

+1)(x+1). Descram bling is en abled with t he SCREN input is HI GH and di sabled w hen

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SMPTE-292M Serializer, Deserializer, and

Deserializer/Reclocker at 1.485Gb/s

Table 1: Frame Aligner Output Timing

D10-19 D0-9 LINE FRAME HANC CRCERR

DATA DAT A 0 0 0 0

--- --- 0 0 0 0

VIDEO

ACTIVE

EAV

LINE

CRC

HORIZ

BLANK

SAV

Draft Copy

VIDEO

ACTIVE

DATA DAT A 0 0 0 0

3FF3FF0000
0000000000
0000000000

XYZ XYZ 0 0 0 0

LN0LN00000
LN1LN111*0 0

CRC0 CRC0 0 0 0 0
CRC1 CRC1 0 0 0 0 or 1
DATA DAT A 0 0 1 0

--- --- 0 0 1 0

DATA DAT A 0 0 1 0

3FF3FF0000
0000000000
0000000000

XYZ XYZ 0 0 0 0
DATA DAT A 0 0 0 0
DATA DAT A 0 0 0 0

--- --- 0 0 0 0
* FRAME is HIGH only if LN0/LN1 indicates the first line of a frame.

** CRCERR is HIGH only during CRC1 if the CRC is incorrect.

Advance Product Information

VSC6511

D[19:0] Databus

As mentioned previously, in Serializer mode D[19:0] is configured as a input. In Deserializer mode,

D[19:0] is configured as an output.

Application Information

The VSC6511 cable driver output is intended to fully comply with the SMPTE-292M cable driver specifi­cations. This includes an 800mV swing and a return loss of more than 15dB. The circuit shown below shows
how to connect the output of the VSC6511 to the 75 ohm ca ble and downstream device. The output of the
VSC6511 is actually 120 0mV. The ou tput termination circuit shown below attenuates the ou tput signal to
800mV and ensures a return loss better than -15dB. The ISET resistor is 1 .78K

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dvance Product Information

SC6511

Figure 1: High Speed Interconnect Example (Differential)

6511

1.78K
ISETx

V

SS

SMPTE-292M Serializer, Deserializer, and

Deserializer/Reclocker at 1.485Gb/s

V

DD

75

10nH

75

75 ohm Cables

75

10nH

75

V

DD

NOTE: All resistors are 1%
WARNING: SUBJECT TO CHANGE

Figure 2: High Speed Interconnect Example (Single Ended)

Draft Copy

6511

1.78K
ISETx

V

SS

NOTE: All resistors are 1%
Optional use of external Voltage Reference provides tighter swing tolerance

V

DD

75

10nH

75

75 ohm Coax

75

10nH

75

V

DD

75

V

DD

or

37.5

V

DD

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SMPTE-292M Serializer, Deserializer, and

Deserializer/Reclocker at 1.485Gb/s

The output swing of the VSC6511 is controlled through the ISETx pins and a VREF input. By connecting
an 1.78K ohm resistor, 1%, between VSS and ISETx the output swing will be controlled to within 800mV +/­7%. An optional bandpass v ol tage refer ence may be used to furth er tigh ten t he out put swings by accurately driv­ing the VREF input.

Configuration Modes:

The MODE(1:0) inputs configure the VSC6511 into its different modes of operation. The table below sum­marizes the different signals and circuits in the VSC6511 that change function in the different modes.

Table 2: Mode Configuration Features: Serializer Mode

SIGNAL/CIRCUIT

MODE1
MODE0

D[19:0] Data Bus 20-BIT OUTPUT 20-BIT OUTPUT 20-BIT INPUT

SDO0/SDO1 Serial Outputs NOT USED, DISABLED

RCLK Output

CRU Bypass Mux NOT ACTIVE

SDI Serial Input ACTIVE ACTIVE IGNORED

Draft Copy

CRC CRC is an error output CRC is an error output Enables CRC Generator

SIGDET Output ACTIVE AC TIVE DISABLED LOW

1.001 Output ACTIVE ACTIVE DISABLED LOW

FRAME Output ACTIVE ACTIVE DISABLED LOW

LINE Output ACTIVE ACTIVE DISABLED LOW

HANC Output ACTIVE ACTIVE DIS ABLED LOW

RECOVERED CLOCK

DESERIALIZER

MODE

HIGH
HIGH

FROM CRU

Advance Product Information

VSC6511

DESERIALIZER/

RECLOCKER MODE

LOW

HIGH

SOURCE IS CRU

OUTPUT OR SDI/SDI

RECOVERED CLOCK

FROM CRU

CRU OUTPUT GOES

TO SDO0/SDO1

SERIALIZER

MODE

LOW
LOW

SOURCE IS

SERIALIZER

BUFFERED REFCLK

CRU NOT ACTIVE

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G52311-0, Rev 2.0

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dvance Product Information

SC6511

SMPTE-292M Serializer, Deserializer, and

Deserializer/Reclocker at 1.485Gb/s

Features: Serializer Mode

1. 20 Bit TTL Interface @ 74.25 MHz

2. On-chip Clock Multiplier Unit

3. On-Chip Scrambler and NRZI Encoder with ENABLE

4. CRC Generator with ENABLE

5. 2 or 4 user configurable 75ohm cable driver outputs

6. Output Signal Detect indicators

7. Buffered REFCLK output for easy clock distribution

8. 700 mW Typical Power

Description

The VSC6511 can be configured as a 20-bit HDTV Serializer using the MODE[1:0] pins. A 74.25 MHz
TTL REFCLK is mul tiplied by 20 in the Clock M ultip lier Unit (C MU) to gene rate a 1. 485 GHz b it rate c lock.
The CMU aligns a divided- b y-20 clock wit h REFCLK in order to latc h the 20-bit TTL data b us D[19:0] into the
Input Register. When enabled by CRC being HIGH, the data is mo nito red for S AV/EAV and a CRC checksum i s
calculated and inserted into the data stream at the appropriate point in each video line. The data is then scram­bled and NRZI encoded, only if this stage is enabled by SCREN=HIGH. The data is then serialized and output
on the differential outputs, SDO0/SDO0
driving specifications. The scrambler and NRZI encoder can be disabled by setting the TTL input, SCREN to
LOW. The SDO0/SDO0
larly, the SDO1/SDO1

output can be disabled and forced HIGH by setting the TTL input OE0 to LOW. Simi-

output can be disabled and forced HIGH by setting the TTL input OE1 to LOW.

and SDO1/SDO1, which are compliant with the SMPTE 292M cable

Figure 3: Serializer Mode

Draft Copy

OE0
SDO0

SD
ISET0

OE1
SDO1
SDO1
ISET1

OUTPUTS

O0

RCLK

D[19:0]

CRCEN

SCREN

REFCLK

74.25 MHz

D Q

Clock

Multiply

x20

CRC Gen

1.485 GHz

/20

Scrambler

NRZI Encoder

*

Serializer

CABLE DRIVER

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SMPTE-292M Serializer, Deserializer, and

Deserializer/Reclocker at 1.485Gb/s

Functional Description: Serializer Mode

The following func ti ona l bl oc ks ar e used i n the S er ia lizer mode of operat i on. P lea se re fer to t he F unct ional
Description at the beginning of this document for the a description of each of these blocks.

Clock Multiplier Unit (CMU)
CRC Generator
Scrambler and NRZI Encoder
Serializer
Cable Driver Outputs

Table 3: T ransmit AC Characteristics (Serializer Mode)

Parameters Description Min Max Units Conditions

Advance Product Information

Measured from the valid data
level of D[0:19] to the crossing
of REFCLK

20% to 80%, 75 Ohm load to
Vdd, Tested on a sample basis

T

T

T

R,TF

T

RJ

1

2

D[0:19] Setup time to the
rising edge of REFCLK

D[0:19] hold time after the
rising edge of REFCLK

SDO0, SDO1 rise/fall time
SDO0/SDO1 output jitter

2.0 —ns.

1.5 — ns.

150 270 ps.

—0.20UI

VSC6511

Draft Copy

Figure 4: Transmit Timing Waveforms (Serializer mode)

REFCLK

T

2

Data Valid

D[19:0]

Data Valid

T

1

Data Valid

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Table 4: Transmit AC Characteristics (Serializer Mode)

Parameters Description Min Max Units Conditions

T

1

T

2

TR,T

D[0:19] Setup time to the
rising edge of REFCLK

D[0:19] hold time after the
rising edge of REFCLK

F

T

RJ

SDO0, SDO1 rise/fall time
SDO0/SDO1 output jitter

2.0 —ns.

1.5 — ns.

150 270 ps.

—0.20UI

SMPTE-292M Serializer, Deserializer, and

Deserializer/Reclocker at 1.485Gb/s

Measured from the valid data
level of D[0:19] to the crossing
of REFCLK

20% to 80%, 75 Ohm load to
Vdd, T e sted on a sampl e basis

Draft Copy

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SMPTE-292M Serializer, Deserializer, and

Deserializer/Reclocker at 1.485Gb/s

VSC6511

Features: Deserializer Mode

Advance Product Information

1. Compliant with SMPTE-292M @ 1.485Gb/s

2. Clock and Data Recovery

3. 1:20 Deserializer

4. Descrambler and NRZI Decoder with ENABLE

5. Data Framer aligns data to SAV/EAV

6. On-chip Clock Multiplier Unit

7. CRC Checker

8. LINE, FRAME, HANC Indication

9. 3.3V, 800 mW -- typical power

10. 20 Bit TTL Interface @ 74.25 MHz

General Description

The VSC6511 can be configured as a 20-bit HDTV Deserializer using the MODE[1:0] pins. Serial data
from SDI/SDI
the serial data is descrambled/NRZI decoded, deserialized and output on D[19:0] synchronously by a divided­by-twenty recovered clock, RCLK. A CRC Checker monitors the output data and indicates any CRC errors on
the CRC pin. Descrambling is enabled by SCREN being HIGH. Data framing aligns the SAV/EAV patterns in
the data with the data bus and RCLK and generates a once -per-line and once-per -frame syn chronizat i on out put.
A signal detect function on SDI/SDI

is sent to the Clock Recovery Unit (CRU) for clock extraction and data resynchronization. Then

monitors the quality of the serial input.

Figure 5: Deserializer Mode

Draft Copy

D[19:0]

SCREN

SIGDET

SDI
SDI

REFCLK

74.25 MHz

Clock

Recovery

Unit

Clock

Multiply

x20

1.485 GHz

1.485 GHz

/20

NRZI Decoder

Descrambler

Framer

CRC CheckDeserializer

D Q

CRCERR

LINE
FRAME
HANC

1001

RCLK

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dvance Product Information

SC6511

SMPTE-292M Serializer, Deserializer, and

Deserializer/Reclocker at 1.485Gb/s

Functional Description: Deserializer Mode

The following functional blocks are used in the Deserializer mode of operation. Please refer to the Func-

tional Description at the beginning of this document for the a description of each of these blocks.

Clock Multiplier Unit (CMU)
Serial Input
Clock Recovery Unit
Deserializer
Descrambler and NRZI Decoder
CRC Checker
Frame Aligner and SAV/EAV output

Figure 6: Receive Timing Waveforms (Deserializer Mode)

RCLK

D[0:19]

LINE

T

1

Data Valid

T

2

FRAME

CRCERR

Draft Copy

Table 5: Receive AC Characteristics (Deserializer Mode)

Parameters Description Min. Max. Units Conditions

T

1

T

2

TR, T

F

T

LOCK

Note: The RCLK output from the CRU is 40% high and 60% low by design.

TTL Outputs alid prior to
RCLK rise

TTL Outputs valid after
RCLK rise

TTL Output rise and fall
time

Data acquisition lock time
@ 1.485 Gb/s

3.0 —ns.

2.0 — ns.

—2.0ns.

— TBC ms.

Between V
V

IH(MIN)

IL(MAX)

, into 10 pf. load.

and

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SMPTE-292M Serializer, Deserializer, and

Deserializer/Reclocker at 1.485Gb/s

VSC6511

Features: Deserializer / Reclocker Mode

Advance Product Information

1. Compliant with SMPTE-292M @ 1.485Gb/s

2. Clock and Data Recovery

3. 1:20 Deserializer

4. Descrambler and NRZI Decoder with ENABLE

5. Data Framer al igns data to SAV/EAV

6. 2 or 4 User Configurable 75 ohm cable driver outputs

7. On-chip Clock Multiplier Unit

8. LINE, FRAME, HANC Indication

9. CRC Checker

10. 20 Bit TTL Interface @ 74.25 MHz

11. On-chip Clock Multiplier and Recovery Unit

12. 3.3V, 900mW -- typical power.

General De scription

In the Deserializer/Reclocker Mode, both the Deserializer and the Reclocker are active. All the features of
each function are available with the exception of the reclocker status/control pins on the databus D0 and D2. In
this mode, D[0:19 ] is used solely for th e deseria lized recovered d ata. A lso, RC LK is use d for the dese rializ er’s

recovered clock and will not provide a buffered version of REFCLK and the BYPASS capability is also not
available.

Figure 7: Block Diagram: De serializer/Reclocker Mode

OE0

Draft Copy

D[19:0]

SCREN

SDI
SDI

REFCLK

74.25 MHz

Clock

Recovery

Unit

Clock

Multiply

x20

Deserializer

1.485 GHz

1.485 GHz

/20

NRZI Decoder

Descrambler

CRC Check

Framer

CABLE DRIVER

D Q

SDO0
SDO0
ISET0

OE1

SDO1
SDO1
ISET1

OUTPUTS

SIGDET

CRCERR

LINE
FRAME
HANC

RCLK

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SC6511

Figure 8: REFCLK Timing Waveforms: All Modes

T

L

SMPTE-292M Serializer, Deserializer, and

Deserializer/Reclocker at 1.485Gb/s

T

H

REFCLK

T

R

Table 6: Reference Clock Requirements *

Parameters Description Min Max Units Conditions

FR Frequency Range

FO Frequency Offset

DC REFCLK duty cycle

, T

T

H

L

T

R

Note: The PLL locks to the rising edge of REFCLK.

REFCLK high/low times
REFCLK rise

73.75 74.50 MHz

-1000 1000 ppm.

-15 +15 %

3.0 —ns.

—2.0ns.

Will accept both 74.176/74.25MHz
Difference in REFCLK frequencies

between the transmitting and
receiving VSC6511s.

Measured at 1.5V
Measured between V

V

IL(MAX)

Between V

or V

IL(MAX)

IH(MIN)

V

IH(MIN)

V

IL(MAX)

IL(MAX)

to V

and V

to

IH(MIN)

IH(MIN)

Figure 9: RCLK Timing Waveforms*

T

Draft Copy

L

T

H

V

IH(MIN)

RCLK

V

IL(MAX)

T

R

Table 7: RCLK Performance - Deserializer and Deserializer/Reclocker Mode

Parameters Description Min Max Units Conditions

F

OFFSET

DC RCLK duty cycle - 40% / 60%

T

H

T

L

T

R

Note: The RCLK output from the CRU is 40% high and 60% low by design.

RCLK Frequency offset from
REFCLK

RCLK high times

RCLK low times
RCLK rise/fall time

-1.0 +1.0 %

-5 +5 %

3—ns.

5.9 — ns.

—1.5ns.

Maximum deviati on when th e CR U is
not locked. Deserializer Mode.

Measured at 1.5V. Deserializer Mode
and Deserializer/Reclocker Mode.

Measured between V
V

IH(MIN)

Measured between V
V

IL(MAX)

Between V

IL(MAX)

and V

IH(MIN)

IL(MAX)

to

to

IH(MIN)

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Table 8: RCLK Performance -

Parameters Description Min Max Units Conditions

DC RCLK duty cycle - 50% / 50%

, T

T

H

L

T

R

Note: The RCLK output is a buffered version of the REFCLK input. The above specifications assume a 50% duty cycle on the

REFCLK input.

RCLK high/low times
RCLK rise/fall time

Absolute Maximum Ratings

Power Supply Voltage (VDD) .............................................................................................................-0.5V to +4V

PECL DC Input Voltage.........................................................................................................-0.5V to V

TTL DC Input Voltage.......................................................................................................................-0.5V to 5.5V

DC Voltage Applied to TTL Outputs ................................................................................... -0.5V to V

TTL Output Current ..................................................................................................................................+/-50mA

PECL Output Current................................................................................................................................+/-50mA

Case Temperature Under Bias.........................................................................................................-55° to +125

Storage Temperature.......................................................................................................................-65° to + 150

Maximum Input ESD (Human Body Model).............................................................................................. 1500 V

Serializer & Reclocker Modes

-5 +5 %

3.5 —ns.

—1.5ns.

(1)

Measured at 1.5V. Serializer &
Reclocker Modes (REFCLK=50/50)

Measured between V
V

IL(MAX)

Between V

or V

IL(MAX)

IH(MIN)

VSC6511

IL(MAX)

to V

IH(MIN)

and V

IH(MIN)

DD

DD

to

+0.5V

+ 0.5V

o

C

o

C

Recommended Operating Conditions

Draft Copy

Power Supply Voltage.................................................................................................... .....................3.3V +/- 5%

Ambient Operating Temperature Range...............................................................0°C Ambient to +95°C Case

Notes:

1) CAUTION: Stresses listed under “Absolute Maximum Ratings” may be applied to devices one at a time without causing

permanent damage. Functionality at or above the values listed is not implied. Exposure to these values for extended peri­ods may affect device reliability.

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SC6511

DC Characteristics

Parameters Description Min Typ Max Units Conditions

V

V

I

I

V
V

V

P

∆V

∆V

OUT75

IH
IL

IH

IL

OH
OL
DD

D

IN

Input HIGH voltage (TTL)
Input LOW voltage (TTL)

Input HIGH current (TTL)

Input LOW current (TTL)
Output HIGH Voltage (TTL)

Output LOW Voltage (TTL)
Supply voltage
Power Dissipation:

(Estimated)
Serializer Mode
Deserializer Mode
Deserializer/Reclocker
Mode

PECL input swing:

PECL output swing:

(Over recommended operating conditions).

2.0 —5.5 V
0—0.8 V

——500 µA

——-500µA

2.4 — — V

——0.5 V

3.14 — 3.47 V

—
—
—

200 — 1200 mVp-p

750 — 850 mVp-p

SMPTE-292M Serializer, Deserializer, and

Deserializer/Reclocker at 1.485Gb/s

—

VIN = 2.4 V, 6.8Kohm Pull­up resistor on all inputs.

VIN = 0.5 V, 6.8Kohm Pull­up resistor on all inputs.

I

= -1.0mA

OH

IOL= +1.0mA
VDD = 3.3V + 5%

700
800
900

mW

Outputs open, VDD = VDD
max
(These are estimates)

AC Coupled.
Internally biased at V

Using appropriate matching
network

DD

/2

Draft Copy

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SMPTE-292M Serializer, Deserializer, and

Deserializer/Reclocker at 1.485Gb/s

Package Pin Descriptions

MODE1

VREF

63 61 59 57 55 53 51 49

V53

D0
D1
D2

VDDT

D3
D4
D5
D6

VDDT

D7
D8
D9

VSST

Draft Copy

VSSA

CAP0

1

3

5

7

9

11

13

15

17 19 21 23 25 27 29 31

Figure 10: Pin Diagram

ISET1

SDO1

OE1

VSSP

SDO1

VDDD

SDO0

VSC6511

VSSP

Advance Product Information

VSC6511

ISET0

VDDD

MODE0

SDO0

OE0

TEST1

VSST

47

45

43

41

39

37

35

33

D10
D11

D12
VDDT

D13
D14
D15
D16
VDDT

D17
D18
D19

VSST
LINE
SIGDET

(Top View)

Table 9: Pin Identification

Pin # Name Description

2,3,4,6

7,8,9,11
12,13,47,46
45,43,42,41
40,38,37,36

50
64

24 SCREN

Page 16 

D0-D3
D4-D7

D8-D11
D12-D15
D16-D19

MODE0
MODE1

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SDI

CAP1

VDDA

SDI

VDDD

TEST2

VDDD

SCREN

1.001
HANC

FRAME

VDDD

REFCLK

CRC

RCLK

VSST

INPUT/OUTPUT - TTL
Bidirectional data bus. In Serializer mode, this is a 20-bit input bus timed to
REFCLK. In Deserializer mode, this is a 20-bit output bus timed to RCLK. In
Reclocker and Cable Driver mode, several of these bits are defined as status
outputs.

INPUT - TTL: Mode select inputs. See Table #2.
INPUT - TTL: When HIGH, enables scrambling in Serializer/Deserializer modes

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Pin # Name Description

30 CRC

26 FRAME

34 LINE

27 HANC

25 1.001

21,22 SDI, SDI
56,54

60,58
52,62 ISET0, ISET1

53,61 OE0, OE1

Draft Copy

29 REFCLK

31 RCLK

33 SIGDET

16,17 CAP0, CAP1
49,19 TEST1, TEST2

1V53

20,23,28,57,51 VDDD

5,10,39,44 VDDT

63 VREF
18 VDDA

55,59 VSSP

14,32,35,48 VSST

15 VSSA

SDO0, SDO0
SDO1, SDO1

SMPTE-292M Serializer, Deserializer, and

Deserializer/Reclocker at 1.485Gb/s

BIDIRECTIONAL - TTL: In Serializer Mode, CRC Generation is enabled when
this input is HIGH and disabled when LOW. In Deserializer Mode and
Deserializer/Reclocker Mode, this is an output which indicates a CRC error has
occurred.

OUTPUT - TTL: In Deserializer and Deserializer/Reclocker modes, this is an
output which, when HIGH, indicates that a FRAME synchronization event is on
D[0:19].

OUTPUT - TTL: In Deserializer and Deserializer/Reclocker modes, this is an
output which, when HIGH, indicates that a LINE synchronization event is on
D[0:19].

OUTPUT- TTL: Output which is HIGH during the Horizontal Blanking period
between EAV and SAV.

OUTPUT - TTL: When HIGH, indicates that a valid receive signal is present on
SDI/SDI
20xREFCLK.

INPUT - Differential. Serial input to CRU.
OUTPUT - Differential. High Speed Cable Driver output.

Serial output from the Serializer, Reclocker or SDI/SDI
Connect resistor to ground to set the output swing of SDO0, and SDO1
INPUT - TTL. Output enable pins for SDO0, and SDO1. Enabled when high for

each output.
INPUT - TTL. REFerence CLocK at 74.25 MHz. This is the input to the CMU and

times D(19:0) in Serializer Mode.
OUTPUT - TTL: Output clock. In Serializer and Reclocker Mode, this is a buffered

version of REFCLK. In Deserializer Mode, this is the recovered clock used to time
D(19:0).

OUTPUT - TTL. An analog signal detect output which, when HIGH, indicates
that the IP/IN input contains a valid SMPTE-292M amplitude signal.

Analog I/O: Loop Filter Capacitor, 0.1uF nominal, 3V swing maximum
INPUT - TTL. LOW for factory test, HIGH for normal operation.
INPUT - POWER: This power supply would normally be 3.3V. If 5V tolerance is

required, this pin should be connected to 5V supply.
Power Supply. 3.3V Supply for digital logic.
TTL I/O Power Supply.
Voltage Reference Input. If used, this is biased to 1.25V.
Analog Power Supply. 3.3V for Clock Multiplier PLL. Bypass to pin 15.
Ground for High Speed Outputs
TTL I/O Ground
Analog Ground Bypass to pin 18.

and that the SMPTE-292M incoming data is greater than 500ppm from

input buffer.

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VSC6511

Package Thermal Characteristics

The VSC6511 is packaged in an exposed pad, thin quad flat pack (TQFP) which adheres to industry stan­dard EIAJ footprints for a 10x10x1.0mm body, 64 lead TQFP. The package construction is shown below. The
bottom of the lead frame is exposed so that it can be soldered to the printed circuit board and connected to the
ground plane. This provides excellent thermal characteristics and reduces electrical parasitics as well.

Figure 11: Package Cross Section

Advance Product Information

Wire Bond

Copper Lead Frame

Ground Bond

Die

Die Attach Epoxy

Exposed Pad

Plastic Molding Compound

Table 10: 64-pin, Exposed Pad TQFP Thermal Resistance

Symbol Description Value Units

Draft Copy

θ

ca-0

θ

ca-100

θ

ca-200

θ

ca-400

θ

ca-600

The VSC6511 is designed to operate with a case temperature up to 95oC. The user must guarantee that the
case temperature specification is not violated. With the thermal resistances shown above, the VS6511 can oper­ate in still air ambient temperat ures of 70
these limits then some form of cool ing thr ough a hea tsink or an increa se in airflo w mu st be pr o vided. Add itional
heat can be transferred to the printed circuit board by not using thermal reliefs on the power and ground plane
vias as well as using multiple vias to the power and ground planes.

If the exposed pad is not sol de re d to t he pr i nted circuit board and gro unde d, b ot h ther mal an d el ectr i cal per­formance will be degraded significantly.

Thermal resistance from case to ambient, still air
Thermal resistance from case to ambient, 100 LFPM air
Thermal resistance from case to ambient, 200 LFPM air
Thermal resistance from case to ambient, 400 LFPM air
Thermal resistance from case to ambient, 600 LFPM air

o

C [~70oC = 95oC - 0.8W * 30]. If the ambient air t emperature e xceeds

30
25
23
21
20

o

C/W

o

C/W

o

C/W

o

C/W

o

C/W

Moisture Sensitivity Level

This device is rated with a Moisture Sensitivity Level 3 rating. Refer to Application Note AN-20 for
appropriate handling procedures.

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SMPTE-292M Serializer, Deserializer, and

Deserializer/Reclocker at 1.485Gb/s

Package Information: 64-pin Exposed Pad TQFP

F

G

64 49

1

16

Exposed Pad

(Bottom Side)

N

3217

11/13o

48

M

IH

33

Item mm Tolerance

A1.20 MAX

A1 0.10 ±0.05

A2 1.00 ±0.05

E0.22 ±0.05
F 12.00 ±0.40
G 10.00 ±0.10
H 12.00 ±0.40

I 10.00 ±0.10
J0.60 ±0.15

K0.50 BSC

Mx.xx ±0.xx

Nx.xx ±0.xx

A

A2

Draft Copy

0.08/0.20 R

0

11/13

0.08 R. MIN.

K

0o-7o

0.09/0.20
J

A1

0.xxx MAX. LEAD
NONPLANARITY

E

NOTES:
Drawing not to scale.
Exposed Pad Electrically Grounded
All dimensions in millimeters

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SMPTE-292M Serializer, Deserializer, and

Deserializer/Reclocker at 1.485Gb/s

Ordering Information

The order number for this product is formed by a combination of the device number, and package type.

Device Type

VSC6511 - SMPTE-292M Multifunction Chip

Package Type

RC: 64-Pin, 10x10x1.0mm, Exposed Pad TQFP

Marking Information

The package is marked with three lines of text as shown below.

Figure 12: Package Marking Information

Pin 1 Identifier

VITESSE

VSC6511

Advance Product Information

VSC6511

RC

Draft Copy

Part Number

Date Code

VSC6511 RC

####AAAA

Package Suffix

Lot Tracking Code

Notice

This document contains informat ion ab out a prod uct duri ng it s fa bricati on or ear ly sampli ng phase of de v el­opment. The information contained in this document is based on design targets, simulation results or early pro­totype test results. Characteristic data and other specifications are su bject to change without notice. Theref ore
the reader is cautioned to confirm that this data sheet is current prior to design or order placement.

Warning

Vi tesse S emicondu ctor Co rporat ion’s products are not intended for use in life supp ort appl iances, de v ices or
systems. Use of a Vitesse product in such applications without written consent is prohibited.

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Revision History

2.0 New Document.

SMPTE-292M Serializer, Deserializer, and

Deserializer/Reclocker at 1.485Gb/s

Draft Copy

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Advance Product Information

VSC6511

Draft Copy

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