Datasheet VSC6424 Datasheet (VITESSE)

VITESSE

SEMICONDUCTOR CORPORATION

Preliminary Datasheet

SC6424

500 Mb/s Video

Shift Register IC

Features

• Multiplex or Demultiplex Operation

• Selectable Shift Register Length

• 500Mb/s Operation using internal timing

• 250Mb/s Operation using external timing

• Functional Replacement for Bt424

• External ECL Reference Voltage (-1.32 V)

• ECL and TTL I/Os: ECL for high-speed interface,
TTL for low-speed interface

• Power Supplies: +3.3V an d -2V @ 2.7 Watts (Max.)

o

• Commer cial (0

to +70oC) Temperature Range

• Package: 14mm x 20mm 128 PQFP

General Description

The VSC6424 is a 500Mb/s vide o shift register IC that is b ased on a 40-bit us er-configured shift register.
The shift register may b e used ei t her as a mult ip lexer (parallel in , serial out ) o r as a demul t iplexer (serial in, par­allel out). The VSC642 4 can be configured int o 8 5 - bi t, 8 4- bi t , 5 8- b it , 4 10- bi t , 2 16 - bit , 2 20- bi t , 1 3 2- bi t, or 1
40-bit shift register.

VSC6424 Functional Block Diagram

OEN

HBLANK

Low

Speed

Interface

(TTL)

VBLANK

A<0:4>

AEN/RETIME

SIN

(ECL)

SB<0:39>

S<0:2>
MODE

INT/EXTN

OPS

LLDN

SEN/DIVC

SLDN/SYNC

CLK

(ECL)

SP<0:2>

40

3

3

Input

Latch

(TTL)

(TTL)

Timing Control

Clock

Generator

5

40

40-bit

Shift

Register

40

10

Phase

R o ta tio n

MUX

DE­MUX

8

10

DOUT<0:7>

CLKOUT

DIN<0:9>

CLKE(ECL)
CLKT(TTL)

High

Speed

Interface

(ECL)

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00 Mb/s Video

hift Register IC

Preliminary Datash ee t

VSC6424

Functional Description

The VSC6424 is a 40-bit user configurable shift register designed to provide general purpose serialization
or de-serialization for high speed designs. The VSC6424 provides both multiplexer (MUX) and demultiplexer
(DEMUX) operations in a single package. With the ability to generate timing signals internally or have them
provided externally the VSC6424 maintains the highest design flexibility.

The low speed signals (parallel dat a, c onfiguration, external timing) use a TTL interface and t he high-speed
signals (serial data, high-speed clock) use an ECL interface. Two power supplies are utilized, +3.3 Volts and -2
Volts, dissipating a maximum of 2.7 Watts. A -1.32V external reference voltage is necessary for the ECL inter­face. The part is packaged in a 14mm x 20mm 128-pin plastic quad flat pack with an exposed heat spreader.

Shift Register Mode/Modulus Selection

The shift register can be setup to work as multipl exer or as a demultiplexer. The MODE pin controls the
direction of operation (MUX or DEMUX). The select pins S<0:2> put the shift register in one of 8 configura­tions shown in Table 1

Table 1: Modulus of Operation

S2 S1 S0

0 0 0 8 4:1 10 1:4
0 0 1 8 5:1 8 1:5
0 1 0 5 8:1 5 1:8
0 1 1 4 10:1 4 1:10
1 0 0 2 16:1 2 1:16
1 0 1 2 20:1 2 1:20
1 1 0 1 32:1 1 1:32
1 1 1 1 40:1 1 1:40

Multiplexer

MODE = 0

Demultiplexer

MODE = 1

Internal Timing

The VSC6424 can be set up to use either internal or external timing sources. The VSC6424 contains an
internal timing generato r that provides load an d output rate s dependin g on the modu lus selected for th e shift
register. The timing generator takes an external high speed differential clock (CLK). Internal timing mode must
be used for designs above 250MHz.

The internal timing generator also provides two low-speed clock outputs, CLKT(TTL) and CLKE(ECL).
The low speed clock is brought out so that other ICs can use th is to latch the low speed data while in DMUX
mode. The slow speed clock output can be the same as the internal clock, or 1/2 the internal frequency by set­ting DIVC high. These outputs can also be shifted in 45 degree increme nts, using the phase se lect pins
SP<0:2>, to allow compensation for trace delays on the board. Phase rotation is not available in divide by 5 or
divide by 10 mod es.

The internal high speed clock is also bro ught out to a differential ECL ou tput (CLKOUT). This output is
provided for clocking of the high speed data into the next IC.

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VITESSE

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Preliminary Datasheet

SC6424

The Output Phase Shift (OPS) signal gives the capability of selecting which edge of the high speed clock
the DOUT data is synchron ized to . When OPS is low, DOUT comes out on the rising edge of CLK. When OPS
is high, DOUT comes out on the falling edge of CLK. The high speed output clock (CLKOUT) is not affected by
the state of OPS.

500 Mb/s Video

Shift Register IC

External Timing

To provide a functional replacement for older designs using the Bt424, former ly manufactured by Brook­Tree, the VSC6424 provides an external timing mode. This can be accomplished by setting the INT/EXTN pin
low to bypass the internal timing generator. In this case the load and shift timing signals are provided through
the Shift Enable(SEN ), Shift Register Load Control(SLDN), and the Latch Load C on trol(LLDN) pins.

The VSC6424 has two cycles of propaga tion del ay in mul ti plexer mode where t he Bt 424 onl y has o ne. Thi s
provides the ability to control on which edge of the output clock the output data is clocked on. With the Output
Phase Select (OPS) pin low the output data (DOUT) is synchronous with the positive edge of CLKOUT, where
if OPS is high the output data is synchronous to the negative edge of CLKOUT. See Figure 6 for a timing dia­gram example with OPS low.

The shift register can also be lo aded with seri al dat a while in e xternal t iming mode. T his is accompl ished b y
inputting data into the shift register through the Serial Input (SIN) pin. The data is latched on the rising edge of
the CLK while SLDN is high and SEN is low. The data is then shifted to the output pins on each clock cycle
once Shift Enable (SE N ) is set high.

I/O Mapping

There are 10 high speed ECL data inputs and 8 high speed ECL data outputs. Some configurations of oper­ation do not use all these inputs and outputs. T he sta te of t he out put s n ot being used in a giv en mode is not guar­anteed. The following two tables, Table 2 and Table 3, show how the high speed bus (DOUT or DIN) maps to
the low speed bus (SB) for a given configuration.

Data is taken and supplied LSB first. The numbers in the table cells refers to the data bit on the low speed
bus (SB<0:39>). They are the inputs in MUX mode and the outputs in DEMUX mode.

Table 2: MUX Mode SB to DOUT Cross Reference

S<2:0> Modulus DOUT7 DOUT6 DOUT5 DOUT4 DOUT3 DOUT2 DOUT1 DOUT0

000 8 4:1 28-31 24-27 20-23 16-19 12-15 8-11 4-7 0-3
001 8 5:1 35-39 30-34 25-29 20-24 14-19 10-14 5-9 0-4
010 5 8:1 32-39 24-31 16-23 8-15 0-7
011 4 10:1 30-39 20-29 10-19 0-9
100 2 16:1 16-32 0-15
101 2 20:1 20-39 0-19
110 1 32:1 0-31
111 1 40:1 0-39

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00 Mb/s Video

hift Register IC

Table 3: DEMUX Mode DIN to SB Cross Reference

S<2:0> Modulus DIN9 DIN8 DIN7 DIN6 DIN5 DIN4 DIN3 DIN2 DIN1 DIN0

000 10 1:4 36-39 32-35 28-31 24-27 20-23 16-19 12-15 8-11 4-7 0-3
001 8 1:5 35-39 30-34 25-29 20-24 14-19 10-14 5-9 0-4
010 5 1:8 32-29 24-31 16-23 8-15 0-7
011 4 1:10 30-39 20-29 10-19 0-9
100 2 1:16 16-32 0-15
101 2 1:20 20-39 0-19
110 1 1:32 0-31
111 1 1:40 0-39

Preliminary Datash ee t

VSC6424

Initialization

The VSC6424 requires that the SYNC/SLDN input be low for at least one clock cycle after power on, then
be set high for at least on cloc k per i od to ini t ia li ze t he device. This is an edge sensitive function. In internal tim­ing mode this serves to start the internal clock dividers and set the shift register and low speed output clocks in
motion. Additional edges while in internal timing mode serves to synchronize the output clocks as described
below. Once this has been done the device takes (2n) cycles to stabilize. During this time the slow bus (SB)
should be set to zero. The first data is then latched from the slow bus (SB) at the end of the (2n ) cycles. The
device is no w set to run and will lat ch data fro m the slo w b us (SB) every (n) cycl es. See Table 5 to determine (n)
for a selected modulus.

In MUX mode with internal timing the VSC6424 chip can also be initialized by providing a slow speed
clock to the SYNC input. This slow speed clock must be synchronized with high speed clock and based on the
modulus that the MUX is set to. For example if the VSC6424 is set to 4:1 mode and the high speed clock is set
to 500MHz then the SYNC input must be 125MHz. The initialization at power on will still take (2n) cycles of
the high speed clock. This allows the system to dictate when the slow speed data is latched and where the shift­ing begins.

In external timing mode the SLDN/SYNC signal serves to set the shift register in motion once the data has
been latched from the slow speed bus.

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SEMICONDUCTOR CORPORATION

Preliminary Datasheet

SC6424

Figure 1: Synchronized VSC6424 Block Diagram

120

40

40

VSC6424

40

SLDN/SYNC

CLKT

VSC6424

SLDN/SYNC

3 - 30

VSC6424

SLDN/SYNC

500 Mb/s Video

Shift Register IC

Synchronization

Several VSC6424 chips can be synch roni zed t og eth er while in i nt er nal t iming mode by connecting the sl ow
speed TTL clock output (CLKT) of a master chip to the synchroni zation input (SYNC) of a slave chip. T he in ter­nal timing generator synchronize s to the rising edge of the SYNC input. Given that (n) is the number of high
speed clock cycles for a given modulus mode, synchronization takes two times (n) or (2n) clock cycles to lock
in. If it is necessary to synchroniz e more than two VSC64 24 devices use the TTL clock outpu t (CLKT) from
one chip to drive the SYNC inputs of each of the slave devices. See Figure 2 for a block diagram. See Figure 7
for a timing illustration of the synchronization timing of the slave chip. See Table 5 to determine (n) for a
selected modulus.

In MUX mode multiple VSC6424 chips can als o be sync hronized by pr oviding a slow speed clock to the
SYNC input on all of the devices. This slo w speed cl ock mu st be synchronized with high speed clock and b a sed
on the modulus that the MUX is set to. F or example if the VSC6424 is set to 8: 1 mod e and t he high speed clock
is set to 400MHz then the SYNC input must be 50MHz.

MPU Address Interface

An Address Interface mode translates TTL compatible addresses to ECL compatible output levels. This is
provided for compatibility with the Bt424. When the Address Enable (AEN) signal is low, data from the
Address Line A<0:4> TTL input pins is transferred to the DOUT<0,2,4,6,7> ECL output pins with one clock
cycle delay. When AEN is high, the A<0:4> inputs are ignored. The DOUT<0:7> data is always synchronized
to CLK, regardless of the state of AEN. See Figure 9 for a timing illustration of this function.

Video Blanking

The VSC6424 also has a blanking functi on for video appli cations. I n multip le xe r mode, thi s functi on all o ws
zeroing of the high speed outputs (DOUT<0:7>). Setting HBLANK or VBLANK low drives all DOUT<0:7>
outputs low synchro nously wit h th e clock (CLK). The outputs will be driven low on the modulus boundary. The
outputs are driven low for (n) clock cycles given that (n) is the modulus mode that the chip is set to. See table 4
to determine the value of (n) for a given modulus.

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SEMICONDUCTOR CORPORATION

00 Mb/s Video

hift Register IC

Preliminary Datash ee t

VSC6424

HBLANK or VBLANK must be driven low for at least one clock cycle two clock cycles before the desired
point of blanking. See Figure 6 for a timing illustration of this function.

Retimer

The chip also contains a retime r function. This fun ction works in DEMUX mode. The RETIME signal is
routed to DOUT<7> through a flip-flop. The flip-flop is internally clocked by the low speed ECL output clock
(CLKE). This function is depicted in the detailed block diagram (Figure 3) below. See Figure 5 for a timing
illustration.

Figure 2: Multiplexer Detailed Block Diagram

OEN

MODE

AEN/RETIME

A<0:4>

HBLANK
VBLANK

S<0:2>

OPS

CLK

40

MUX

CLKE

8

Retimer

Output

Latch

DOUT<7>

7

8

DOUT<0:6>

High

Speed

Interface

(ECL)

CLKOUT

Termination

It is recommended to leave all unused ECL outputs floating. It is recommended that unused ECL inputs be
terminated low (-2V supply). Refer t o th e following table recommended input termination for all levels.

Table 4: Input Termination Recommendations

Type State Input

ECL High ground via a diode
ECL Low -2V supply
TTL High +3.3V supply
TTL Low Ground

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SEMICONDUCTOR CORPORATION G52236-0, Rev 3.0

VITESSE

SEMICONDUCTOR CORPORATION

Preliminary Datasheet

SC6424

Figure 3: Multiplexer Timing (Internal Timing. 4:1 Mode.)

CLK

t

cyci

CLKOUT

CLKE

CLKT

t

sbch

SB<0:39>

DOUT<0:7>

t

D0

sbcs

500 Mb/s Video

Shift Register IC

t

cco

t

c-ce

t

ce-ct

D1

ccdn

D0

D0

D0

t

cdn4 cycle delay

D0

t

MODE

OPS

INT/EXTN

HBLANK

VBLANK

S<0:2>

SP<0:2>

DIVC

AEN
OEN

A<0:4>

DIN<0:9>

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00 Mb/s Video

hift Register IC

CLK

CLKOUT

CLKE

CLKT

DIN<0:9>

SB<0:39>

RETIME

Preliminary Datash ee t

Figure 4: Demultiplexer and Retimer Timing (Internal Timing. 1:4 Mode.)

t

cyci

t

cco

D0 D0 D0 D1 D1

D0

t

t

dis

dih

2 cycle delay

D1 D1

D0

t

csb

D2

VSC6424

DOUT

MODE

INT/EXTN

HBLANK

VBLANK

S<0:2>

SP<0:2>

DIVC

DOUT

<0:6>

<7>

OPS

OEN

t

cdn

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VITESSE

SEMICONDUCTOR CORPORATION

Preliminary Datasheet

SC6424

Figure 5: Multiplexer Timing (External Timing. 4:1 Mode)

CLK

t

cyce

CLKOUT

CLKE

CLKT

LLDN
SLDN

SB<0:39>

D

t

sbls

500 Mb/s Video

Shift Register IC

t

cco

t

slds

t

sblh

t

sldh

DOUT

SP<0:2>

<0:7>

INT

MODE

OPS

S<0:2>

SEN

DD

t

cdn2 cycle delay

D

D

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POWER

CLK

CLKE

CLKT

SYNC

Preliminary Datash ee t

VSC6424

Figure 6: Initialization Timing 4:1 Mode

2n Cycles

Figure 7: Synchronization Timing

CLK

CLKOUT

CLKE

CLKT

t

systsyh

SYNC

n cycles n cycles

Synchronizing

Table 5: Synchronization & Blanking Timing

S<0:2> 000 001 010 011 100 101 110 111

n 4 5 8 10 16 20 32 40

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SEMICONDUCTOR CORPORATION

Preliminary Datasheet

SC6424

CLK

t

cyci

CLKOUT

CLKE

CLKT

SB<0:39>

H/VBLANK

<0:7>

DOUT

D1

D0

t

bls

Figure 8: Blanking Timing (Internal Timing)

t

cco

D2

t

blh

2 cycles

D0 D0

n cycles

500 Mb/s Video

Shift Register IC

D3

D2

D2

DOUT

CLK

AEN

A<0:4>

OEN

<0:7>

Figure 9: Address Interface / Output Enable Timing

t

aes

B0 B2

tast

D0 D0 D0 B0 B1

B1

ah

t

aeh

B2

t

oed

D1

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00 Mb/s Video

hift Register IC

Table 6: Timing Tables

Parameter Description Min Typ Max Units

t

cyci

t

cyce

t

dis

t

dih

t

sbcs

t

sbch

t

sbls

t

sblh

t

cco

t

cdn

t

cdi

t

ccdn

t

ccdi

t

oed

t

dds

t

as

t

ah

t

aes

t

aeh

t

bls

t

blh

t

slds

t

sldh

t

sys

t

syh

t

sis

t

sih

t

csb

t

c-ce

t

ce-ct

Preliminary Datash ee t

VSC6424

Minimum cycle time in internal timing mode 2.0 - - ns
Minimum cycle time in external timing mode 4.0 - - ns
DIN setup time 200 - - ps
DIN hold time 900 - - ps
SB setup with respect to CLK 600 - - ps
SB hold tim e with respe ct to CLK 800 - - ps
SB setup with respect to LLD 100 - - ps
SB hold with respect to LLD 1200 - - ps
CLK to CLKOUT delay 1100 - 3500 ps
CLK rising to DOUT, with OPS low 1200 - 3700 ps
CLK falling to DOUT, with OPS high 1300 - 3900 ps
CLKOUT to DOUT skew, with OPS low -140 - 1100 ps
CLKOUT to DOUT skew, with OPS high -50 - 1200 ps
OEN to DOUT 900 - 3000 ps
DOUT<x> to DOUT<y> skew - - 100 ps
A<0:4> setup time 1100 - - ps
A<0:4> hold time 200 - - ps
AEN setup time 900 - - ps
AEN hold time 600 - - ps
H/VBLANK setup 1000 - - ps
H/VBLANK hold 200 - - ps
SLDN setup 1300 - - ps
SLDN hold 100 - - ps
SYNC setup 800 - - ps
SYNC hold 300 - - ps
SIN setup 700 - - ps
SIN hold 300 - - ps
CLK to SB delay 1700 - 5800 ps
CLK to CLKE delay 1500 - 5200 ps
CLKE to CLKT skew 400 - 2500 ps

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Preliminary Datasheet

SC6424

DC Characteristics

Table 7: ECL Inputs and Outputs

Parameter Description Min Typ Max Units Conditions

V

OH

V

OL

V

IH

V

IL

I

IH

I

IL

Notes: 1) Load=50Ω to -2.0V.

2) External Reference (V

Table 8: TTL Inputs and Outputs

Parameters Description Min Max Units Conditions

V

OH

V

OL

V

IH

V

IL

I

IH

I

IL

I

OZH

I

OZL

I

OZHB

I

OH

Output HIGH voltage -1020 - -700 mV ­Output LOW voltage -2000 - -1620 mV ­Input HIGH vol ta ge -1165 - -700 mV ­Input LOW voltage -2000 - -1475 mV ­Input HIGH current - - 200 µAV
Input LOW current -50 - - µAV

) = -1.32 V + 25mV

ref

Output HIGH voltage 2.4 - V IOH = -12 mA

Output LOW voltage - 0.4 V IOL = 12mA

Input HIGH voltage 2.0 V

Input LOW voltage 0 0.8 V -

Input HIGH current - 300 µA VIN = 2.4 V

Input LOW current -50 - µA VIN = 0.4 V

3-State Output OFF

Current HIGH

3-State Output OFF

Current LOW

3-State Output OFF

Current HIGH for Bi-direct s

Open Collecto r O u tput

Leakage Current

-200µA V

-100 - µA V

-500µA V

-200µA V

+ 1.0 V V -

TTL

500 Mb/s Video

Shift Register IC

(max)

IN=VIH

(min)

IN=VIL

= 2.4 V

OUT

= 0.4 V

OUT

= 2.4 V

OUT

= 2.4 V

OUT

Notes: 1) Outputs are open

Power Dissipation

Table 9: VSC6424 Power Supply Currents

Parameter Description (Max) Units

I

TT

I

TTL

P

D

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Power supply current from V
Power supply current from V
Power dissipation (Note: Specified with outputs open circuit.)2.7W

VITESSE

(-2.0 V+0.1V Max -2.1V) 850 mA

TT

(+3.3 V+0.3V Max +3.6V) 250 mA

TTL

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00 Mb/s Video

hift Register IC

Absolute Maximum Ratings

Power Supply Voltage (VTT) Potential to GND.............................................................................-2.5 V to +0.5 V

Power Supply Voltage (V

ECL Input Voltage Applied ...................................................................................................+0.5 V to V

TTL Input Voltage Applied ..................................................................................................-0.5V to V

Output Current (I
Case Temperature Under Bias (T
Storage Temperature (T

Note: Caution: Stresses listed under “A bsolute Maximum Ratings” may be applied to devices one at a time without causing per-

manent damage. Functionality at or exceeding the values listed is not implied. Exposure to these values fo r extended
periods may affect device reliability.

)...................................................................................................................................50 mA

OUT

) Potential to GND...........................................................................-0.5 V to +4.3 V

TTL

)................................................................................................-55o to + 125oC

C

) ...........................................................................................................-65o to + 150oC

STG

(1)

Preliminary Datash ee t

VSC6424

TT

TTL

Recommended Operating Conditions

Power Supply Voltage (VTT)................................................................................................................-2.0 V+0.1V

Power Supply Voltage (V

Commercial Operating Temperature Range* (T).................................................................................. 0

).............................................................................................................+3.3 V+0.3V

TTL

o

to 70oC

-0.5 V

+ 1.0V

* Lower limit of specification is ambient temperature and upper limit is case temperature.

ESD Ratings

Proper ESD procedures should be used when handling this product. The VSC6424 is rated to the following
ESD voltages based on the human body model:

1. All pins are rated at or above 1500V.

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Preliminary Datasheet

SC6424

Package Pin Descriptions

Table 10: Package Pin Identification

Signal Pin I/O Level Description

7, 9, 18, 30, 32, 44, 45,58, 59,

VCC

VTT 3, 6, 13, 26, 33, 70, 77, 90, 97 -2V Supply Connection.
VTTL
VREF 4 -1.32V external ECL Reference voltage.

DIN<0:9>

DOUT<0:7> 86, 84, 83, 81, 80, 76, 75, 74 O ECL The 8 Multiplexer High-Speed Outputs.

SB<0:39>

MODE 62 I TTL Mux/DMux select signal. 1 for DMUX, 0 for MUX.

AEN

RETIME

CLK 60 I ECL Differential Clock Input (True)

CLKN 61 I ECL Differential Clock Input (Complement)

S<0:2> 39, 40, 41 I TTL Shift Register Modulus Control

CLKE 87 O ECL
CLKT 88 O TTL Low Speed Clock. TTL version of above.

SP<0:2> 36, 37, 38 I TTL Phase select for output clocks (CLKE, CLKT)

SYNC
SLDN

LLDN 43 I TTL

SIN 42 I ECL

71, 72, 73, 82, 85, 94, 96 , 10 8,

109, 122, 123

5, 8, 21, 31, 34, 48, 55, 69, 95,

98, 112, 119

101, 102, 103, 104, 105, 68, 67,

66, 65, 64

89, 91, 92, 93, 110, 111, 113,
114, 115, 116, 11 7, 118, 120,

121, 10, 11, 12, 14, 15, 16, 17,

19, 20, 22, 23, 24, 25, 27, 28,
29, 46, 47, 49, 50, 51, 52, 53,

54, 56, 57

100 I TTL

106 I TTL

0V Ground Connection.

+3.3V Supply Connection

I ECL The 10 Demultiplexer High-Speed Inputs.

BTTL

Slow Bidirectional Bus. Multip lexer Input,
Demultiplexer Output.

Address enable. In Mux mode, while AEN is low, the
clock transfers A<0:4> to DOUT<0,2,4,6,7>. In
DMUX mode it provides retimer input.

Low Speed Clock. Clock used for latching the low
speed bus in internal timing mode.

Shift register load control. Used to transfer data from
input latch to shift register in external timing mode.
Data is transferred on the rising edge of CLK while
SLDN is low. In internal timing mode, SYNC is the
synchronization input.

Input latch control. In external timin g mo de , LLDN
low makes the low speed input latches transparent.

Serial data in. The shift register can be serially loaded
using this pin. The data is latche d on rising edge of
CLK. Connect to VTT if not used.

500 Mb/s Video

Shift Register IC

G52236-0, Rev 3.0 
7/13/99 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: [phone]

VITESSE

SEMICONDUCTOR CORPORATION Page 15

VITESSE

SEMICONDUCTOR CORPORATION

00 Mb/s Video

Preliminary Datash ee t

hift Register IC

Table 10: Package Pin Identification

Signal Pin I/O Level Description

Shift enable. In external tim in g m ode , SEN h ig h stops

SEN
DIVC

OEN 107 I ECL

INT

EXTN

A<0:4> 2, 1, 128, 127 , 126 I TTL

HBLANK 124 I TTL Horizo ntal blank function. Active low.
VBLANK 125 I TTL Vertical blank function. Active low.

OPS 35 I TTL

CLKOUT 78 O ECL High spee d cl oc k out (True)

CLKOUTN 79 O ECL High speed output clock (Complement)

63 I ECL

99 I TTL

the shift register from shifting. In internal timing
mode, DIVC high divides the output clocks (CLKE,
CLKT)by 2.

Output Enable. OEN high forces the DOUT<0:7> low.
This signal is asynchronous.

Timing control. A high sets the chip for inte rnal
timing, a low sets the chip for external timing.

Address pins. These pins get transferred to
DOUT<0:7> in Address Interface mode.

Clock phase select. When this signal is low the low
speed outputs (DOUT<0:7>) are clocked with the
rising edge of the clock. Setting it high clocks them
with the falling edge of the clock.

VSC6424

Page 16 

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: [phone]

VITESSE

SEMICONDUCTOR CORPORATION G52236-0, Rev 3.0

VITESSE

SEMICONDUCTOR CORPORATION

Preliminary Datasheet

SC6424

Package Information

The VSC6424 is packaged in a thermally enhanced 128 PQFP with an embedded heat sink.

PIN 128

PIN 1

EXPOSED
INTRUSION

0.127 MAX.

EXPOSED
HEATSINK

PIN 38

RAD. 2.92 ± .50

(2)

D

1

D

TOP VIEW

2.54 ± .50

E

1

PIN 64

500 Mb/s Video

Shift Register IC

E

A

2

Notes: 1) Drawing is not to scale

2) All dimensions in mm

3) Package represented is
also used for the 64,
80, & 100 PQFP packages.

Pin count drawn does

not reflect the 128 Package.

10° TYP .

Part Number:101-267-7
Issue Number: 1

A

A

1

10° TYP .

R

R1

θ

1

.25

A

θ

MAX.

0.17

e

b

STANDOFF

A

1

LEAD COPLANARITY

L

G52236-0, Rev 3.0 

VITESSE

SEMICONDUCTOR CORPORATION Page 17

7/13/99 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: [phone]

VITESSE

SEMICONDUCTOR CORPORATION

00 Mb/s Video

hift Register IC

Package Thermal Considerations

Figure 10: ΘCA vs Air Velocity for the 128 PQFP (14mmx20mmx2.7mm)

30

25

20

15

C/W)

o

(

10

5

Case to Air Thermal Resistance

Preliminary Datash ee t

VSC6424

Air Vel.

LFPM

027.5
100 23.1
200 19.8
400 17.6
600 16.0

Theta(ca)

o

C/W

0

0

Θ

measurement method: Semi-standard G38-87, in a wi nd tunnel

CA

Semi-standard G4 2-88/JEDEC JC 15.1 #1 FR4 PCB 3”x4.5”x0.62”

200 400 600

Air Velocity (LFPM)

Notice

This document contains preliminary information about a new product in the preproduction phase of devel­opment. The information in this docume nt is based on i niti al pr oduct characterization. Vitesse reserv es th e right
to alter specifications, features, capabilities, functions, manufacturing release dates, and even general availabil­ity of the product at any time. The reader is cautioned to confirm this datasheet is current prior to using it for
design.

Warning

Vitesse Semiconductor Corporation’s product are not intended for use in life support appliances, devices or
systems. Use of a Vitesse product in such applications without the written consent is prohibited.

Page 18 

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: [phone]

VITESSE

SEMICONDUCTOR CORPORATION G52236-0, Rev 3.0