Page 1
Features
• High output voltage and wide bandwidth: optimal for
use in color monitors in the fH(horizontal deflection
frequency) = 90-kHz class
(f = 120 MHz –3 dB at V
OUT
= 40 Vp-p)
• Package: Molded 15-pin SIP package housing 3
channels in a single package
Package Dimensions
unit: mm
2127A
Wideband Output Module (Video Pack)
Ordering number : EN5309A
93096HA (OT) No. 5309-1/4
[VPS12]
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN
CRT Display Video Output Amplifier:
High-Voltage, Wideband Amplifier
VPS12
Parameter Symbol Conditions Ratings Unit
Recommended supply voltage
V
CC
80 V
V
BB
10 V
Parameter Symbol Conditions Ratings Unit
Maximum supply voltage
V
CC
max 90 V
V
BB
max 15 V
Allowable power dissipation Pd max At Tc = 25°C with an ideal heat sink 25 W
Maximum junction temperature Tj max 150 °C
Maximum case temperature Tc max 100 °C
Storage temperature Tstg –20 to +110 °C
Specifications
Absolute Maximum Ratings at Ta = 25°C
Parameter Symbol Conditions
Ratings
Unit
min typ max
Frequency band (–3 dB) f
c
V
CC
= 80 V, VBB= 10 V, CL= 10 pF
120 MHz
V
IN
(DC) = 3.2 V, V
OUT
(p-p) = 40 V
Pulse response
t
r
V
CC
= 80 V, VBB= 10 V, CL= 10 pF 4.2 ns
t
f
V
IN
(DC) = 3.2 V, V
OUT
(p-p) = 40 V 3.2 ns
Voltage gain VG (DC) 13 15 17 Times
I
CC
(1)
VCC= 80 V, VBB= 10 V, VIN(DC) = 2.9 V,
45 mA
Current drain
f = 10 MHz clock, CL= 10 pF, V
OUT
(p-p) = 40 V
ICC(2)
VCC= 80 V, VBB= 10 V, VIN(DC) = 2.9 V,
70 mA
f = 120 MHz clock, CL= 10 pF, V
OUT
(p-p) = 40 V
Electrical Characteristics at Ta = 25°C (for a single channel)
Operating Conditions at Ta = 25°C
Page 2
Internal Equivalent Circuit
Test Circuit (for testing a single channel)
No. 5309-2/4
VPS12
Page 3
Thermal Design
Since the VPS12 has the three-channel configuration shown in the circuit diagram on page 2, we first consider a single
channel. The chip temperatures of the transistors during operation can be determined from the following formula:
Tj = (Tri) = θj-c (Tri) × Pc (Tri) + ∆Tc + Ta (°C)........................(1)
θj-c (Tri): Thermal resistances of the transistor chips themselves
Pc (Tri): Collector loss of the transistors
∆Tc: Increase in case temperature
Ta: Ambient temperature
The θj-c (Tri) for the individual transistors is:
θj-c(Tr1) to (Tr4) = 35°C/W.........................................................(2)
Although the loss in each transistor in the video pack changes with frequency and thus are not identical, assuming a
maximum frequency of 120 MHz (clock), the transistor with the largest loss is Tr3 in the emitter-follower stage. From
the Pd-f(clock) figure it can be seen that this loss is 22% of the total loss. Thus:
Pc (EF stage) f = 120 MHz = Pd (1ch) f = 120 MHz × 0.22 [W] .............(3)
Select a θh for the heat sink so that the junction temperature (Tj) of this transistor does not exceed 150°C. Equation (4)
gives the relationship between θh and ∆Tc.
∆Tc = Pd (TOTAL) × θh ..............................................................(4)
The required θh can be calculated from this equation and equation (1).
No. 5309-3/4
VPS12
Page 4
VPS12 Thermal Design Example
Conditions: fV= 120 MHz (clock) in an fH= 85-kHz class monitor
VCC= 80 V, VBB= 10 V, V
OUT
= 40 Vp-p (CL= 10 pF)
Consider using this monitor at Ta = 60°C and operating it at a maximum frequency of f = 120 MHz (clock).
As was mentioned previously, the chip with the largest loss is Tr3 in the emitter-follower stage. Deriving that value from
the figures below and equation (3) gives:
Pc (EF stage) = 5.8 × 0.22 ≈ 1.3 [W]............................................(5)
Next, applying the value of θj-c to equation (5) shows ∆Tj to be as follows:
∆Tj = 1.3 × 35 = 45.5 [°C]
Here, ∆Tj is less than 50°C, and in the thermal design we only have to assure that Tc is less than 100°C. That is, we must
set θh so that Tc is less than 100°C when Pd (TOTAL) = Pd (one channel) × 3.
Here, ∆Tc will be ∆Tc = 100 – 60 = 40°C
Since θh = ∆Tc ÷ Pd (TOTAL) = 40 ÷ (5.8 × 3) = 2.3, then θh = 2.3 °C/W.
In an actual system, it may be possible to use a heat sink smaller than the one required for the value calculated above due
to the actual ambient temperature and other operating conditions. Actual designs should be optimized to match those
conditions using the data presented above.
No. 5309-4/4
VPS12
VCC(V) VBB(V) V
OUT
(V) VO(center)
80 10 40 45
This catalog provides information as of September, 1996. Specifications and information herein are subject to
change without notice.
■ No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace
equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of
which may directly or indirectly cause injury, death or property loss.
■ Anyone purchasing any products described or contained herein for an above-mentioned use shall:
➀
Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and
distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all
damages, cost and expenses associated with such use:
➁
Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on
SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees
jointly or severally.
■ Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for
volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied
regarding its use or any infringements of intellectual property rights or other rights of third parties.
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