Datasheet VND830LSP Datasheet (ST)

®

VND830LSP

DOUBLE CHANNEL HIGH SIDE DRIVER

TYPE R

DS(on)

I

OUT

V

CC

VND830 LSP 60 mΩ (*) 18 A (*) 36 V

(*) Per each channel

■ CMOS COMPATIBLE INPUTS

■ OPEN DRAIN STATUS OUTPUTS

■ ON STATE OPEN LOAD DETECTION

■ OFF STATE OPEN LOAD DETECTION

■ SHORTED LOAD PROTECTION

■ UNDERVOLTAGE AND OVERVOLTAGE

SHUTDOWN

■ LOSS OF GROUND PROTECTION

■ VERY LOW STAND-BY CURRENT

■ REVERSE BATTERY PROTECTION (**)

DESCRIPTION

The VND830LSP is a monolith ic device made by using STMicroelectronics VIPower M0-3 Technology, i ntended for dr iving any ki nd of load with one side connected to ground. Active VCC pin voltage clamp protec ts the device against low energy spikes (see ISO7637 transient

BLO C K DIAGRA M

10

1

PowerSO-10

™

compatibility table). Active current limitation combined with thermal shutdown a nd automatic restart protects the device against over load. The device detects open load condition both in on and off state. The openload threshold is aimed at detecting the 5W/12V standard bulb as an openload fault in the on state. Device automatically turns off in case of ground pin disconnection.

V

CC

V

CC

CLAMP

GND

INPUT1

STATUS1

OVERTEMP. 1

INPUT2

STATUS2

OVERTEMP. 2

(**) See application schematic at page 8

LOGIC

OVERVOLTAGE

UNDERVOLTAGE

CLAMP 1

DRIVER 1

CURRENT LIMITER 1

OPENLOAD ON 1

OPENLOAD OFF 1

CLAMP 2

DRIVER 2

CURRENT LIMITER 2

OPENLOAD ON 2

OPENLOAD OFF 2

OUTPUT1

OUTPUT2

March 20 03 1/18

VND830LSP

ABSOLUTE MAXIMUM RATI NG

Symbol Parameter Value Unit

tot

DC Supply Voltag e 41 V Reverse DC Supply Voltage - 0.3 V

CC

DC Reverse Ground Pin Current - 200 mA DC Output Current Internally Limited A Reverse DC Output Current - 6 A DC Input Current +/- 10 mA DC Status Cur rent +/- 10 mA Electros tatic Dischar ge (Human Bod y Model: R=1.5K Ω; C=100pF)

- INPUT

- STATUS

- OUTPU T

- V

CC

4000 4000 5000 5000

Powe r Dissipation TC=25°C 74 W

Maximum Switching Energy (L=0.14m H; R Junction Operating Temperature Internally Limited °C

j

Case Operating Temperature - 40 to 150 °C

c

=0Ω; V

L

=13.5V ; T

bat

=150ºC ; IL=14A)

jstart

52 mJ

Storage Temperature - 55 to 150 °C

V

CC

- V

- I

GND

I

OUT

- I

OUT

I

IN

I

STAT

V

ESD

P

E

MAX

T

stg

CONNECTION DIAGRAM (TOP VIEW)

V V V V

GROUND INPUT 1 STATUS 1 STATUS 2 INPUT 2

V

CC

CURRENT AND VOLTAGE CONVENTIONS

I

IN1

I

V

IN1

V

STAT1

I

IN2

I

V

STAT2

IN2

V

STAT2

INPUT 1

STATUS 1

INPUT 2

STATUS 2

6 7 8 9

10

11

5 4 3

2 1

V

CC

OUTPUT 1 OUTPUT 1 N.C. OUTPUT 2 OUTPUT 2

I

OUT1

I

S

V

CC

OUTPUT 1

V

OUT1

I

OUT2

V

OUT2

GND

OUTPUT 2

I

GND

2/18

1

VND830LSP

THERMAL DATA

Symbol Parameter Value Unit

R

thj-case

R

thj-amb

(*) When mounted on a standard single-sided FR-4 board with 50mm2 of Cu (at least 35µm thick). Horizontal mounting and no artificial air

flow.

ELECTRICAL CHARACTERISTICS (8V<VCC<36V; -40°C< Tj <150°C, unless otherwise specified)

(Per each channel) POWER OUTPUT

Symbol Parameter Test Conditions Mi n Typ Max Unit

V

CC

V

USD

V

OV

R

ON

I

S

I

L(off1)

I

L(off2)

I

L(off3)

I

L(off4)

Thermal R esistance Ju nction-ca se 2 °C/W

Thermal Resistance Ju nction-amb ient 52 (*) °C/W

(**) Oper at i ng Su pp ly Voltage 5.5 13 36 V

(**) Undervoltage Shut-down 3 4 5.5 V

(**) Overvoltage Shut-down 36 V

On State Resistance

(**) Supply Current

Off State Output Curren t VIN=V Off State Output Curren t VIN=0V; V Off State Output Curren t VIN=V Off State Output Curren t VIN=V

=2A; Tj=25°C

I

OUT

I

=2A; VCC> 8V

OUT

Off State; V Off State; V

V

IN=VOUT

On State; V

OUT

OUT OUT

=13V; V

CC

=13V; Tj =25°C;

CC

=0V

=13V

CC

IN=VOUT

=0V

12

5

=0V; VCC=36V; Tj=125°C 0 50 µA

=3.5V -75 0 µA

OUT

=0V; Vcc=13V; Tj =125°C 5 µA =0V; Vcc=13V; Tj =25°C 3 µA

60

120

40

25

7

mΩ mΩ

µA

mA

(**) Per device

SWITCHING (VCC =13V)

Symbol Parame ter Test Condit ions Min Ty p Max Unit

RL=6.5Ω from VIN rising edge to V

=1.3V

OUT

RL=6.5Ω from VIN falling edge to V

=11.7V

OUT

RL=6.5Ω from V V

=10.4V

OUT

RL=6.5Ω from V V

=1.3V

OUT

=1.3V to

OUT

=11.7V to

OUT

30 µs

See

relative

diagram

See

relative

diagram

dV

t

d(on)

t

d(off )

dt

OUT

(on)

OUT

(off)

Turn-on Delay Time

Turn-off Delay Time

/

Turn-on Voltage Slope

/

Turn-off Voltage Slope

LOGIC INPUT

Symbol Param eter Test Conditions M in Typ Max Unit

Input Low Level 1.25 V

IL

Low Level Input Current VIN = 1.25V 1 µA

IL

Input High Level 3.25 V

IH

High Level Input Current VIN = 3.25V 10 µA Input Hyst eresis Voltage 0.5 V

I

Input Clamp Voltage

= 1mA

IN

I

= -1mA

IN

66.8

-0.7

8V

V

I

V

I

IH

I(hyst)

ICL

V/µs

V

3/18

1

VND830LSP

ELECTRICAL CHARACTERISTICS (continued)

STATUS PIN

Symbol Parameter Test Conditions Min Typ Max Unit

V

STAT

I

LSTAT

C

STAT

V

SCL

Status Low Output Voltage I Status Leakage Current Normal Operation; V Status Pin Input

Capacitance Status Clamp Voltage

PROTECTIONS

Symbol Parame ter Test Condit ions Min Ty p Max Unit

T

TSD

T

t

SDL

I

V

demag

hyst

lim

Shut-down Temperature 150 175 200 °C

Reset Temp erature 135 °C

R

Ther ma l Hy steresi s 7 15 °C Status Delay in Overload

Conditions Current limitation Turn-off Output Clamp

Voltage

= 1.6 mA 0.5 V

STAT

Normal Operation; V

= 1mA

I

STAT

I

= - 1mA

STAT

Tj>T

TSD

V

=13V

CC

5.5V < V I

OUT

< 36V

CC

=2A; L= 6m H VCC-41 VCC-48 VCC-55 V

= 5V 10 µA

STAT

= 5V 100 pF

STAT

66.8

-0.7

18 23 29

8V

20 µs

29

V

A A

OPENLOAD DETECTION

Symbol Param eter Test Conditions M in Typ Max Unit

I

OL

t

DOL(on)

V

T

DOL(off)

OPEN LOAD STATUS TIMING (with external pull-up)

V

INn

V

STATn

Openload ON State Detectio n Threshold Openload ON State Detection Delay

=5V 0.6 0.9 1.2 A

V

IN

=0A 200 µs

I

OUT

Openload OFF State Voltage Detection

OL

Threshold Openload Detection Delay

at Turn Off

V

OUT

t

DOL(off)

VIN=0V 1.5 2.5 3.5 V

OL

I

OUT

t

DOL(on)

> V

< I

OL

V

INn

V

STATn

1000 µs

OVER TEMP STATUS TIMING

Tj > T

TSD

t

SDL

t

SDL

4/18

2

1

Switching time Waveforms

V

OUTn

dV

/dt

OUT

(on)

V

INn

t

d(on)

80%

10%

t

d(off)

90%

dV

OUT

VND830LSP

/dt

(off)

t

TRUTH TABLE

CONDITIONS INPUT OUTPUT STATUS

Normal Operation

Current Limitation

Overtemperature

Undervoltage

Overvoltage

Output Voltage > V

Output Current < I

OL

L

H

L H H

L H

L

H

L X X

(T

< T

j

> T

j

L

L H

H

L H

TSD

H H

H ) H ) L

H

L

X

H

L

H

L

5/18

1

VND830LSP

ELECTRICAL TRANSIENT REQUIREMENTS ON VCC PIN

ISO T/R 7637/1

Test Pulse

1 -25 V -50 V -75 V -100 V 2 ms 10 Ω

2 +25 V +5 0 V +75 V +100 V 0.2 ms 10 Ω 3a -25 V -50 V -100 V -150 V 0.1 µs 50 Ω 3b +25 V +50 V +75 V +100 V 0.1 µs 50 Ω

4 -4 V -5 V -6 V -7 V 100 ms, 0.01

5 +26.5 V +46.5 V +66.5 V +86.5 V 400 ms, 2

ISO T/R 76 37/1

Test Pulse

1C C C C

2C C C C 3aCCCC 3bCCCC

4C C C C

5C E E E

CLASS CONTENTS

C All functions of the device are performed as designed after exposure to disturbance. E One or more functions of the device is not performed as designed after exposure and cannot be returned

to proper operation without replacing the device.

I II III IV Dela ys and

I II III IV

TEST LEVELS

TEST LEVELS R ESULTS

Impedance

Ω

6/18

Figure 1: Waveforms

INPUT

n

OUTPUT VOLTAGE STATUS

V

CC

INPUT

n

OUTPUT VOLTAGE STATUS

V

CC

INPUT

n

OUTPUT VOL TAGE STATUS

VND830LSP

NORMAL OPERATION

n

UNDERVOLT AGE

V

USD

n

OVERVOLTAGE

VCC<V

OV

n

USDhyst

undefined

VCC>V

OV

INPUT

n

OUTPUT VOLTAGE STATUS

INPUT

n

OUTPUT VOLTAGE STATUS

T

INPUT

n

j

n

OUTPUT CURRENT

STATUS

n

OPEN LOAD with external pull-up

V

n

V

OL

OUT>VOL

OPEN LOAD without exter nal pull-up

n

OVERTEMPE RATURE

T

TSD

T

R

n

7/18

1

VND830LSP

APPLICATION SCHEMATIC

+5V

R

prot

µ

C

R

prot

R

prot

R

prot

STA T US1

INPUT1

STA TUS2

INPUT2

GND PROTECTION NETWORK AGAINST REVERSE BATTERY

Soluti on 1: Resistor in the ground line (R can be us ed with any typ e of load.

The fo llowin g is an indica tion on how to dim ension the

resistor.

R

GND

1) R

2) R

where -I be found in the absolute maximum rating section of the

≤ 600mV / I

GND

≥ (− VCC) / (-I

GND

is the DC re vers e grou nd pi n cu rren t an d can

GND

S(on)max

)

GND

.

device’s datasheet. Power Dissipation in R

battery situations) is:

= (-VCC)2/R

P

D

GND

(when VCC<0: during reverse

GND

This resistor can be shared amongst several different HSD. Please note that the value of this re sistor shou l d be calcul ated with form ula (1) wher e I sum of the maximum on-state currents of the different

S(on)max

devices. Please note that if the microprocessor ground is not

common with the device ground then the R produce a shift (I and the status output values. This shift will vary

S(on)max

* R

) in the input thresholds

GND

only). This

GND

becomes t he

GND

will

V

CC

OUTPUT1

V

GND

R

GND

D

OUTPUT2

GND

depending on how man y devic es are ON in the ca se of several high side drivers sharing the same R

If the calculated power dissipation leads to a large resistor or seve ral de vic es have to s hare t he s ame r esisto r then the ST suggests to utilize Solution 2 (s ee below).

Solution 2: A resistor (R

D

GND

A diode (D

=1kΩ) should be inserted in parallel to

GND

if the devi ce will be driving an inductive load.

) in the gro und line.

GND

This small signal diode can be safely shared amongst several different HSD. Also in this case, the presence of the ground network wi ll produce a shift ( input threshold and the status output values if the microprocessor ground is not common with the device ground. This shift will not vary if more than one HSD shares the same diode/resistor network.

LOAD DUMP PROTECTION

Dld is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds VCC max DC rating. The same applies if the device will be subject to transients on the VCC line that are grea ter tha n the ones sh own in the ISO T/R 7637/1 table.

D

ld

.

GND

j

600mV) in t he

8/18

1

C I/Os PROTECTION:

µ

If a ground protection network is used and negative transient are present on the VCC line, the control pins will be pulled negative. ST suggests to insert a resistor (R in line to prevent the µC I/Os pins to latch-up.

prot

The valu e of these res istors is a compromise between the leakage curre nt of µC and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of µC I/Os.

-V

CCpeak/Ilatchup

prot

≤ (V

OHµC-VIH-VGND

) / I

IHmax

≤ R

Calcu lation examp le:

CCpeak

prot

= - 100V and I

≤ 65kΩ .

For V 5kΩ ≤ R Recomm ended R

value is 10kΩ.

prot

latchup

≥ 20mA; V

OHµC

≥ 4.5V

OPEN LOAD DETECTION IN OFF STATE

Off state open load detection requires an external pull-up resistor (R

positive supply voltage (V

) connected between OUTPUT pin and a

PU

) like the +5 V line used to

PU

Open Load detection in off state

VND830LSP

supply the micropro cessor. The exter na l res i stor ha s to be s ele ct ed ac cor d ing t o th e follow i n g re quiremen ts:

)

1) no fal s e ope n l oad in dica t ion w he n l oad is conn ec ted: in this c ase we ha ve to av oid V

V

; this results in the following condition

Olmin

V

=(VPU/(RL+RPU))RL<V

OUT

Olmin.

2) no misdetection when load is disconnected: in this

case the V

has to be higher than V

OUT

results in the following condition R I

.

L(off2)

Beca us e I

may si gn ifi c a ntly incr ea se if V

s(OFF)

high (up t o several mA ), the pul l-up resi stor R be conne cted t o a su pp ly t ha t is swit ch ed OFF when t h e

module is in standby. The values of V

OLmin

, V

OLmax

and I

the Electrical Characteristi cs section.

to be high er tha n

OUT

<(V

PU

are available in

L(off2)

; this

OLmax

PU–VOLma x

is pulled

out

should

PU

)/

INPUT

STATUS

DRIVER

+

LOGIC

V batt. VPU

CC

V

OUT

+

R

-

OL

V

GROUND

L(off2)

I

PU

R

L

R

9/18

VND830LSP

Off State Output Current

IL(off1)

1.35

1.2

1.05

0.9

0.75

0.6

0.45

0.3

0.15

0

-50 -25 0 25 50 75 100 125 150 175

Off State Vcc=13V

Vin=Vout=0V

High Level Input Current

Iih (µA)

6

5.25

4.5

3.75

2.25

1.5

0.75

Vin=3.25V

3

0

-50 -25 0 25 50 75 100 125 150 175

Tc (ºC)

Input Clamp Voltage Status Leakage Current

Vicl (V)

8

7.75

7.5

7.25

7

6.75

6.5

6.25

6

Iin=1mA

-50 -25 0 25 50 75 100 125 150 175

Tc (ºC)

Ilstat (µA)

0.07

0.06

Vstat=5V

0.05

0.04

0.03

0.02

0.01

0

-50 -25 0 25 50 75 100 125 150 175

Tc ( º C)

Tc (ºC)

10/18

1

Vstat (V)

0.8

0.7

0.6

0.5

0.4

0.3

0.2

Istat=1.6mA

0.1

0

-50 -25 0 25 50 75 100 125 150 175

Tc (ºC)

Status Clamp VoltageStatus Low Output Voltage

Vscl (V)

8

7.75

7.5

7.25

6.75

6.5

6.25

Istat=1mA

7

6

-50 -25 0 25 50 75 100 125 150 175

Tc ( º C)

VND830LSP

On State Resistance Vs T

Ron (mOhm)

100

90

80

70

60

50

40

30

20 10

0

Iol (A)

1.75

1.5

1.25

0.75

0.5

0.25

Iout=2A

Vcc=13V

-50 -25 0 25 50 75 100 125 150 175

2

Vin=5V

1

0

-50 -25 0 25 50 75 100 125 150 175

case

Tc ( º C)

On State Resistance Vs V

Ron (mOhm)

160

140

120

100

80

60

40

20

0

Iout=2A

0 5 10 15 20 25 30 35 40

Vcc (V)

Input High LevelOpenload On State Detection Threshold

Vih (V)

4

3.8

3.6

3.4

3.2

3

2.8

2.6

2.4

2.2 2

-50 -25 0 25 50 75 100 125 150 175

CC

Tc=150ºC

Tc=25ºC

Tc= -40ºC

Tc (ºC)

Vil (V)

2.25

2.125

2

1.875

1.75

1.625

1.5

1.375

1.25

-50 -25 0 25 50 75 100 125 150 175

Tc ( º C)

Input Hysteresis VoltageInput Low Level

Vihyst (V)

1.4

1.3

1.2

1.1

1

0.9

0.8

0.7

0.6

0.5

-50 -25 0 25 50 75 100 125 150 175

Tc (ºC)

11/18

1

VND830LSP

Overvoltage Shutdown

Vov

50

47.5

45

42.5

40

37.5

35

32.5

30

-50 -25 0 25 50 75 100 125 150 175

Tc (ºC)

Openload Off State Voltage Detection Threshold

Vol (V)

5

4.5

4

3.5

3

2.5

2

1.5

1

0.5 0

Vin=0V

-50 -25 0 25 50 75 100 125 150 175

Turn-on Voltage Slope Turn-off Voltage Slope

dVout/dt(on) (V/ms)

800

700

600

500

400

Vcc=13V

Rl=6.5Ohm

dVout/dt(off) (V/ms)

800

700

600

500

400

Vcc=13V

Rl=6.5Ohm

Tc ( º C)

I

LIM

300

200

100

0

-50 -25 0 25 50 75 100 125 150 175

Tc ( º C)

Vs T

case

Ilim (A)

35

32.5

30

27.5

25

22.5

20

17.5

15

12.5 10

Vcc=13V

-50 -25 0 25 50 75 100 125 150 175

Tc (ºC)

300

200

100

0

-50 -25 0 25 50 75 100 125 150 175

Tc ( º C)

12/18

1

Maximum turn off current versus load inductance

LMAX (A)

I

100

10

VND830LSP

A

B C

1

0.01 0.1 1 10 100

A = Single Pulse at T

B= Repetitive pulse at T C= Repetitive Pulse at T

Conditions: VCC=13.5V

Values are generated with RL=0Ω In case of repetitive pulses, T

the temperature specified above for curves B and C.

VIN, I

L

=150ºC

Jstart

=100ºC

Jstart

=125ºC

Jstart

jstart

Demagnetization

(at beginning of each demagnetization) of every pulse must not exceed

L(mH)

Demagnetization

t

13/18

1

VND830LSP

PowerSO-10™ PC Board

PowerSO-10™ THERMAL DATA

R

thj-amb

Layout condition of Rth and Zth measurements (PCB FR4 a rea= 58mm x 58mm, PCB thickness =2mm, Cu thickness=35µm, Copper areas: from minimum pad lay-out to 8cm

Vs PCB copper area in open box free air condition

2

).

RTHj_amb (°C/W)

55

Tj-Tamb=50°C

50

45

40

35

14/18

30

0246810

PCB Cu heatsink area (cm^2)

PowerSO-10 Thermal Impedance Junction Ambient Single Pulse

ZTH (°C/W)

1000

VND830LSP

100

10

1

0.1

0.0001 0.001 0.01 0.1 1 10 100 1000

Time (s)

Thermal fitting model of a d ouble channe l HSD in PowerSO-10

Pulse calculation formula

Z

THδ

where

RTHδ Z

δ tpT⁄=

THtp

2

0.5 cm

2

6 cm

1 δ–()+⋅=

Tj_1

Pd1

Tj_2

C1

C1 C2

R1

Pd2

Thermal Parameter

C3 C4

R3R1 R6R5R2

R2

T_amb

C5 C6C2

R4

Area/island (cm2)0.56

R1 (°C/W) 0.15 R2 (°C/W) 0.8 R3( °C/W) 0.7 R4 (°C/W) 0.8 R5 (°C/W) 12 R6 (°C/W) 37 22 C1 (W.s/°C) 0.0006 C2 (W.s/°C) 2.10E-03 C3 (W.s/°C) 0.013 C4 (W.s/°C) 0.3 C5 (W.s/°C) 0.75 C6 (W.s/°C) 3 5

15/18

VND830LSP

PowerSO-10™ MECHANICAL DATA

DIM.

MIN. TYP MAX. MIN. T YP. MAX.

mm. inch

A 3.35 3.65 0.132 0.144

A (*) 3.4 3.6 0.134 0.142

A1 0.00 0.10 0.000 0.004

B 0.40 0.60 0.016 0.024

B (*) 0.37 0.53 0.014 0.021

C 0.35 0.55 0.013 0.022

C (*) 0.23 0.32 0.009 0.0126

D 9.40 9.60 0.370 0.378

D1 7.40 7.60 0.291 0.300

E 9.30 9.50 0.366 0.374

E2 7.20 7.60 0.283 300

E2 (*) 7.30 7.50 0.287 0.295

E4 5.90 6.10 0.232 0.240

E4 (*) 5.90 6.30 0.232 0.248

e 1.27 0.050 F 1.25 1.35 0.049 0.053

F (*) 1.20 1.40 0.047 0.055

H 13.80 14.40 0.543 0.567

H (*) 13.85 14.35 0.545 0.565

h 0.50 0.002 L 1.20 1.80 0.047 0.070

L (*) 0.80 1.10 0.031 0.043

α 0º 8º 0º 8º

α (*) 2º 8º 2º 8º

(*) Muar only POA P013P

16/18

HE

h

A

F

A1

10

1

eB

0.25

D

= =

D1

= =

E2

DETAIL "A"

B

0.10 A

E

SEATING

PLANE

A

C

α

B

E4

SEATING

PLANE

A1

L

P095A

111

1

VND830LSP

PowerSO-10™ SUGGESTED PAD LAYOUT

14.6 - 14.9

10.8 - 11

6.30

0.67 - 0.73 1 2 3

9.5 4

5

10

0.54 - 0.6

9 8 7

1.27

6

TAPE AND REEL SHIPMENT (suffix “13TR”)

TUBE SHIPMENT (no suffix)

C

A

B

A

All dimensi ons ar e in mm.

Base Q.ty Bulk Q.ty Tube length (± 0.5) A B C (± 0.1)

Casablanca 5 0 1000 532 10.4 16. 4 0.8

Muar 50 1000 532 4.9 1 7.2 0.8

MUARCASABLANCA

B

REEL DIMENSIONS

Base Q.ty 600 Bulk Q.ty 600 A (max) 330 B (min) 1.5 C (± 0.2) 13

F 20.2 G (+ 2 / -0) 24.4 N (min) 60 T (max) 30.4

C

TAPE DIMENSIONS

According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb 1986

Tape width W 24 Tape Hole Spacing P0 (± 0.1) 4 Component Spacing P 24 Hole Diameter D (± 0.1/-0) 1.5 Hole Diameter D1 (min) 1.5 Hole Position F (± 0.05) 11.5 Compartm ent Depth K (max) 6.5 Hole Spacing P1 (± 0.1) 2

All dimensions are in mm.

Top

cover

tape

End

500mm min

All dimensions are in mm.

Empty components pockets saled with cover tape.

User direction of feed

Start

No componentsNo components Components

500mm min

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VND830LSP

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