Datasheet VIPER100SP, VIPER100ASP, VIPER100A, VIPER100 Datasheet (SGS Thomson Microelectronics)

VIPer100/SP

VIPer100A/ASP

SMPS PRIMARY I.C.

May 1999

BLOCK DIAGRAM

TYPE V

DSS

I

n

R

DS(on)

VI Per 1 00/ SP 620V 3 A 2.5 Ω
VI Per 1 00A /ASP 700V 3 A 2.8 Ω

FEATURE

■ ADJUSTABLESWITCHINGFREQUENCYUP

TO200KHZ

■ CURRENT MODE CONTROL

■ SOFTSTART AND SHUT DOWN CONTROL

■ AUTOMATIC BURST MODE OPERATION IN

STAND-BY CONDITIONABLE TO MEET
”BLUE ANGEL” NORM (<1W TOTAL POWER
CONSUMPTION)

■ INTERNALLY TRIMMEDZENER

REFERENCE

■ UNDERVOLTAGE LOCK-OUT WITH

HYSTERESIS

■ INTEGRATED START-UPSUPPLY

■ AVALANCHERUGGED

■ OVERTEMPERATURE PROTECTION

■ LOW STAND-BYCURRENT

■ ADJUSTABLECURRENTLIMITATION

DESCRIPTION

VIPer100/100A, made using VIPower M0
Technology, combines on the same silicon chip a
state-of-the-art PWM circuit together with an
optimized high voltage avalanche rugged Vertical
Power MOSFET (620Vor 700V / 3A).

Typical applications cover off line power supplies
with a secondary power capability of 50W in wide
range condition and 100Win singlerange or with
doubler configuration. It is compatible from both
primary or secondary regulation loop despite
using around 50% less components when
compared with a discrete solution. Burst mode
operation is an additional feature of this device,
offering the possibility to operate in stand-by
mode without extra components.

PowerSO-10

1

10

PENTAWATTHV PENTAWATT HV

(022Y)

F

C

0

0

2

3

1

V

DD

OSC

COMP

DRAIN

SOURCE

13 V

UVLO

LOGIC

SECURITY

LATCH

PWM

LATCH

FF

FF

R/SSQ

S

R1

R2 R3

Q

OSCILLATOR

OVERTEMP.

DETECTOR

ERROR

AMPLIFIER

_
+

0.5 V +
_

1.7

µ

s

DELAY

250 ns

BLANKING

CURRENT

AMPLIFIER

ON/OFF

0.5V
1V/A

_

+

+
_

4.5 V



1/20

ABSOLUTEMAXIMUM RATING

Symb o l Para met er Val u e Uni t

V

DS

Continuous Drain-Sour ce Voltage (Tj = 2 5 to 125oC)
for VIPer100/SP
for VIPer100A/ASP

-0.3 to 620

-0.3 to 700

V
V

I

D

Maximum Current Inte rnally Li mited A

V

DD

Supply Volt age 0 to 15 V

V

OSC

Volt age Range Input 0 t o V

DD

V

V

COMP

Volt age Range Input 0 t o 5 V

I

COMP

Maximum Continuous Curre nt ±2mA

V

esd

Elect r o st at ic discharge (R = 1.5 KΩ C = 100pF) 4000 V

I

D(AR)

Avalanche Drain-Sour ce Curr e nt , Repetitive or Not-Repetit iv e
(T

C

=100oC, Pulse Width Limited by TJmax, δ <1%)
for VIPer100/SP
for VIPer100A/ASP

2

1.4

A
A

P

tot

Power Dissipation at Tc = 25oC82W

T

j

Junction Operating Tempe r at ure Int ernally Limited

o

C

T

stg

St orage T emperature -65 to 150

o

C

THERMALDATA

PENTAWATT-HV PowerSO-10(*)

R

thj-case

Ther mal Res istance Junc ti on-case Max 1.4 1.4

o

C/W

R

thj-a mb.

Ther mal Res istance Ambient-case Max 60 50

o

C/W

(*) When mounted using the minimum recommended pad size on FR-4 board.

CURRENT AND VOLTAGE CONVENTIONS

­+

13V

OSC

COMP SOURCE

DRAINVDD

VCOMP

V

OSC

V

DD

VDS

ICOMP

I

OSC

IDD ID

FC00020

CONNECTION DIAGRAMS(Top View)

PENTAWATTHV PENTAWATT HV (022Y) PowerSO-10

VIPer100/SP -VIPer100A/ASP

2/20

PINSFUNCTIONAL DESCRIPTION
DRAINPIN:

Integrated power MOSFET drain pin. It provides
internal bias current during start-up via an
integrated high voltage current source which is
switched off during normal operation.The device
is able to handle an unclamped current during its
normal operation, assuring self protection against
voltage surges, PCB stray inductance, and
allowing a snubberless operation for low output
power.

SOURCEPIN:

Power MOSFET source pin. Primary side circuit
commonground connection.

VDD PIN :

This pin providestwo functions:

- It corresponds to the low voltage supply of the

controlpart of the circuit. If V

DD

goes below 8V,
the start-up current source is activated and the
output power MOSFET is switched off untilthe
V

DD

voltage reaches 11V. During this phase,
the internal current consumption is reduced,
the V

DD

pin is sourcing a current of about 2mA
and the COMP pin is shorted to ground. After
that, the current source is shut down, and the
devicetries to startup by switching again.

- This pin is also connected to the error

amplifier, in order to allow primary as well as
secondary regulation configurations. In caseof
primary regulation, an internal 13V trimmed
reference voltage is used to maintain V

DD

at
13V. For secondary regulation, a voltage
between 8.5V and 12.5V will be put on V

DD

pin
by transformer design, in order to stuck the
output of the transconductanceamplifier to the
high state. The COMP pin behaves as a

constant current source, and can easily be
connected to the output of an optocoupler.
Note that any overvoltage due to regulation
loop failure is still detected by the error
amplifier through the V

DD

voltage, which
cannot overpass 13V. The output voltage will
be somewhathigher thanthe nominalone, but
still undercontrol.

COMP PIN :

This pin provides two functions :

- It is the output of the error transconductance

amplifier, and allows for the connection of a
compensation network to provide the desired
transfer function of the regulation loop. Its
bandwidth can be easily adjusted to the
needed value with usual componentsvalue. As
stated above, secondary regulation
configurations are also implemented through
the COMPpin.

- When the COMP voltage is going below 0.5V,

the shut-downof the circuit occurs, with a zero
duty cycle for thepower MOSFET. This feature
can be used to switch off the converter, and is
automatically activated by the regulation loop
(whatever is the configuration) to provide a
burst mode operation in case of negligible
output power or openload condition.

OSC PIN :

An R

T-CT

network must be connected on that pin
to define the switching frequency. Note that
despite the connection of R

T

to VDD,no

significant frequency change occurs for V

DD

varying from 8V to 15V. It provides also a
synchronisationcapability, when connected to an
external frequencysource.

ORDERING NUMBERS

PENTAW AT T HV PENT AWAT T HV ( 022Y) PowerSO- 10

VI Per 100

VI Per 1 00A

VIP er 100 (022Y)

VIPer100A (022Y)

VIPe r 100SP

VIPer100ASP

VIPer100/SP - VIPer100A/ASP

3/20

AVALANCHE CHARACTERISTICS

Symb o l Para met er Max Valu e Uni t

I

D(ar)

Avalanche Current , Repetit ive or Not-Repet it ive
(pulse widt h limited by T

j

max, δ <1%)
for VIPer100/SP
for VIPer100A/ASP (see f ig.12)

2

1.4

A
A

E

(ar)

Single Pulse Avalanche Ener g y
(starti ng T

j

=25oC, ID=I

D(ar)

) (see fig.12)

60 mJ

ELECTRICAL CHARACTERISTICS (TJ=25oC, VDD=13 V, unless otherwisespecified)
POWERSECTION

Symb o l Paramet er Test Con d it i ons Mi n . Typ . Max. Unit

BV

DSS

Drain-Source Voltage ID=1mA V

COMP

=0V
for VIPer100/SP
for VIPer100A/ASP (se e f ig. 5)

620
700

V
V

I

DSS

Of f - State Drain Curr ent V

COMP

=0V TJ=125oC

V

DS

= 620 V for V I Per100/SP

V

DS

= 700 V for V I Per100A/AS P

1
1

mA
mA

R

DS(on)

St at ic Drain Source on
Resistance

ID=2A
for VIPer100/SP
for VIPer100A/ASP
I

D

=2A TJ= 100oC
for VIPer100/SP
for VIPer100A/ASP

2.0

2.3

2.5

2.8

4.5

5.0

Ω
Ω

Ω
Ω

t

f

Fall T ime ID = 0.2 A Vin=300V(1)

(see f ig.3)

100 ns

t

r

Rise Time ID=2A Vin= 300 V (1)

(see f ig. 3)

50 ns

C

OSS

Out put Capacitance VDS= 25 V 150 pF

(1) On Inductive Load, Clamped.

SUPPLY SECTION

Symb o l Paramet er Test Con d it i ons Mi n . Typ . Max. Unit

I

DDch

St art - u p Charging
Current

VDD=5V VDS=70V
(see fig. 2 and fig . 15)

-2 mA

I

DD0

Oper at i ng Supply Current VDD=12V, FSW=0KHz

(see f ig. 2)

12 16 mA

I

DD1

Oper at i ng Supply Current VDD=12V, FSW= 100 KHz 15.5 mA

I

DD2

Oper at i ng Supply Current VDD=12V, FSW=200KHz 19 mA

V

DDo f f

Undervoltage Shutdown (see fig. 2) 8 V

V

DDo n

Undervoltage Reset (see fig. 2) 11 12 V

V

DDhyst

Hysteresis Start-up (see f ig. 2) 2.4 3 V

VIPer100/SP -VIPer100A/ASP

4/20

ELECTRICAL CHARACTERISTICS (continued)
OSCILLATORSECTION

Symb o l Paramet er Test Con d it i ons Mi n . Typ . Max. Unit

F

SW

Os cillator Frequency
Total Variation

RT= 8.2 K

Ω

CT=2.4 nF

V

DD

= 9 to15 V

with R

T

± 1% CT ± 5%

(see fig. 6 and fig . 9)

90 100 110 KHz

V

OSCih

Os cillator Peak Voltage 7.1 V

V

OSCil

Os cillator Valley V o lt age 3.7 V

ERRORAMPLIFIERSECTION

Symbol Parameter Test Cond ition s Min. Typ. Max. Unit

V

DDreg

VDDReg ulation Point I

COMP

= 0 mA (se e fig.1) 12. 6 13 1 3. 4 V

∆V

DDreg

Total Variation TJ= 0 to 100oC2%

G

BW

Unity Gain Bandwidt h From Input = VDDto Output = V

COMP

COM P pin i s open (see fig. 10 )

150 KHz

A

VOL

Open Loop Voltage
Gain

COM P pin i s open (see fig. 10 ) 45 52 dB

G

m

DC Transc onductance V

COMP

= 2.5 V (see fig. 1) 1.1 1.5 1.9 mA/V

V

COMPLO

Out put Low Level I

COMP

=-400µAVDD=14V 0.2 V

V

COMPHI

Out put High L ev el I

COMP

= 400 µAVDD=12V 4.5 V

I

COMPLO

Out put Low Current
Capability

V

COMP

=2.5V VDD= 14 V -600 µA

I

COMPHI

Out put High C ur rent
Capability

V

COMP

=2.5V VDD= 12 V 600 µA

PWM COMPARATORSECTION

Symbol Parameter Test Cond ition s Min. Typ. Max. Unit

H

ID

∆V

COMP

/∆I

Dpeak

V

COMP

= 1 to 3 V 0.7 1 1.3 V/A

V

COMPoffVCOMP

off s et I

Dpeak

=10mA 0.5 V

I

Dpeak

Peak Current Limitation VDD=12V COMPpinopen 3 4 5.3 A

t

d

Current Sense Delay
to turn-off

ID= 1 A 250 ns

t

b

Blanking Time 250 360 ns

t

on(min)

Minimum on Time 350 ns

SHUTDOWNAND OVERTEMPERATURESECTION

Symbol Parameter Test Cond ition s Min. Typ. Max. Unit

V

COMPth

Restart threshold (see fig. 4) 0.5 V

t

DISsu

Disable Set Up Time (see fig. 4) 1.7 5 µs

T

tsd

Ther mal Shut down
Tem perature

(see fig. 8 ) 140 170

o

C

T

hyst

Ther mal Shut down
Hyst eresis

(see fig. 8 ) 40

o

C

VIPer100/SP - VIPer100A/ASP

5/20

Figure1:VDDRegulationPoint

I

COMP

ICOMPHI

ICOMPLO

VDDreg

0

V

DD

Slope =

Gm in mA/V

FC00150

Figure3: TransitionTime

ID

VDS

t

t

tf tr

10%Ipeak

10%V

D

90%VD

FC00160

Figure2: UndervoltageLockout

V

DDon

IDDch

IDD0

VDD

V

DDoff

VDS=70V

Fsw = 0

IDD

VDDhyst

FC00170

Figure4: ShutDown Action

VCOMP

VOSC

ID

t

tDISsu

t

t

ENABLE

DISABLE

ENABLE

VCOMPth

FC00060

Figure5: BreakdownVoltagevs Temperature Figure 6: Typical FrequencyVariation

Temperature (°C)

FC00180

0 20 40 60 80 100 120

0.95

1

1.05

1.1

1.15

BV

DSS

(Normalized)

Temperature (°C)

0 20 40 60 80 100 120 140

-5

-4

-3

-2

-1

0

1

FC00190

(%)

VIPer100/SP -VIPer100A/ASP

6/20

Figure8: OvertemperatureProtection

t

t

t

t

Tj

Vdd

Id

Vcomp

Ttsd

Ttsd-Thyst

Vddon
Vddoff

SC10191

Figure7: Start-upWaveforms

VIPer100/SP - VIPer100A/ASP

7/20

Figure9: Oscillator

1 2 3 5 10 20 30 50

30

50

100

200

300

500

1,000

Rt (kΩ)

Frequency (kHz)

Oscillatorfrequency vs Rt and Ct

Ct = 1.5 nF

Ct = 2.7nF

Ct = 4.7nF

Ct = 10nF

FC00030FC00030

1 2 3 5 10 20 30 50

0.5

0.6

0.7

0.8

0.9

1

Rt (kΩ)

Dmax

Maximum duty cycle vs Rt

FC00040

Rt

Ct

OSC

VDD

~360Ω

CLK

FC00050

For RT> 1.2 KΩ:
F

SW

=

2.3

R

TCT

D

MAX

D

MAX

= 1 −

550

R

T

− 150

RecommendedD

MAX

values:
100KHz: > 80%
200KHz: > 70%

VIPer100/SP -VIPer100A/ASP

8/20

Figure10: ErrorAmplifierFrequency Response

0.001 0.01 0.1 1 10 100 1,000

(20)

0

20

40

60

Frequency (kHz)

VoltageGain (dB)

RCOMP= +∞
RCOMP= 270k
RCOMP= 82k

RCOMP= 27k
RCOMP= 12k

FC00200

Figure11: ErrorAmplifierPhase Response

0.001 0.01 0.1 1 10 100 1,000

(50)

0

50

100

150

200

Frequency (kHz)

Phase (°)

RCOMP= +∞
RCOMP= 270k

RCOMP= 82k

RCOMP= 27k
RCOMP= 12k

FC00210

VIPer100/SP - VIPer100A/ASP

9/20

Figure12: AvalanceTest Circuit

FC00195

U1
VIPer100

13V

OSC

COMP SOURCE

DRAINVDD

­+

23

54

1

R3
100

R2
1k

BT2
12V

C1
47uF
16V

Q1
2 x STHV102FIin parallel

R1

47

L1
1mH

GENERATORINPUT

500us PULSE

BT1
0 to 20V

VIPer100/SP -VIPer100A/ASP

10/20

Figure13: OffLine Power Supply With Auxliary Supply Feedback

AC IN

+Vcc

GND

F1

BR1

D3

R9

C1

R7

C4

C2

TR2

R1

C3

D1

D2

C10

TR1

C9C7

L2

R3

C6

C5

R2

U1

VIPer100

­+

13V

OSC

COMP SOURCE

DRAINVDD

FC00081

C11

Figure14: OffLine Power Supply With OptocouplerFeedback

FC00091

AC IN

F1

BR1

D3

R9

C1

R7

C4

C2

TR2

R1

C3

D1

D2

C10

TR1

C9C7

L2

+Vcc

GND

C8

C5

R2

U1

VIPer100

U2

R4

R5

ISO1

R6

R3

C6

­+

13V

OSC

COMP SOURCE

DRAINVDD

C11

VIPer100/SP - VIPer100A/ASP

11/20

OPERATIONDESCRIPTION:
CURRENT MODE TOPOLOGY:

The current mode control method, like the one
integrated in the VIPer100/100Auses two control
loops - an inner current control loop andan outer
loop for voltage control. When the Power
MOSFET output transistor is on, the inductor
current (primary side of the transformer) is
monitored with a SenseFET technique and
converted into a voltage V

S

proportional to this

current. When V

S

reaches V

COMP

(the amplified
output voltage error) the powerswitch is switched
off. Thus, the outer voltage control loop defines
the level at which the inner loop regulates peak
current through the powerswitch and theprimary
windingof the transformer.

Excellent open loop D.C. and dynamic line
regulation is ensured due to the inherent input
voltage feedforward characteristic of the current
mode control. This results in an improved line
regulation, instantaneous correction to line
changes and better stability for the voltage
regulationloop.

Current mode topology also ensures good
limitation in the case of short circuit. During a first
phase the output current increases slowly
followingthe dynamic of the regulationloop. Then
it reaches the maximum limitation current
internally set and finally stops because the power
supply on V

DD

is no longer correct. For specific
applications the maximum peak current internally
set can be overridden by externally limiting the
voltage excursion on the COMP pin. An
integrated blanking filter inhibits the PWM
comparator output for a short time after the
integrated Power MOSFET is switched on. This
function prevents anomalous or premature
termination of the switching pulse in the case of
current spikes caused by primary side
capacitance or secondary side rectifier reverse
recovery time.

STAND-BY MODE

Stand-by operation in nearly open load condition
automatically leads to a burst mode operation
allowing voltage regulation on the secondary
side. The transition from normal operation to
burst mode operation happens for a power P

STBY

given by :
P

STBY

=

1
2

L

PISTBY

2

F

SW

Where:
L

P

isthe primaryinductance of the transformer.

F

SW

is the normal switching frequency.

I

STBY

is the minimum controllable current,
corresponding to the minimum on time that the
deviceis able to provide in normal operation.This
current can be computed as :

I

STBY

=

(t

b

+ td) V

IN

L

P

tb+tdis the sum of the blanking time and of the
propagation time of the internal current sense
and comparator, and represents roughly the
minimum on time of the device. Note that P

STBY

may be affectedby the efficiencyof the converter
at low load, and must include the power drawn on
the primary auxiliaryvoltage.

As soon as the power goes below this limit, the
auxiliary secondary voltage starts to increase
above the 13V regulation level forcing the output
voltage of the transconductance amplifier to low
state (V

COMP

<V

COMPth

). This situation leads to
the shutdown mode where the power switch is
maintained in the off state, resulting in missing
cycles and zero duty cycle. As soon as V

DD

gets

back to the regulation level and the V

COMPth

threshold is reached, the device operates again.
The above cycle repeats indefinitely, providing a
burst mode of which the effective duty cycle is
much lower than the minimum one when in
normal operation. The equivalent switching
frequency is also lower than the normal one,
leading to a reduced consumption on the input
mains lines. This mode of operation allows the
VIPer100/100A to meet the new German ”Blue
Angel” Norm with less than 1W total power
consumption for the system when working in
stand-by. The output voltage remains regulated
around the normal level, with a low frequency
ripple corresponding to the burst mode. The
amplitude of this ripple is low, because of the
output capacitors and of the low output current
drawn in such conditions.The normal operation
resumes automatically when the power get back
to higher levels than P

STBY

.

HIGH VOLTAGE START-UP CURRENT
SOURCE

An integrated high voltage current source
provides a bias current from the DRAIN pin
during the start-up phase. This current is partially
absorbed by internal control circuits which are

VIPer100/SP -VIPer100A/ASP

12/20

placed into a standby mode with reduced
consumption and also provided to the external
capacitor connected to the V

DD

pin. As soon as
the voltage on this pin reaches the high voltage
threshold V

DDon

of the UVLO logic, the device
turns into active mode and starts switching. The
start up current generatoris switched off, and the
converter should normally provide the needed
current on the V

DD

pin through the auxiliary

winding of the transformer, as shown on figure

15.
In case of abnormal condition where the auxiliary

winding is unable to provide the low voltage
supply current to the V

DD

pin (i.e. short circuit on
the output of the converter), the external
capacitor discharges itself down to the low
threshold voltage V

DDoff

of the UVLO logic, and
the device get back to the inactive state where
the internal circuits are in standby mode and the
start up current source is activated. The converter
enters a endless start up cycle, with a start-up
duty cycle definedby theratio of charging current
towards discharging when the VIPer100/100A
tries to start. This ratio is fixed by design to 2 to
15, which gives a 12% start up duty cycle while
the power dissipation at start up is approximately

0.6 W, for a 230 Vrms input voltage. This low
value of start-upduty cycleprevents the stressof
the output rectifiers and of the transformer when

in short circuit.
The external capacitor C

VDD

on the VDDpin must
be sized according to the time needed by the
converter to start up, when the device starts
switching. This time t

SS

depends on many
parameters, among which transformer design,
output capacitors, soft start feature and
compensation network implemented on the
COMP pin. The following formula can beused for
definingthe minimum capacitor needed:

C

VDD

>

I

DDtSS

V

DDhyst

where:
I

DD

is the consumption current on the VDDpin

when switching. Refer to specified I

DD1

and I

DD2

values.
t

SS

is the start up time of the converter when the
device begins to switch. Worst case is generally
at full load.

V

DDhyst

is the voltage hysteresis of the UVLO

logic. Refer to theminimumspecified value.
Soft start feature can be implemented on the

COMP pin through a simple capacitor which will
be also used as the compensation network. In
this case, the regulation loop bandwidth is rather
low, because of the large value of this capacitor.
In case a large regulation loop bandwidth is
mandatory, the schematics of figure 16 can be

Figure15: Behaviourof the high voltagecurrent source at start-up

Ref.

UNDERVOLTAGE
LOCK OUT LOGIC

15 mA1mA

3mA

2mA

15 mA

VDD

DRAIN

SOURCE

VIPer100

Auxiliaryprimary

winding

VDD

t

VDDoff

VDDon

Start up duty cycle ~ 12%

C

VDD

FC0010 0

VIPer100/SP - VIPer100A/ASP

13/20

used. It mixes a high performance compensation
network together with a separate high value soft
start capacitor. Both soft start time and regulation
loop bandwidth can be adjustedseparately.

If the device is intentionally shut down by putting
the COMP pin to ground, the device is also
performingstart-up cycles, and the V

DD

voltage is

oscillatingbetween V

DDon

and V

DDoff

. This voltage
can be used for supplying external functions,
provided that their consumption doesn’t exceed

0.5mA. Figure 17 shows a typical application of
this function, with a latchedshut down. Once the
”Shutdown” signal has been activated, the device
remains in the off state until the input voltage is
removed.

TRANSCONDUCTANCE ERROR AMPLIFIER

The VIPer100/100Aincludes a transconductance
error amplifier. Transconductance Gm is the
change in output current (I

COMP

) versus change

in input voltage(V

DD

). Thus:

G

m

=

∂

I

COMP

∂ V

DD

The output impedance Z

COMP

at the output of this

amplifier (COMP pin) can be defined as:
Z

COMP

=

∂V

COMP

∂ I

COMP

=

1

G

m

x

∂ V

COMP

∂ V

DD

This last equation shows that the open loop gain
A

VOL

canbe related to GmandZ

COMP

:

A

VOL=GmxZCOMP

where Gmvalue for VIPer100/100A is 1.5 mA/V
typically.

G

m

is well defined by specification, but Z

COMP

and therefore A

VOL

are subject to large
tolerances. An impedance Z can be connected
between the COMP pin and ground in order to
define more accurately the transfer function F of
the error amplifier, according to the following
equation,very similar to the one above:

F

(S)

=Gm x Z(S)

The error amplifier frequency response is
reported in figure 10 for different values of a
simple resistance connected on the COMP pin.
The unloaded transconductance error amplifier
shows an internal Z

COMP

of about 330 KΩ. More
complex impedance can be connected on the
COMP pin to achieve different compensation
laws. A capacitor will provide an integrator
function, thus eliminating the DC static error, and
a resistance in series leads to a flat gain at higher
frequency, insuring a correct phase margin. This
configurationis illustrated on figure18.

As shown in figure18 an additional noise filtering
capacitor of 2.2 nF is generally needed to avoid
any highfrequencyinterference.

It can be also interesting to implement a slope
compensation when working in continuous mode
with duty cycle higher than 50%.Figure 19 shows
such a configuration. Note that R1 and C2 build
the classical compensation network, and Q1 is
injecting the slope compensation with the correct
polarity from the oscillator sawtooth.

EXTERNALCLOCK SYNCHRONIZATION:

The OSC pin provides a synchronisation
capability, when connected to an external
frequency source. Figure 20 shows one possible

Figure17: Latched Shut Down

-

+

13V

OSC

COMP SOURCE

DRAINVDD

VIPER100

Shutdown

U1

Q1

Q2

R1

R2R3

R4

D1

FC00110

Figure16: Mixed Soft Startand Compensation

AUXILIARY
WINDING

-

+

13V

OSC

COMP SOURCE

DRAINVDD

U1
VIPER100

R1

C1

+

C2

D1

R2

R3

D2

D3

+

C3

FC00131

C4

VIPer100/SP -VIPer100A/ASP

14/20

schematic to be adapted depending the specific
needs. If the proposed schematic is used, the
pulse duration must be keptat a low value (500ns
is sufficient) for minimizing consumption. The
optocoupler must be able to provide 20mA
through the optotransistor.

PRIMARY PEAK CURRENT LIMITATION

The primary I

DPEAK

current and, as resulting
effect, the output power can be limited using the
simple circuit shown in figure 21. The circuit
based on Q1, R

1

and R2clamps the voltage on
the COMP pin in order to limit the primary peak
current of the device to a value:

I

DPEAK

=

V

COMP

− 0.5

H

ID

where:
V

COMP

= 0.6x

R

1

+ R

2

R

2

The suggestedvalue for R1+R2is in the range of
220KΩ.

OVER-TEMPERATUREPROTECTION:

Over-temperature protection is based on chip
temperature sensing. The minimum junction
temperature at which over-temperature cut-out
occurs is 140

o

C while the typical value is 170oC.
The device is automatically restarted when the
junction temperature decreases to the restart
temperaturethreshold that is typically 40

o

C below

the shutdownvalue (see figure 8).

Figure19: SlopeCompensation

FC00141

­+

13V

OSC

COMP SOURCE

DRAINVDD

VIPER100

R1R2

Q1

C2

C1 R3

U1

C3

-

+

13V

OSC

COMP SOURCE

DRAINVDD

VIPER100

U1

R1

C1

FC00121

C2

Figure18: TypicalCompensation Network

­+

13V

OSC

COMP SOURCE

DRAINVDD

U1
VIPER100

10 k

Ω

FC00220

Figure20:ExternalClock Synchronization Figure 21:Current Limitation CircuitExample

­+

13V

OSC

COMP SOURCE

DRAINVDD

VIPER100

U1

R1

R2

Q1

FC00240

VIPer100/SP - VIPer100A/ASP

15/20

T1

U1
VIPerXX0

13V

OSC

COMP SOURCE

DRAINVDD

-

+

1

5

2

3

4

C4

C2

C5

C1

D2

R1

R2

D1

C7

C6

C3

ISO1

From input

diodesbridge

Tosecondary

filtering and load

FC00500

Figure22: Recommendedlayout

LAYOUTCONSIDERATIONS

Some simple rules insure a correct running of
switching power supplies. They may be classified
into two categories:

- To minimisepower loops: the waythe switched

power current must be carefully analysed and
the corresponding paths must present the
smallest inner loop area as possible. This
avoids radiated EMC noises, conducted EMC
noises by magnetic coupling, and provides a
better efficiency by eliminating parasitic
inductances,especially on secondaryside.

- Touse different tracksfor low level signals and

power ones. The interferencesdue to a mixing
of signal and power may result in instabilities
and/or anomalous behaviour of the device in
case of violent power surge (Input
overvoltages,output short circuits...).

In case of VIPer, these rules apply as shown on
figure 22. The loops C1-T1-U1, C5-D2-T1,
C7-D1-T1 must be minimised. C6 must be as
close as possible from T1. The signal
components C2, ISO1, C3 and C4 are using a
dedicated track to be connected directly to the
sourceof the device.

VIPer100/SP -VIPer100A/ASP

16/20

DIM.

mm inch

MIN. TYP. MAX. MIN. TYP. MAX.

A 4.30 4.80 0.169 0.189
C 1.17 1.37 0.046 0.054
D 2.40 2.80 0.094 0.110
E 0.35 0.55 0.014 0.022
F 0.60 0.80 0.024 0.031

G1 4.90 5.28 0.193 0.208
G2 7.42 7.82 0.292 0.308
H1 9.30 9.70 0.366 0.382
H2 10.40 0.409
H3 10.05 10.40 0.396 0.409

L 16.60 17.30 0.653 0.681

L1 14.60 15.22 0.575 0.599
L2 21.20 21.85 0.835 0.860
L3 22.20 22.82 0.874 0.898
L5 2.60 3.00 0.102 0.118
L6 15.10 15.80 0.594 0.622
L7 6.00 6.60 0.236 0.260

M 2.50 3.10 0.098 0.122

M1 7.56 8.16 0.298 0.321

R 0.50 0.020

V4 90

o

90

Diam. 3.70 3.90 0.146 0.154

A

C

H2

H3

H1

L5

Diam

L2

L3

L6

L7

F

G1

G2

L

L1

D

R

M

M1

E

Resin

between

leads

V4

P023H3

PENTAWATT HV (VERTICAL) MECHANICAL DATA

VIPer100/SP - VIPer100A/ASP

17/20

DIM.

mm inch

MIN. TYP. MAX. MIN. TYP. MAX.

A 4.30 4.80 0.169 0.189
C 1.17 1.37 0.046 0.054
D 2.40 2.80 0.094 0.110
E 0.35 0.55 0.014 0.022

F 0.60 0.80 0.024 0.031
G1 4.90 5.28 0.193 0.208
G2 7.42 7.82 0.292 0.308
H1 9.30 9.70 0.366 0.382
H2 10.40 0.409
H3 10.05 10.40 0.396 0.409

L 16.42 17.42 0.646 0.686
L1 14.60 15.22 0.575 0.599
L3 20.52 21.52 0.808 0.847
L5 2.60 3.00 0.102 0.118
L6 15.10 15.80 0.594 0.622
L7 6.00 6.60 0.236 0.260

M 2.50 3.10 0.098 0.122

M1 5.00 5.70 0.197 0.224

R 0.50 0.020

V4 90

o

90

o

Diam. 3.70 3.90 0.146 0.154

A

C

H2

H3

H1

L5

Diam

L3

L6

L7

F

G1

G2

L

L1

D

R

M

M1

E

Resin

between

leads

V4

P023H2

PENTAWATT HV 022Y(VERTICAL HIGH PITCH) MECHANICAL DATA

VIPer100/SP -VIPer100A/ASP

18/20

DIM.

mm inch

MIN. TYP. MAX. MIN. TYP. MAX.

A 3.35 3.65 0.132 0.144

A1 0.00 0.10 0.000 0.004

B 0.40 0.60 0.016 0.024
C 0.35 0.55 0.013 0.022
D 9.40 9.60 0.370 0.378

D1 7.40 7.60 0.291 0.300

e 1.27 0.050

E 9.30 9.50 0.366 0.374

E1 7.20 7.40 0.283 0.291
E2 7.20 7.60 0.283 0.300
E3 6.10 6.35 0.240 0.250
E4 5.90 6.10 0.232 0.240

F 1.25 1.35 0.049 0.053

h 0.50 0.002
H 13.80 14.40 0.543 0.567

L 1.20 1.80 0.047 0.071

q 1.70 0.067

α 0

o

8

o

DETAIL”A”

PLANE

SEATING

α

L

A1

F

A1

h

A

D

D1

==
==

==

E4

0.10 A

E1E3

C

Q

A

==

B

B

DETAIL”A”

SEATING
PLANE

==

==

E2

610

51

eB

HE

M

0.25

==

==

0068039-C

PowerSO-10 MECHANICAL DATA

VIPer100/SP - VIPer100A/ASP

19/20

Information furnished is believed to beaccurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are
subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products
are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

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VIPer100/SP -VIPer100A/ASP

20/20