Datasheet VG36648041BT-8, VG36648041BT-10, VG36648041BT-7 Datasheet (VIS)

0.3V

±

Preliminary VG36648041CT

VIS

Description

The device is CMOS Synchronous Dynamic RAM organized as 2,097,152 - word x 8-bit x 4-bank. it is fabricated with an advanced submicron CMOS technology and designed to operate from a singl y 3.3V only power supply. It is packaged in JEDEC standard pinout and standard plastic TSOP package.

Features

• Single 3.3V () power supply

• High speed clock cycle time : 7/8ns

• Fully synchronous with all signals referenced to a positive clock edge

• Programmable CAS Iatency (2,3)

• Programmable burst length (1,2,4,8,& Full page)

• Programmable wrap sequence (Sequential/Interleave)

• Automatic precharge and controlled precharge

• Auto refresh and self refresh modes

• Quad Internal banks controlled by A12 & A13 (Bank select)

• Each Bank can operate simultaneously and independently

• LVTTL compatible I/O interface

• Random column access in every cycle

• X8 organization

• Input/Output controlled by DQM

• 4,096 refresh cycles/64ms

• Burst termination by burst stop and precharge command

• Burst read/single write option

CMOS Synchronous Dynamic RAM

The information shown is subject to change without notice.

Document : 1G5-0153 Rev.1 Page 1

VIS

Pin Configuration

Preliminary VG36648041CT CMOS Synchronous Dynamic RAM

V

DD

DQ0 V

DDQ

NC DQ1

V

SSQ

NC DQ2 V

DDQ

NC DQ3

V

SSQ

NC V

DD

NC WE

CAS RAS CS

A13/BA0 A12/BA1

A

10

A

0

A

1

A

2

A

3

V

DD

1 2

3 4 5 6 7

8 9 10 11

12 13 14 15 16 17 18 19 20 21 22

23

24 25 26 27

VG36648041

54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28

V

SS

DQ7 V

SSQ

NC DQ6 V

DDQ

NC DQ5 V

SSQ

NC DQ4 V

DDQ

NC V

SS

NC DQM CLK

CKE NC A

11

A

9

A

8

A

7

A

6

A

5

A

4

V

SS

Pin Description VG36648041

Pin Name Function Pin Name Function

A0 - A11 A12,A13

Address inputs Bank select

DQM DQ Mask enable

DQ0 ~ DQ7 Data - in/data - out CLK Clock input RAS Row address strobe CKE Clock enable CAS Column address strobe CS Chip select WE Write enable V

V

SS

V

DD

Ground V Power ( + 3.3V)

DDQ

SSQ

Supply voltage for DQ Ground for DQ

Document : 1G5-0153 Rev.1 Page 2

VIS

Block Diagram

Preliminary VG36648041CT CMOS Synchronous Dynamic RAM

CLK CKE

Address

CS RAS CAS

WE

Clock Generator

Row Address Buffer

Mode

Register

Control Logic

Command Decoder

& Refresh Counter

Column Address Buffer

& Burst Counter

Row Decoder

Column Decoder & Latch Circuit

Data Control Circuit

Bank D

Bank C

Bank B

Bank A

Sense Amplifier

DQM

DQ

Buffer

Latch Circuit

Input & Output

Document : 1G5-0153 Rev.1 Page 3

≤

Preliminary VG36648041CT

VIS

Absolute Maximum D.C. Ratings

Voltage on any pin relative to Vss VIN, V Supply voltage relative to Vss VDD, V Short circuit output current I Power dissipation P Operating temperature T Storage temperature T

Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause

peumanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.

Maximum A.C. Operating Requirements for LVTTL Compatible

Parameter Symbol Min Max Unit Notes

Input High Voltage V Input Low Voltage V

CMOS Synchronous Dynamic RAM

Parameter Symbol Value Unit

OUT

DDQ

OUT

D OPT STG

IH

IL

2.0 V

V

-2.0

SSQ

-0.5 to + 4.6 V

-0.5 to + 4.6 V 50 mA

1.0 W

0 to + 70

-55 to + 125

+ 2.0 V 2

DDQ

0.8

V 2

°C °C

Recommended DC Operating Conditions for LVTTL Compatible

Parameter Symbol Min Typ Max Unit

Supply Voltage V Input High Voltage, all inputs V Input Low Voltage, all inputs V

DD, VDDQ

IH

IL

3.0 3.3 3.6 V

2.0

-0.3

-

V

+ 0.3 V

DD

0.8 V

Capacitance

(Ta = 25°C, f = 1MHZ)

Parameter Symbol Min Typ Max Unit Notes

Input capacitance (All input pins except CLK pin) C CLK pin C Data input/output capacitance C

Notes : 1. Capacitance measured with effective capacitance measuring method.

2. The overshoot and undershoot voltage duration is 3ns with no input clamp diodes.

in

CLK

I/O

2.5 3.75 5.0 pF 1

2.5 3.25 4.0 pF 1

4.0 5.25 6.5 pF 1

Document : 1G5-0153 Rev.1 Page 4

≤

∞

≥

∞

≤

∞≥≥≥∞≤≥

≥

≤

µA

≤

µA

Preliminary VG36648041CT

VIS

DC Characteristics (Recommended Operating Conditions unless otherwise noted)

Parameter Symbol Test Conditions

Operating current I

Precharge standby current in power down mode

Precharge standby current in Nonpower down mode

Active standby current in power down mode

Active standby current in Nonpower down mode

Operating current (Burst mode)

Refresh current I Self refresh current I

Input leakage current (Inputs)

Output leakage current (I/O pins)

Output Low Voltage V Output High Voltage V

Notes :

1. ICC1 depends on output loading and cycle rates. Specified values are obtained with the output open. In addition to this, ICC1 is measured on condition that addresses are changed only one time during t

2. ICC4 depends on output loading and cycle rates. Specified values are obtained with the output open. In addition to this, ICC4 is measured on condition that addresses are changed only one time during t

3. ICC5 is measured on condition that addresses are changed only one time during t

4. For LVTTL compatible, VG36648041.

CMOS Synchronous Dynamic RAM

VG36648041B

-7 -8 Unit Notes

Min Max Min Max

CC1

I

CC

ICC 2PS I

CC

I

CC

I

CC

I

CC

I

CC

ICC 3NS

I

CC4

CC5 t CC6

I

LI

I

IL

CK(MIN.)

OL OH

Burst length = 1 One bank active

tRC t

RC(MIN.)

2P

CKE V CKE V

2N

CKE V CS V

Input signals are changed one time during 2 CLK cycles.

2NS

CKEV CLK V

Input signals are stable.

3P

CKE V

3PS

CKE V

3N

CKE V CS V

Input signals are changed one time during 2CLKs.

CKE V CLE V

Input signals are stable. tCK t

CK(MIN.)

All banks Active

RC tRC(MIN.)

CKE 0.2V 0 VIN V

Pins not under test = 0V 0 V

OUT

DQ# in Hi - Z., Dout disabled IOL = 2mA 0.4 0.4 mA 4

IOH = -2mA 2.4 2.4 mA 4

.

, Io = 0mA

IH(MAX.) tCK

IH(MIN.) tCK

IH(MIN.)

, tCK =

IH(MIN.)

IL(MAX.)

IH(MAX.)

IH(MIN.)

IH(MIN.) tCK

IL(MAX.)

, Io = 0mA

DD(MAX)

VDD

, t , t

, t

CK

(MAX)

CL = 3 130 130 mA 1 CL = 2 130 130

= 10ns =

= 10ns.

= 10ns =

= 10ns

=

CL = 3 170 170 mA 2 CL = 2 135 120

-1 1 -1 1

-1.5 1.5 -1.5 1.5

2 2 mA 2 2

25 25 mA

10 10

7 7 mA 5 5

40 40 mA

20 20

220 200 mA 3

1 1 mA

CK(MIN.)

.

Document : 1G5-0153 Rev.1 Page 5

VIS

±

Preliminary VG36648041CT CMOS Synchronous Dynamic RAM

A. C Characteristics : (Ta = 0 to 70°C V

Test Conditions for LVTTL Compatible :

AC input Levels (VIH/VIL) 2.0/0.8V Input timing reference level/

Input rise and fall time 1ns Output load condition 50pF

AC Test Load Circuits (for LVTTL interface) :

V

DDQ

Device Under Test

V

DDQ

OUT

DD

= 3.3V 0.3V

Output timing reference level

Z = 50

Ω

SS

= 0V)

1.4V

50PF

Document : 1G5-0153 Rev.1 Page 6

VIS

Preliminary VG36648041CT CMOS Synchronous Dynamic RAM

A. C Characteristics : (Ta = 0 to 70°C V

= 3.3V 0.3V, V

DD

Parameter CAS

Latency

CLK cycle time 3 t

2 t

CLK to valid output delay 3 t

2 t CLK high pulse width t CLK low pulse width t CKE setup time t CKE hold time t Address setup time t Address hold time t Command setup time t Command hold time t Data input setup time t Data input hold time t Output data hold time t CLK to output in low - Z t CLK to output in H - Z 3 t

2 6 6

SS

symbol

ck3

ck2 Ac3 Ac2

CH

CL CKS CKH

AS

AH CMS CMH

DS

DH

OH

LZ

HZ

= 0V)

VG36648041B Unit

-7 -8

Min Max Min Max

7 8 ns

10 10 ns

6 6 ns

6 6 ns 3 3 ns 3 3 ns 2 2 ns 1 1 ns 2 2 ns 1 1 ns 2 2 ns 1 1 ns 2 2 ns 1 1 ns 3 3 ns 0 0 ns

5 6 ns

Row active to active delay t RAS to CAS delay t Row precharge time t ROW active time t ROW cycle time t Last data in to burst stop t Data - in to ACT(REF) command t

Data - in to precharge t Transition time t Mode reg. set cycle t Power down exit setup time t Self refresh exit time t Refresh time t

RRD RCD

RP

RAS

RC BDL DAL

DPL

T RSC PDE SRX REF

14 16 ns 20 20 ns 20 20 ns 40 120K 48 120K ns 60 68 ns

1 1 CLK

1+ t

RP

1+t

RP

1 1 CLK 1 10 1 10 ns 2 2 CLK 2 2 ns 1 1 CLK

64 64 ms

CLK

Document : 1G5-0153 Rev.1 Page 7

Preliminary VG36648041CT

VIS

Basic Features and Function Description

1.Simplified State Diagram

CMOS Synchronous Dynamic RAM

Mode

Register

Set

MRS

IDLE

Self

Refresh

y

r

t

n

e

F

L

t

E

S

ACT

i

x

e

F

L

E

S

REF

CKE

C

K

E

AUTO

Refresh

Power

Down

Write (Write recovery)

WRITE

SUSPEND

WRITE A

SUSPEND

CKE

Auto Precharge

CKE

Write with

CKE

WRITE A

WRITE

B

S

T

READ

READ A

Active

Power

Down

Read

CKE

Read with

Auto Precharge

CKE

READ

SUSPEND

READA

SUSPEND

ROW

ACTIVE

T

S

B

h

Write

Write recov

Read (write recovery)

A

u

P

R

E

(

P

t

i

w

ry

h

e

t

d

i

r

e

r

W

p

o

t

u

A

R

e

a

d

w

t

o

i

t

P

h

r

e

c

h

a

r

g

r

e

c

h

a

r

g

e

t

e

r

m

i

n

a

t

i

o

n

)

A

e

g

r

a

PRE

Write

W

e

A

(

w

r

i

t

e

P

CKE

Read

R

u

e

t

a

o

d

P

w

r

e

i

t

c

h

a

r

g

e

h

t

i

e

g

w

r

e

a

t

i

r

h

c

e

r

P

o

t

u

r

e

c

o

v

e

r

y

)

n

o

i

t

a

n

i

m

r

e

t

e

g

r

a

h

c

e

r

P

(

E

R

POWER

ON

Precharge

Automatic sequence

Manual input

Note: After the AUTO refresh operation, precharge operation is

performed automatically and enter the IDLE state

Document : 1G5-0153 Rev.1 Page 8

Preliminary VG36648041CT

VIS

2.Truth Table

2.1 Command Truth Table

FUNCTION Symbol Device deselect DESL H X H X X X X X X No operation NOP H X L H H H X X X Mode register set MRS H X L L L L L L V Bank activate ACT H X L L H H V V V Read READ H X L H L H V L V Read with auto precharge READA H X L H L H V H V Write WRIT H X L H L L V L V Write with auto precharge WRITA H X L H L L V H V Precharge select bank PRE H X L L H L V L X Precharge all banks PALL H X L L H L X H X Burst stop BST H X L H H L X X X CBR (Auto) refresh REF H H L L L H X X X Self refresh SELF H L L L L H X X X

CMOS Synchronous Dynamic RAM

CKE

CS RAS CAS WE BA A10

A11

A9 - A0n - 1 n

2.2 DQM Truth Table

CKE

FUNCTION Symbol Data write/output enable ENB H X L Data mask/output disable MASK H X H

2.3 CKE Truth Table

Current State Function Symbol Activating Clock suspend mode entry H L X X X X X Any Clock suspend L L X X X X X Clock suspend Clock suspend mode exit L H X X X X X Idle CBR refresh command REF H H L L L H X Idle Self refresh entry SELF H L L L L H X Self refresh Self refresh exit L H L H H H X

Idle Power down entry H L X X X X X Power down Power down exit L H X X X X X

H : High level, L : Low level

X : High or Low level (Don’t care), V : Valid Data input

n - 1 n - 1

CKE

CS RAS CAS WE

L H H X X X X

DQM

Add -

ressn - 1 n

Document : 1G5-0153 Rev.1 Page 9

VIS

→→→

Preliminary VG36648041CT CMOS Synchronous Dynamic RAM

2.4 Operative Command Table Notes 1

HCurrent state CS RAS CAS WE Address Command Action Notes Idle H X X X X DESL Nop or Power down 2

L H H X X NOP or BST Nop or Power down 2 L H L H BA, CA, A10 READ/READA ILLEGAL 3 L H L L BA, CA, A10 WRIT/WRITA ILLEGAL 3 L L H H BR, RA ACT Row active L L H L BA, A10 PRE/PALL Nop L L L H X REF/SELF Refresh or Self refresh 4 L L L L Op-Code MPS Mode register access

Row active H X X X X DESL Nop

L H H X X NOP or BST Nop L H L H BA, CA, A10 READ/READA Begin read : Determine AP 5 L H L L BA, CA, A10 WRIT/WRITA Begin write : Determine AP 5 L L H H BA, RA ACT ILLEGAL 3 L L H L BA, A10 PRE/PALL Precharge 6

(1/3)

L L L H X REF/SELF ILLEGAL L L L L Op-Code MRS ILLEGAL

Read H X X X X DESL

L H H H X NOP L H H L X BST L H L H BA, CA, A10 READ/READA Term burst, new read : Determine AP 7

L H L L BA, CA, A10 WRIT/WRITA Term burst, start write : Determine AP 7,8 L L H H BA, RA ACT ILLEGAL 3 L L H L BA, A10 PRE/PALL Term burst, precharging L L L H X REF/SELF ILLEGAL L L L L Op-Code MRS ILLEGAL

Write H X X X X DESL

L H H H X NOP L H H L X BST L H L H BA, CA, A10 READ/READA Term burst, start read : Determine AP 7,8

L H L L BA, CA, A10 WRIT/WRITA Term burst, new write : Determine AP 7

Continue burst to end Row active Continue burst to end Row active Burst stop Row active

Continue burst to end write recovering Continue burst to end write recovering Burst stop Row active

L L H H BA, RA ACT ILLEGAL 3 L L H L BA, A10 PRE/PALL Term burst, precharging 9 L L L H X REF/SELF ILLEGAL L L L L Op-Code MRS ILLEGAL

Document : 1G5-0153 Rev.1 Page 10

→

→→→→→→→

→

Preliminary VG36648041CT

VIS

CMOS Synchronous Dynamic RAM

(2/3)

Current state CS RAS CA WE Address Command Action Notes Read with auto

precharge

Write with auto precharge

Precharging H X X X X DESL

Row activating H X X X X DESL

H X X X X DESL

L H H H X NOP L H H L X BST ILLEGAL L H L H BA, CA, A10 READ/READA ILLEGAL 11 L H L L BA, CA, A10 WRIT/WRITA ILLEGAL 11 L L H H BA, RA ACT ILLEGAL 3,11 L L H L BA, A10 PRE/PALL ILLEGAL 3,11 L L L H X PEF/SELF ILLEGAL L L L L Op - Code MRS ILLEGAL

H X X X X DESL

L H H H X NOP

L H H L X BST ILLEGAL L H L H BA, CA, A10 READ/READA ILLEGAL 11 L H L L BA, CA, A10 WRIT/WRITA ILLEGAL 11 L L H H BA, RA ACT ILLEGAL 3,11 L L H L BA, A10 PRE/PALL ILLEGAL 3,11 L L L H X REF/SELF ILLEGAL L L L L Op - code MRS ILLEGAL

L H H H X NOP L H H L X BST L H L H BA, CA, A10 READ/READA ILLEGAL 3

L H L L BA, CA, A10 WRIT/WRITA ILLEGAL 3 L L H H BA, RA ACT ILLEGAL 3 L L H L BA, A10 PRE/PALL

L L L H X REF/SELF ILLEGAL L L L L Op - Code MRS ILLEGAL

L H H H X NOP L H H L X BST L H L H BA, CA, A10 READ/READA ILLEGAL 3 L H L L BA, CA, A10 WRIT/WRITA ILLEGAL 3 L L H H BA, RA ACT ILLEGAL 3,9 L L H L BA, A10 PRE/PALL ILLEGAL 3 L L L H X REF/SELF ILLEGAL L L L L Op - Code MRS ILLEGAL

Continue burst to end Precharging Continue burst to end Precharging

Continue burst to end write recovering with auto precharte

Continue burst to end write recovering with auto precharge

Nop Enter idle after t Nop Enter idle after t Nop Enter idle after t

Nop Enter idle after t

Nop Enter row active after t Nop Enter row active after t Nop Enter row active after t

RP

RCD RCD RCD

Document : 1G5-0153 Rev.1 Page 11

→→→

→→→→→

Preliminary VG36648041CT

VIS

Current CS RAS CAS WE Address Command Action Notes

CMOS Synchronous Dynamic RAM

(3/3)

Write recovering

Write recovering with auto precharge

Auto Refreshing

Mode register setting

H X X X X DESL

L H H H X NOP L H H L X BST L H L H BA, CA, A10 READ/READA Start read, Determine AP 8

L H L L BA, CA, A10 WRIT/WRITA New write, Determine AP L L H H BA, RA ACT ILLEGAL 3 L L H L BA, A10 PRE/PALL ILLEGAL 3 L L L H X PEF/SELF ILLEGAL L L L L Op - Code MRS ILLEGAL

H X X X X DESL

L H H H X NOP L H H L X BST

L H L H BA, CA, A10 READ/READA ILLEGAL 3,8,11 L H L L BA, CA, A10 WRIT/WRITA ILLEGAL 3,11 L L H H BA, RA ACT ILLEGAL 3,11 L L H L BA, A10 PRE/PALL ILLEGAL 3 L L L H X REF/SELF ILLEGAL L L L L Op - Code MRS ILLEGAL

H X X X X DESL Nop Enter idle after t

L H H X X NOP/BST Nop Enter idle after t L H L X X READ/WRIT ILLEGAL

L L H X X ACT/PRE/PALL ILLEGAL L L L X X REF/SELF/MRS ILLEGAL

H X X X X DESL

L H H H X NOP L H H L X BST ILLEGAL L H L X X READ/WRITE ILLEGAL L L X X X ACT/PRE/PALL/

REF/SELF/MRS

Nop Enter row active after t Nop Enter row active after t

Nop Enter row active after t

Nop Enter precharge after t Nop Enter precharge after t

Nop Enter precharge after t

RC RC

Nop Enter idle after 2 Clocks Nop Enter idle after 2 Clocks

ILLEGAL

DPL DPL

DPL

DPL DPL

DPL

Note:

1. All entries assume that CKE was active (High level) during the preceding clock cycle.

2. If both banks are idle, and CKE is inactive (Low level), the device will enter Power downmode. All input buffers except CKE will be disabled.

3. Illegal to bank in specified states; Function may be legal in the bank indicated by BankAddress(BA), depending on the state of that bank.

4. If both banks are idle, and CKE is inactive (Low level), the device will enter Self refresh mode.

All input buffers except CKE will be disabled.

5. Illegal if t

6. Illegal if t

7. Must satisfy burst interrupt condition.

8. Must satisfy bus contention, bus turn around, and/or write recovery requirements.

9. Must mask preceding data which don’t satisfy t

10. Illegal if t

11. Illegal for single bank, but legal for other banks in multi-bank devices.

Document : 1G5-0153 Rev.1 Page 12

is not satisfied.

RCD

is not satisfied.

RAS

is not satisfied.

RRD

DPL

.

VIS

→

Preliminary VG36648041CT CMOS Synchronous Dynamic RAM

2.5 Command Truth Table for CKE

Current state CKE

n - 1

Self refresh (S.R.)

Self refresh recovery

Power down (P.D.)

Both banks idle

CKEnCS RAS CAS WE Address Action Notes

H X X X X X X INVALID, CLK (n - 1)would exit S.R. L H H X X X X S.R. Recovery 2 L H L H H X X S.R. Recovery 2 L H L H L X X ILLEGAL L H L L X X X ILLEGAL L L X X X X X Maintain S.R. H H H X X X X Idle after t

H H L H H X X Idle after t H H L H L X X ILLEGAL

H H L L X X X ILLEGAL H L H X X X X Begin clock suspend next cycle 5 H L L H H X X Begin clock suspend next cycle 5 H L L H L X X ILLEGAL H L L L X X X ILLEGAL L H X X X X X Exit clock suspend next cycle 2 L L X X X X X Maintain clock suspend H X X X X X INVALID, CLK (n - 1) would exit P.D. L H X X X X X

L L X X X X X Maintain power down mode H H H X X X Refer to operations in Operative

H H L H X X Refer to operations in Operative

H H L L H X Refer to operation in Operative

H H L L L H X Auto Refresh H H L L L L Op - Code Refer to operations in Operative

H L H X X X Refer to operations in Operative

H L L H X X Refer to operations in Operative

H L L L H X Refer to operations in Operative

H L L L L H X Self refresh 3 H L L L L L Op - Code Refer to operations in Operative

Note

1

RC RC

EXIT P.D. Idle

Command Table

2

L X X X X X X Power down 3

Any state other than listed above

Note:

1. H : Hight level, L : low level, X : High or low level (Don't care).

2. CKE Low to High transition will re-enable CLK and other inputs asynchronously. A minimum setup time must be satisfied before any command other than EXIT.

3. Power down and Self refresh can be entered only from the both banks idle state.

4. Must be legal command as defined in Operative Command Table.

5. Illegal if t

Document : 1G5-0153 Rev.1 Page 13

H H X X X X X Refer to operations in Operative

Command Table H L X X X X X Begin clock suspend next cycle 4 L H X X X X X Exit clock suspend next cycle L L X X X X X Maintain clock suspend

is not satisfied.

SREX

Preliminary VG36648041CT

VIS

5.Mode Register (Address Input for Mode Set)

CMOS Synchronous Dynamic RAM

13

12

0 Reserved

0

12

13

x

13

12

x

10

11

0 0

11 10

x

11

10

x x 0

9 8 0 0

9

1

9

8

0

8

0 0

7 1

7 6 0

7 6

6

5

LTMODE

5

LTMODE

3

4

3 2

4

WT

3

4

WT

2 1

2

1

BL

1

BL

0

JEDEC Standard Test Set

0

Burst Read and Single Write (for Write Through Cache)

0

Burst Read and Burst Write X = Don’t care

Burst length

Wrap type

Bits2 - 0

000 001

010 011 100

101

110 111

0

1

WT = 0

1 2

4

8 R R R

Full page

Sequential Interleave

WT = 1

1

2

4 8 R R R

R

Latency

mode

Bits6 - 4

000 001

010 011 100 101 110

111

Remark R : Reserved

CAS Iatency

R R

2

3 R R R

R

Document : 1G5-0153 Rev.1 Page 14

Preliminary VG36648041CT

VIS

5.1 Burst Length and Sequence

(Burst of Two)

Starting Address (column address A0, binary)

(Burst of Four)

Starting Address (column address A1 - A0, binary)

CMOS Synchronous Dynamic RAM

0 0, 1 0, 1 1 1, 0 1, 0

00 0, 1, 2, 3 0, 1, 2, 3 01 1, 2, 3, 0 1, 0, 3, 2 10 2, 3, 0, 1 2, 3, 0, 1 11 3, 0, 1, 2 3, 2, 1, 0

Sequential Addressing Sequence (decimal)

Interleave Addressing Sequence (decimal)

(Burst of Eight)

Starting Address (column address A2 - A0, binary)

000 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 001 1, 2, 3, 4, 5, 6, 7, 0 1, 0, 3, 2, 5, 4, 7, 6 010 2, 3, 4, 5, 6, 7, 0, 1 2, 3, 0, 1, 6, 7, 4, 5 011 3, 4, 5, 6, 7, 0, 1 ,2 3, 2, 1, 0, 7, 6, 5, 4 100 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 101 5, 6 ,7, 0, 1, 2, 3, 4 5, 4, 7, 6, 1, 0, 3, 2 110 6, 7 ,0 ,1 ,2 ,3 ,4 ,5 6, 7, 4, 5, 2, 3, 0, 1 111 7, 0, 1, 2, 3, 4, 5, 6 7, 6, 5, 4, 3, 2, 1, 0

Full page burst is an extension of the above tables of Sequential Addressing, with the length being 512 for 8M x 8 devices.

Sequential Addressing Sequence (decimal)

Interleave Addressing Sequence(decimal)

Document : 1G5-0153 Rev.1 Page 15

Preliminary VG36648041CT

VIS

6.Address Bits of Bank-Select and Precharge

6.1 Quad banks controlled by A12 & A13 (for VG36648041/VG36648042)

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13

Row

(Activate command)

CMOS Synchronous Dynamic RAM

A12 A13 Result

0 0 Select Bank A

“Activate “ command

0 1 Select Bank B

“Activate” command

1 0 Select Bank C

“Activate” command

1 1 Select Bank D

“Activate” command

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13

Row

(Precharge command)

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13

Co1.

(CAS strobes)

A10 A12 A13 Result

0 0 0 Precharge Bank A 0 0 1 Precharge Bank B 0 1 0 Precharge Bank C 0 1 1 Precharge Bank D 1 X X Precharge All Banks

X: Don't care

0 Disables Auto - Precharge (End of Burst) 1 Enables Auto - Precharge (End of Burst)

A12 A13 Result

0 0 Enables Read/Write

commands for Bank A

0 1 Enables Read/Write

commands for Bank B

1 0 Enables Read/Write

commands for Bank C

1 1 Enables Read/Write

commands for Bank D

Document : 1G5-0153 Rev.1 Page 16

VIS

7.Precharge

Preliminary VG36648041CT CMOS Synchronous Dynamic RAM

The precharge command can be asserted anytime after t Soon after the precharge command is asserted, the precharge operation is performed and the synchronous DRAM

enters the idle state after t

The earliest timing in a read cycle that a precharge command can be asserted without losing any data in the burst is

as follows.

PrechargeE

CLK

Command

CAS latency = 2

DQ

is satisfied. The parameter tRP is the time required to perform the precharge.

RP(min.)

T0 T1

Read

RAS(min)

T2

Q0

is satisfied.

T3

Q1

T4 T5

PRE

T6

Q3Q2

Burst lengh=4

T7

Hi - Z

Command

CAS latency = 3

DQ

CAS latency = 2 : One clock earlier than the last output data.

3 : Two clocks earlier than the last output data.

In order to write all data to the memory cell correctly, the asynchronous parameter ”t fied. The t minimum number of clocks can be calculated by dividing t

last data word is valid. In the following table, minus means clocks before the reference; plus means time after the reference.

DPL(min.)

In summary, the precharge command can be asserted relative to the reference clock that indicates the

specification defines the earliest time that a precharge command can be asserted. The

CAS latency Read Write

Read

Q0

DPL(min.)

2 -1 + t 3 -2 + t

by the clock cycle time.

DPL(min.) DPL(min.)

PRE

Q1

Q2

” must be satis-

DPL

(t

Q3

RAS

is satisfied)

Hi - Z

Document : 1G5-0153 Rev.1 Page 17

Preliminary VG36648041CT

VIS

8.Auto Precharge

During a read or write command cycle, A10 controls whether auto precharge is selected. If A10 is high in the read or write command (Read with Auto precharge command or Write with Auto precharge command), auto precharge is selected and begins automatically after the burst access.

In the write cycle, t being precharged.

When using auto precharge in the read cycle, knowing when the precharge starts is important because the next activate command to the bank being precharged cannot be executed until the precharge cycle ends. Once auto precharge has started, an activate command to the bank can be asserted after tRP has

been satisfied.

A Read or Write command without auto - precharge can be terminated in the midst of a burst operation. However, a Read or Write command with auto - precharge can not be interrupted by the same bank commands before the entire burst operation is completed. Therefore use of the same bank Read, Write, Precharge or Burst Stop command is prohibited during a read or write cycle with auto - precharge. It should be noted that the device will not respond to the Auto - Precharge command if the device is programmed for full page burst read or write cycles.

The timing when the auto precharge cycle begins depends both on both the CAS Iatency programmed into the mode register and whether the cycle is read or write.

CMOS Synchronous Dynamic RAM

DAL(min.)

must be satisfied before asserting the next activate command to the bank

8.1 Read with Auto Precharge

During a READA cycle, the auto precharge begins one clock earlier (CL = 2) or two clocks earlier

(CL = 3) than the last word output.

READ with AUTO PRECHARGE

T0 T1

CLK

Command

CAS latency = 2

DQ

Command

READA B

QB0

T3

QB1

T2

No New Command to Bank B

T4

Auto precharge starts

T5

QB3QB2

T6

Burst lengh = 4

T7

Hi - Z

T8

CAS latency = 3

DQ

Remark READA means READ with AUTO PRECHARGE

Document : 1G5-0153 Rev.1 Page 18

QB0

QB1

QB2

QB3

Hi - Z

Preliminary VG36648041CT

VIS

8.2 Write with Auto Precharge

During a write cycle, the auto precharge starts at the timing that is equal to the value of t

after the last data word input to the device.

WRITE with AUTO PRECHRGE

CLK

Command

CAS latency = 2

CMOS Synchronous Dynamic RAM

T0 T1

WRITA B

T2

No New Command to Bank B

T3

T4 T5

AUTO PRECHARGE starts

t

DPL

T6

DPL(min.)

Burst lengh = 4

T7

T8

DQ

Command

CAS latency = 3

DQ

Remark WRITA means WRITE with AUTO Precharge

DB0

WRITA B

DB0

DB1

No New Command to Bank B

DB1

DB2

DB3DB2

AUTO PRECHARGE starts

t

DPL

DB3

In summary, the auto precharge cycle begins relative to a reference clock that indicates the last data

word is valid.

In the table below, minus means clocks before the reference; plus means clocks after the reference.

CAS latency Read Write

2 -1 + t 3 -2 + t

DPL(min.) DPL(min.)

Hi - Z_

Hi - Z

Document : 1G5-0153 Rev.1 Page 19

Preliminary VG36648041CT

VIS

8.3 Multibank Operation- Read with Auto Precharge

During a READA cycle interrupted by a Read, Write command of another banks, the auto-pre-

charge scheduled time would not be changed.

Multibank Operation

CLK

Command

CAS latency=2

CMOS Synchronous Dynamic RAM

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14

READA A Read B

Burst lengh=8

Auto precharge bank A starts

DQ

Command

CAS latency=3

DQ

READA A

QA0 QA1

Read B

QA0

QB0

QA1

QB0

Similiar top.21

QB2 QB3 QB4 QB5 QB6 QB7 QB1

Auto precharge bank A starts

QB2 QB3 QB4 QB5 QB6 QB7 QB1

Hi-Z

Document : 1G5-0153 Rev.1 Page 20

Preliminary VG36648041CT

VIS

8.4 Multibank Operation- Write with Auto Precharge

During a WRITEA cycle interrupted by a Read, Write command of another banks, the auto-pre-

charge scheduled time would not be changed.

Multibank Operation

CLK

Command

CAS latency=2

CMOS Synchronous Dynamic RAM

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10

WRITA A

Read B

Burst lengh=8

Auto precharge bank A starts

DQ

Command

CAS latency=3

DQ

Multibank Operation

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11

CLK

Command

CAS latency=2

DQ

DA1

DB0

DA0

WRITA A

DA0

WRITA A Write B

DA0

Read B

DB1

DB2

DB0

DB3

DB1

DB0

DB4

DB2 DB3

DB1

Auto precharge bank A starts

DB6

DB5

DB4

Auto precharge bank A starts

DB2

DB3

DB7

DB5

DB4

Burst lengh=8

Hi-Z

Auto precharge bank A starts

Command

CAS latency=3

DQ

WRITA A Write B

DA0

DA1

DB0

DB1

DB2

DB3

DB4

DB5 DB6 DB7

Document : 1G5-0153 Rev.1 Page 21

Hi-Z

Preliminary VG36648041CT

VIS

9.Read/Write Command Interval

9.1 Read to Read command interval

During a read cycle when a new read command is asserted, it will be effective after the CAS latency,

even if the previous read operation has not completed. READ will be interrupted by another READ.

Each read command can be asserted in every clock without any restriction.

READ to READ Command Interval

CLK

CMOS Synchronous Dynamic RAM

T0 T1

T2

T3

T4 T5

Burst lengh=4, CAS latency=2

T6

T7

T8

1 cycle

Read B

QA0

QB0

QB2QB1

Command

DQ

Read A

9.2 Write to Write Command Interval

During a write cycle, when a new Write command is asserted, the previous burst will terminated and the

new burst will begin with a new write command. WRITE will be interrupted by another WRITE.

Each write command can be asserted in every clock without any restriction.

WRITE to WRITE Command Interval

T0 T1

T2

T3

T4 T5

QB3

Burst lengh=4, CAS latency=2

T6

Hi-Z_

T7

T8

CLK

1 cycle

Write B

QB0

QB2QB1

QB3

Hi-Z_

Command

DQ

Write A

QA0

Document : 1G5-0153 Rev.1 Page 22

Preliminary VG36648041CT

VIS

9.3 Write to Read Command Interval

The write command to read command interval is also a minimum of 1 cycle. Only the write data before

the read command will be written. The data bus must be Hi-Z at least one cycle prior to the first D

WRITE to READ Command Interval

CLK

CMOS Synchronous Dynamic RAM

T0 T1

1 cycle

T2

T3

T4 T5

.

OUT

Burst lengh=4

T6

T7

T8

Command

CAS latency=2

DQ

Command

CAS latency=3

DQ

WRITE A

DA0

Write A

DA0

Read B

9.4 Read to Write Command Interval

During a read cycle, READ can be interrupted by WRITE. DQM must be in High at least 3 clocks prior to the write command. There is a restriction to avoid a data

conflict. The data bus must be Hi-Z using DQM before Write.

Hi-Z

QB0

QB1

QB0

QB1

QB3QB2

QB2

QB3

Document : 1G5-0153 Rev.1 Page 23

Preliminary VG36648041CT

VIS

READ to WRITE Command Interval

CMOS Synchronous Dynamic RAM

CLK

Command

DQM

DQ

CLK

Command

T0 T1

Hi-Z

T0 T1

Read

1 cycle

T2

D0

Write

CAS latency=2

T7

T8

T9

D1

T3

T4 T5

D3D2

T6

T2

T3

T6

Burst length=8, CAS latency=2

T7

Write

DQM

DQ

CLK

Command

DQM

DQ

Q0

T0 T1

Read

The minimum command interval = (4+1) cycles

T2

Q2

Hi-Z is

necessary

T4 T5

Hi-Z is

necessary

example: Burst length=4, CAS latency=3

Write

D0

Q1 D0

T3

D1

T6

T7

D1

D2

T8

D2

Document : 1G5-0153 Rev.1 Page 24

Preliminary VG36648041CT

VIS

10.BURST Termination

There are two methods to terminate a burst operation other than using a read or a write command.

One is the burst stop command and the other is the precharge command.

10.1 BURST Stop Command

During a read burst. when the burst stop command is asserted, the burst read data are terminated and the data bus goes to high-impedance after the CAS latency from the burst stop command.

During a write burst, when the burst stop command is asserted, any data provided at that cycle will not be written. The burst write is effectively terminated and no further data can be written until a new write command is asserted.

Burst Termination

CMOS Synchronous Dynamic RAM

CLK

Command

CAS latency=2

DQ

CAS latency=3

DQ

Remark BST: Burst stop command

T0 T1

Read

T0 T1

T2

Q0

T3

BST

Q1

Q0

T4 T5

Q2

Q1

T4 T5

Burst lengh=X, CAS Intency=2,3

T6

Hi-Z

Q2

Burst lengh=X, CAS latency=2,3

T6

T7

Hi-Z

T7

CLK

Command

CAS latency=2,3

DQ

Write

Q0

Q1

Q2

BST

Hi-Z_

Remark BST: Burst command

Document : 1G5-0153 Rev.1 Page 25

Preliminary VG36648041CT

VIS

10.2 PRECHARGE TERMINATION

10.2.1 PRECHARGE TERMINATION in READ Cycle

precharge command is asserted, the burst read operation is terminated and precharge starts.

mand.

Precharge Termination in READ Cycle

CMOS Synchronous Dynamic RAM

During READ cycle, the burst read operation is terminated by a precharge command. When the

The same bank can be activated again after tRP from the precharge command. When CAS latency is 2,the read data will remain valid until one clock after the precharge com-

When CAS latency is 3, the read data will remain valid until two clocks after the precharge com-

CLK

Command

CAS latency=2

DQ

command

CAS latency=3

DQ

T0 T1

Read

T2

T3

Q0 Q3

T4 T5

PRE ACT

Q1

Q0 Q3

Q2

PRE ACT

Q1

T6

t

RP

t

RP

Q2

T7

Hi-Z

Burst lengh= X

T8

Hi-Z

Document : 1G5-0153 Rev.1 Page 26

Preliminary VG36648041CT

VIS

10.2.2 Precharge Termination in WRITE Cycle

PRECHARGE TERMINATION in WRITE Cycle

CMOS Synchronous Dynamic RAM

During WRITE cycle, the burst write operation is terminated by a precharge command. When the precharge command is asserted, the burst write operation is terminated and precharge starts.

The same bank can be activated again after tRP from the precharge command. The DQM must be high to mask invalid data in.

During WRITE cycle, the write data written prior to the precharge command will be correctly stored. However, invalid data may be written at the same clock as the precharge command. To prevent this from happening, DQM must be high at the same clock as the precharge command. This will mask the invalid data.

CLK

Command

CAS latency = 2

DQM DQ

command

CAS latency = 3

DQM

DQ

T0 T1

Write

D0 D3

Write

D0 D3

D1

T2

D2

T3

T4 T5

PRE ACT

D4

PRE ACT

D4

T6

Hi - Z

t

RP

Hi - Z

t

RP

Burst lengh = X

T7

T8

Document : 1G5-0153 Rev.1 Page 27

VIS

Preliminary VG36648041CT CMOS Synchronous Dynamic RAM

Timing Diagram

Document : 1G5-0153 Rev.1 Page 28

VIS

Mode Register Set

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10

CLK

CKE

CS

Preliminary VG36648041CT CMOS Synchronous Dynamic RAM

t

RSC

RAS

CAS

WE

BS

A10

ADD

DQM

DQ

Hi-Z

t

RP

Address Key

Precharge Command

All Banks

Document : 1G5-0153 Rev.1 Page 29

Mode Register Set

Command

Preliminary VG36648041CT

VIS

AC Parameters for Write Timing (1 of 2)

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CMOS Synchronous Dynamic RAM

Burst Length=4, CAS Latency=2

CLK

CKE

CS

RAS

CAS

WE

BS

t

CH

t

CKS

t

CL

t

CMS

t

CMH

t

CK2

Begin Auto Precharge Bank A

Begin Auto Precharge

(Bank D)

Bank B

t

CKH

A10

t

AS

AH

ADD

DQM

t

RCD

DQ

Activate Command

Bank A

t

RRD

QAa0

Write with Auto Precharge Command Bank A

t

RC

QAa1

QAa2 QAa3 QBa0

Activate Command Bank B

(Bank D)

t

DAL

Write with Auto Precharge Command Bank B

(Bank D)

QBa1

QBa2 QBa3

Activate Command Bank A

t

DS

QAb0 QAb1 QAb2

Write without Auto Precharge Command Bank A

t

DPL

Precharge Command

Bank A

RP

Activate

Command

Bank A

Activate

Command

Bank B

(Bank D)

t

DH

QAb3

Document : 1G5-0153 Rev.1 Page 30

Preliminary VG36648041CT

VIS

AC Parameters for Write Timing (2 of 2)

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23

CMOS Synchronous Dynamic RAM

Burst Length=4, CAS Latency=3,4

CLK

CKE

CS

RAS

CAS

WE

BS

t

CL

t

CH

t

CKS

CMS

t

CMH

t

CK3

Begin Auto Precharge Bank A

Begin Auto Precharge Bank B

(Bank D)

t

CKH

A10

t

AS

AH

ADD

DQM

t

RCD

DQ

Activate Command

Bank A

t

RRD

QAa0

Write with Auto Precharge Command Bank A

QAa1

Activate Command Bank B

(Bank D)

t

RC

QAa2

QAa3 QBa0 QBa1

t

DAL

Write with Auto Precharge Command Bank B

(Bank D)

t

DS

QBa2

QBa3 QAb0QAb1 QAb2

Activate Command Bank A

Write without Auto Precharge Command Bank A

t

QAb3

DPL

Precharge Command

Bank A

t

DH

t

RP

Activate

Command

Bank A

Document : 1G5-0153 Rev.1 Page 31

Preliminary VG36648041CT

VIS

AC Parameters for Read Timing (1 of 2)

CMOS Synchronous Dynamic RAM

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13

Burst Length=2, CAS Latency=2

CLK

CKE

CS

RAS

CAS

WE

BS

A10

tCHt

t

CKS

CL

t

AS

t

AH

t

CK2

t

CMS

t

CMH

Bank B

Begin Auto Precharge

(Bank D)

t

CKH

ADD

t

RRD

t

RAS

t

RC

DQM

DQ

Hi-Z

Activate Command Bank A

t

RCD

Read Command Bank A

t

AC2

t

LZ

t

AC2

t

OH

QAa0

Activate Command Bank B

(Bank D)

t

HZ

t

OH

QAa1

Read with

Auto Precharge

Command

Bank B

(Bank D)

QBa0

Precharge Command Bank A

t

RP

t

HZ

QBa1

Activate Command Bank A

Document : 1G5-0153 Rev.1 Page 32

Preliminary VG36648041CT

VIS

AC Parameters for Read Timing (2 of 2)

CLK

CKE

CS

CMOS Synchronous Dynamic RAM

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15

t

CH

t

CKS

t

CL

t

CK3

t

CMS

t

CMH

Burst Length=2, CAS Latency=3

Begin Auto

Precharge

(Bank D)

Bank B

t

CKH

RAS

CAS

WE

BS

A10

ADD

DQM

t

AH

t

AS

t

RRD

t

RAS

t

RC

t

RP

t

AC3

OH

t

HZ

t

OH

Read with Auto Precharge Command Bank B

(Bank D)

Precharge

Command Bank A

QBa0

DQ

Hi-Z

Activate Command Bank A

t

RCD

Read Command Bank A

t

AC3

t

LZ

Activate Command Bank B

(Bank D)

QAa0 QAa1

Document : 1G5-0153 Rev.1 Page 33

QBa1

t

HZ

Activate

Command

Bank A

Preliminary VG36648041CT

VIS

Power on Sequence and Auto Refresh (CBR)

CLK

CMOS Synchronous Dynamic RAM

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CKE

CS

RAS

CAS

WE

BS

A10

High level is required

Minimum of 2 Refresh Cycles are required

t

RSC

Address Key

ADD

DQM

DQ

Hi-Z

High Level is Necessary

Precharge Command

Inputs

All Banks

must be stable

for 100us

t

RP

1st Auto Refresh

Command

2nd Auto Refresh Command

t

RC

Register

Mode Set Command

Command

Document : 1G5-0153 Rev.1 Page 34

Preliminary VG36648041CT

VIS

Clock Suspension During Burst Read (Using CKE) (1 of 2)

CMOS Synchronous Dynamic RAM

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

Burst Length=4, CAS Latency=2

CLK

CKE

CS

RAS

CAS

WE

BS

t

CK2

A10

ADD

RAa

CAa

DQM

t

HZ

Hi-Z

DQ

Activate

Command

Bank A

Read Command Bank A

QAa0 QAa1 QAa2 QAa3

Clock

Suspended

1 Cycle

Clock

Suspended

2 Cycles

Clock

Suspended

3 Cycles

Document : 1G5-0153 Rev.1 Page 35

Preliminary VG36648041CT

VIS

Clock Suspension During Burst Read (Using CKE) (2 of 2)

CLK

CKE

CS

CMOS Synchronous Dynamic RAM

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

t

CK3

Burst Length=4, CAS Latency=3

RAS

CAS

WE

BS

A10

ADD

DQM

DQ

Hi-Z

RAa

CAa

QAa0

QAa1

QAa2 QAa3

t

HZ

Activate

Command

Bank A

Read

Command

Bank A

Clock

Suspended

1 Cycles

Clock

Suspended

2 Cycles

Clock

Suspended

3 Cycles

Document : 1G5-0153 Rev.1 Page 36

Preliminary VG36648041CT

VIS

Clock Suspension During Burst Write (Using CKE) (1 of 2)

CMOS Synchronous Dynamic RAM

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

Burst Length=4, CAS Latency=2

CLK

CKE

CS

RAS

CAS

WE

BS

t

CK2

A10

ADD

RAa

CAa

DQM

DQ

Hi-Z

Activate

Command

Bank A

DAa0 DAa1 DAa2 DAa3

Suspended

Write

Command

Bank A

Clock 1 Cycle

Clock

Suspended

2 Cycles

Clock

Suspended

3 Cycles

Document : 1G5-0153 Rev.1 Page 37

Preliminary VG36648041CT

VIS

Clock Suspension During Burst Write (Using CKE) (2 of 2)

CMOS Synchronous Dynamic RAM

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

Burst Length=4, CAS Latency=3

CLK

CKE

CS

RAS

CAS

WE

BS

t

CK

A10

ADD

RAa

CAa

DQM

DQ

Hi-Z

Activate

Command

Bank A

DAa0 DAa1 DAa2 DAa3

Suspended

Write

Command

Bank A

Clock 1 Cycle

Clock

Suspended

2 Cycles

Clock

Suspended

3 Cycles

Document : 1G5-0153 Rev.1 Page 38

Preliminary VG36648041CT

VIS

Power Down Mode and Clock Mask

CMOS Synchronous Dynamic RAM

Burst Length=4, CAS Latency=2

CLK

CKE

CS

RAS

CAS

WE

CLK can be Stopped

*

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

t

CK2

t

CKS

t

CKH

VALID

t

CKS

BS

A10

ADD

DQM

DQ

Hi-Z

RAa

Activate

Command

Bank A

Power Down Mode Entry

ACTIVE

STANDBY

CAa

Read Command Bank A

Power Down Mode Exit

QAa0

QAa1

Clock Mask

Start

QAa2

Clock Mask

End

t

HZ

QAa3

Precharge

Command

Power Down

Mode Entry

Precharge Standby

Power

Down

Mode Exit

Command

Document : 1G5-0153 Rev.1 Page 39

VIS

Auto Refresh (CBR)

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CLK

CKE

CS

Preliminary VG36648041CT CMOS Synchronous Dynamic RAM

Burst Length=4, CAS Latency=2

t

CK2

RAS

CAS

WE

BS

A10

ADD

DQM

DQ

Hi-Z

RAa

t

RP

t

RC

t

RC

CAa

Q0 Q1

Q2

Q3

Precharge

Command

All Banks

CBR Refresh Command

CBR Refresh

Command

Activate Command

Read

Command

Document : 1G5-0153 Rev.1 Page 40

Preliminary VG36648041CT

VIS

Self Refresh (Entry and Exit)

CMOS Synchronous Dynamic RAM

CLK

CKE

CS

RAS

CAS

WE

CLK can be Stopped

*

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

t

CKS

t

SRX

t

SRX

t

CKS

BS

A10

ADD

DQM

DQ

Hi-Z

All Banks must be idle

Self refresh

Entry

Self Refresh

Exit

t

RC

Self Refresh

Entry

Self Refresh

Exit

t

RC

Activate

Command

* Clock can be stopped at CKE=Low. If clock is stopped, it must be restarted/stable for 4 clock cycles before CKE=High

Document : 1G5-0153 Rev.1 Page 41

Preliminary VG36648041CT

VIS

Random Column Read (Page Within same Bank)(1 of 2)

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CLK

CKE

CS

CMOS Synchronous Dynamic RAM

t

CK2

Burst Length=4, CAS Latency=2

RAS

CAS

WE

BS

A10

ADD

DQM

DQ

Hi-Z

RAa

CAa

QAa0 QAa1

CAb CAc

QAa2 QAa3 QAb0

QAc0 QAc1 QAc2

QAb1

QAc3

RAa

RAd

CAd

QAd0

QAd1

QAd2

QAd3

Precharge

Command

Bank A

Read

Command

Bank A

Read

Command

Bank A

Read

Command

Bank A

Precharge

Command

Bank A

Activate

Command

Bank A

Read

Command

Bank A

Document : 1G5-0153 Rev.1 Page 42

Preliminary VG36648041CT

VIS

Random Column Read (Page Within same Bank)(2 of 2)

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CLK

CKE

CS

CMOS Synchronous Dynamic RAM

t

CK3

Burst Length=4, CAS Latency=3

RAS

CAS

WE

BS

A10

ADD

DQM

DQ

Hi-Z

RAa

CAa

CAb CAc RAd

QAa0 QAa1 QAa2

QAb0 QAb1 QAc0

QAa3

QAc1

QAc2 QAc3

RAd

CAd

Activate

Command

Bank A

Read

Command

Bank A

Read

Command

Bank A

Read

Command

Bank A

Precharge

Command

Bank A

Activate

Command

Bank A

Read

Command

Bank A

Document : 1G5-0153 Rev.1 Page 43

Preliminary VG36648041CT

VIS

Random Column Write (Page Within same Bank) (1 of 2)

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CLK

CKE

CS

CMOS Synchronous Dynamic RAM

t

CK2

Burst Length=4, CAS Latency=2

RAS

CAS

WE

BS

A10

ADD

DQM

DQ

Hi-Z

Ra

Ca

Da0

Da1 Da2

Cb Cc Rd

Db0 Db1 Dc0

Da3

Dc1

Dc2 Dc3

Rd

Cd

Dd0

Dd1

Dd2 Dd3

Activate

Command

Bank B

(Bank D)

Write

Command

Bank B

(Bank D) (Bank D)

Write

Command

Bank B

Write

Command

Bank B

(Bank D)

Precharge

Command

Bank B

(Bank D)

Activate

Command

Bank B

(Bank D) (Bank D)

Write

Command

Bank B

Document : 1G5-0153 Rev.1 Page 44

Preliminary VG36648041CT

VIS

Random Column Write (Page Within same Bank) (1 of 2)

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CLK

CKE

CS

CMOS Synchronous Dynamic RAM

t

CK

Burst Length=4, CAS Latency=3

RAS

CAS

WE

BS

A10

ADD

DQM

DQ

Hi-Z

Ra

Ca

Da0

Da1 Da2

Da3

Cb

Db0 Db1

Rd

Cc Cd

Dc1

Dc2 Dc3

Dc0

Rd

Dd0

Dd1

Activate

Command

Bank B

(Bank D) (Bank D)

Write

Command

Bank B

Write

Command

Bank B

(Bank D)

Write

Command

Bank B

(Bank D)

Precharge

Command

Bank B

(Bank D)

Activate

Command

Bank B

(Bank D)

Write

Command

Bank B

(Bank D)

Document : 1G5-0153 Rev.1 Page 45

Preliminary VG36648041CT

VIS

Random Row Read (Interleaving Banks)(1 of 2)

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CLK

CKE

High

CS

CMOS Synchronous Dynamic RAM

t

CK2

Burst Length=8, CAS Latency=2

RAS

CAS

WE

BS

A10

ADD

DQM

DQ

Hi-Z

t

RCD

t

AC2

QBa1 QBa2

QBa3

QBa5 QBa6 QBa7

QBa4

t

RP

QAa0

QAa1

QAa2

QAa3 QAa4

QAa5

QAa6 QAa7

QBb1

QBb0QBa0

Activate

Command

Bank B

(Bank D)

Read

Command

Bank B

(Bank D)

Activate

Command

Bank A

Precharge

Command

Bank B

(Bank D)

Read

Command

Bank A

Active

Command

Bank B

(Bank D)

Read

Command

Bank B

(Bank D)

Document : 1G5-0153 Rev.1 Page 46

Preliminary VG36648041CT

VIS

Random Row Read (Interleaving Banks) (2 of 3)

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CMOS Synchronous Dynamic RAM

Burs tLength=8, CAS Latency=3

CLK

CKE

CS

RAS

CAS

WE

BS

High

t

CK3

A10

ADD

DQM

DQ

Hi-Z

Activate

Command

Bank B

(Bank D)

t

RCD

Read

Command

Bank B

(Bank D)

t

AC3

QBa2

QBa1

Activate

Command

Bank A

QBa3

QBa5

QBa4

Read

Command

Bank A

QBa6 QBa7

Precharge

Command

Bank B

(Bank D)

t

RP

QAa0 QAa1

QAa2

Activate

Command

Bank B

(Bank D)

QAa3

QAa4

Command

(Bank D)

QAa5

Read

Bank B

QAa6

QAa7

Precharge

Command

Bank A

Document : 1G5-0153 Rev.1 Page 47

QBb0QBa0

Preliminary VG36648041CT

VIS

Random Row Write (Interleaving Banks) (1 of 2)

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CMOS Synchronous Dynamic RAM

Burst Length=8, CAS Latency=2

CLK

CKE

CS

RAS

CAS

WE

BS

High

t

CK2

A10

ADD

DQM

DQ

Hi-Z

Activate

Command

Bank A

t

RCD

Write

Command

Bank A

QAa1 QAa2

QAa3

QAa4

QAa5

QAa6 QAa7

Activate

Command

Bank B

(Bank D)

t

DPL

QBa0 QBa1

Precharge

Command

Bank A

Write

Command

Bank B

(Bank D)

t

RP

QBa2

Command

Bank A

QBa3 QBa4

Active

QBa5

QBa6 QBa7

Command

QAb0 QAb1

Write

Bank A

t

DPL

QAb2QAa0

Precharge

Command

Bank B

(Bank D)

QAb3

Document : 1G5-0153 Rev.1 Page 48

QAb4

Preliminary VG36648041CT

VIS

Random Row Write (Interleaving Banks) (2 of 2)

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CMOS Synchronous Dynamic RAM

Burst Length=8, CAS Latency=3

CLK

CKE

CS

RAS

CAS

WE

BS

High

t

CK

A10

ADD

DQM

DQ

Hi-Z

Activate

Command

Bank A

t

RCD

QAa0 QAa1

Write

Command

Bank A

QAa2

QAa3

RBa

QAa4

QAa5 QAa6

Activate

Command

Bank B

(Bank D)

QAa7 QBa0

Write

Command

Bank B

(Bank D)

t

DPL

QBa1

QBa2 QBa3

Precharge

Command

Bank A

t

RP

QBa4

QBa5 QBa6

Activate

Command

Bank A

QBb7 QAb0

Write

Command

Bank A

t

DPL

QAb1

Command (Bank D)

QAb2

Precharge Bank B

Document : 1G5-0153 Rev.1 Page 49

QAb3

Preliminary VG36648041CT

VIS

Read and Write Cycle (1 of 2)

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CLK

CKE

CS

CMOS Synchronous Dynamic RAM

t

CK2

Burst Length=4, CAS Latency=2

RAS

CAS

WE

BS

A10

ADD

DQM

RAa

CAb

CAc CAa

DQ

Hi-Z

Activate

Command

Bank A

Write

Command

Bank A

QAa0

QAa1

QAa2

QAa3

DAb0

Write

Command

Bank A

DAb1

The Write Data

is Masked with a

Zero Clock

latency

DAb3 QAc0

Read

Command

Bank A

QAc1

The Read Data is Masked with

Two Clocks

Latency

Document : 1G5-0153 Rev.1 Page 50

QAc3

Preliminary VG36648041CT

VIS

Read and Write Cycle (2 of 2)

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CMOS Synchronous Dynamic RAM

Burst Length=4, CAS Latency=3

CLK

CKE

CS

RAS

CAS

WE

BS

t

CK3

A10

ADD

RAa

CAa

CAb

CAc

DQM

DQ

Hi-Z

Activate

Command

Bank A

Read

Command

Bank A

QAa0 QAa1

QAa2

QAa3

DAb0 DAb1

Write

Command

Bank A

DAb3

The Write Data

is Masked with a

Zero Clock

Latency

Read

Command

Bank A

QAc0

QAc1

The Read Data

is Masked with

a Two Clock

Latency

Document : 1G5-0153 Rev.1 Page 51

QAc3

Preliminary VG36648041CT

VIS

Interleaved Column Read Cycle (1 of 2)

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CMOS Synchronous Dynamic RAM

Burst Length=4, CAS Latency=2

CLK

CKE

CS

RAS

CAS

WE

BS

t

CK2

A10

ADD

DQM

DQ

Ra Ra

Ra

t

Hi-Z

Activate

Command

Bank A

RCD

Read

Command

Bank A

Cb

Ra

t

AC2

QAa0 QAa1

Activate

Command

Bank B

(Bank D) (Bank D)

Ca Cb Cc Cb Cd

QAa2

Read

Bank B

QAa3

Command

QBa0

Read

Bank B

(Bank D)

QBa1

QBb0 QAb0

Read

Command

Bank B

(Bank D)

QBc0

QBb1 QBd0

Read

Command

Bank A

QBc1

Command (Bank D)

Read

Bank B

QAb1

Precharge

Command

Bank A

QBd1

QBd2

QBd3

Precharge Command

Bank B

(Bank D)

Document : 1G5-0153 Rev.1 Page 52

Preliminary VG36648041CT

VIS

Interleaved Column Read Cycle (2 of 2)

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CMOS Synchronous Dynamic RAM

Burst Length=4, CAS Latency=3

CLK

CKE

CS

RAS

CAS

WE

BS

t

CK3

A10

ADD

Ra Ra

Ra

Ca

Ca Cb Cc

Cb

DQM

t

DQ

Hi-Z

Activate

Command

Bank A

RCD

t

RRD

Read

Command

Bank A

Activate

Command

(Bank D)

Bank B

t

AC3

QAa1

QAa0

Read

Command

Bank B

(Bank D) (Bank D)

QAa3

QAa2

Command

Read

Bank B

QBa0

QBb0 QAb0

QBa1 QAb3

Read

Command

Bank B

(Bank D)

QBc0

QBb1 QAb2

Read

Command

Bank A

QBc1

Precharge

Command

Bank B

(Bank D)

QAb1

Precharge Command

Bank A

Document : 1G5-0153 Rev.1 Page 53

Preliminary VG36648041CT

VIS

Interleaved Column Write Cycle (1 of 2)

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CLK

CKE

CS

CMOS Synchronous Dynamic RAM

t

CK2

Burst Length=4, CAS Latency=2

RAS

CAS

WE

BS

A10

ADD

DQM

Ra Ra

Ra

t

RCD

t

RRD

Ca

Ra

Ca Cb Cc

Cb

t

RP

DPL

DQ

Hi-Z

Activate

Command

Bank A

DAa0 DAa1

Write

Command

Bank A

DAa3

DAa2

Activate

Command

Bank B

(Bank D)

DBa0 DBa1 DBd1

Write

Command

Bank B

(Bank D)

DBb0 DAb0

Write

Command

Bank B

(Bank D)

DBb1

DBc0 DBc1

Write

Command

Bank B

(Bank D)

Write

Command

Bank A

DAb1

DBd0

Precharge

Command

Bank A

Write

Command

Bank B

(Bank D)

DBd2 DBd3

Precharge Command

Bank B

(Bank D)

Document : 1G5-0153 Rev.1 Page 54

Preliminary VG36648041CT

VIS

Interleaved Column Write Cycle (2 of 2)

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CLK

CKE

CS

CMOS Synchronous Dynamic RAM

t

CK

Burst Length=4, CAS Latency=3

RAS

CAS

WE

BS

A10

ADD

DQM

Ra Ra

Ra

t

Ca

RCD

RRD

Ca Cb Cc

Cb

t

DPL

Cd

t

DPL

t

RP

DQ

Hi-Z

Activate

Command

Bank A

QAa0 QAa1

Write

Command

Bank A

Activate

Command

Bank B

(Bank D)

QAa2

QAa3

Command

(Bank D)

QBa0 QBa1

Write

Bank B

QBb0 QAb0

Write

Command

Bank B

(Bank D)

QBc0 QBc1

QBb1 QBd0

Write

Command

Bank B

(Bank D)

Write

Command

Bank A

QAb1

QBd1

Write

Command

Bank B

(Bank D)

Precharge Command

Bank A

QBd2 QBd3

Precharge Command

Bank B

(Bank D)

Document : 1G5-0153 Rev.1 Page 55

Preliminary VG36648041CT

VIS

Auto Precharge after Read Burst (1 of 2)

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CMOS Synchronous Dynamic RAM

Burst Length=4, CAS Latency=2

CLK

CKE

CS

RAS

CAS

WE

BS

High

t

CK2

Start Auto Precharge

(Bank D)

Bank B

Start Auto Precharge Bank A

Start Auto Precharge

(Bank D)

Bank B

A10

ADD

Ra Ra

Ra

Ca

Ra

Ca Cb Rb

Rb Rc

Cb

Rc

Cc

DQM

DQ

Hi-Z

Activate

Command

Bank A

Read

Command

Bank A

QAa0

Activate

Command

Bank B

(Bank D)

QAa1

QAa2

Read with

Auto Precharge

Command

Bank B

(Bank D)

QAa3

QBa0

QBa2 QAb2

QBa1 QBb1

Read with

Auto Precharge

Command

Bank A

QAb0

QBa3 QBb0

Activate

Command

Bank B

(Bank D)

QAb1

Auto Precharge

Read with

Command

Bank B

(Bank D)

QAb3

Activate

Command

Bank A

Auto Precharge

QBb2 QBb3

Read with Command

Bank A

QAc1

QAc0 QAc2

Document : 1G5-0153 Rev.1 Page 56

Preliminary VG36648041CT

VIS

Auto Precharge after Write Burst (2 of 2)

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CLK

CMOS Synchronous Dynamic RAM

t

CK3

Burst Length=4, CAS Latency=3

CKE

CS

RAS

CAS

WE

BS

A10

High

Ra

Rb

Start Auto Precharge

Bank A

Start Auto Precharge

(Bank D) (Bank D)

Bank B

Start Auto Precharge Bank B

ADD

Ra

Ca

Ra

Ca

Cb

Rb

RBb

Cb

DQM

DQ

Hi-Z

Activate

Command

Bank A

Activate

Command

Bank B

(Bank D)

Read

Command

Bank A

QAa0 QAa1

Read with

Auto Precharge

Command

Bank B

QAa2

(Bank D)

QAa3

QBa0

QBa1

QBa2 QAb2

Read with

Auto Precharge

Command

Bank A

QBa3

Command

(Bank D)

QAb0

Activate

Bank B

QAb1

Auto precharge Bank B

QAb3

Write with

Command

(Bank D)

QBb0

Document : 1G5-0153 Rev.1 Page 57

QBb1 QBb2

Preliminary VG36648041CT

VIS

Auto Precharge after Write Burst (1 of 2)

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CMOS Synchronous Dynamic RAM

Burst Length=4, CAS Latency=2

CLK

CKE

CS

RAS

CAS

WE

BS

High

t

CK2

Start Auto Precharge

(Bank D)

Bank B

Start Auto Precharge

Bank A

Start Auto Precharge

(Bank D)

Bank B

A10

ADD

Ra

Ca

Cb

Rb

Rc

Cb Ca

Rc Cc

DQM

DQ

Hi-Z

Activate

Command

Bank A

QAa0 QAa1

Write

Command

Bank A

QAa3

QAa2

Activate

Command

Bank B

(Bank D)

QBa0 QBa1 QBb1

Write with

Auto Precharge

Command

Bank B

(Bank D)

QBa2 QAb2

QAb0 QAb1

QBa3

Write with

Auto Precharge

Command

Bank A

Activate

Command

Bank B

(Bank D)

QBb0

QAb3

Write with

Auto Precharge

Command

Bank B

(Bank D)

QBb2 QBb3

Activate

Command

Bank A

QAc0 QAc1 QAc2 QAc3

Write with

Auto Precharge

Bank A

Start Auto

Precharge

Document : 1G5-0153 Rev.1 Page 58

Bank A

Preliminary VG36648041CT

VIS

Auto Precharge after Write Burst (2 of 2)

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CLK

CMOS Synchronous Dynamic RAM

t

CK

Burst Length=4, CAS Latency=3

CKE

CS

RAS

CAS

WE

BS

A10

High

Ra

Start Auto Precharge

Bank B

(Bank D)

Rb

Start Auto Precharge

Bank A

Start Auto Precharge

(Bank D)

Bank B

ADD

Ra

Ca

Ra

Ca

Cb

Rb

RBb

Cb

DQM

DQ

Hi-Z

Activate

Command

Bank A

QAa0 QAa1

Activate

Command

Bank B

(Bank D)

Read

Command

Bank A

QAa2

QBa0

QAa3

Read with

Auto Precharge

Command

Bank B

QAb0

QBa1

(Bank D)

QBa3

QBa2 QAb2

Read with

Auto Precharge

Command

Bank A

QAb1

QAb3

Activate

Command

Bank B

(Bank D)

QBb0

QBb1 QBb2

Write with

Auto precharge

Command

(Bank D)

Bank B

QBb3

Document : 1G5-0153 Rev.1 Page 59

Preliminary VG36648041CT

VIS

Full Page Read Cycle (1 of 2)

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CLK

High

CKE

CS

CMOS Synchronous Dynamic RAM

t

CK2

Burst Length=Full Page, CAS Latency=2

RAS

CAS

WE

BS

A10

ADD

DQM

DQ

Hi-Z

Ra

QAa-1

Ca

QAa+1 QBa QBa+1

QAa

QBa+2

QBa+3

QBa+4 QBa+51

QBa+6

Ca Rb

Ra

QAa

QAa+1

QAa+2

QAa-2

Rb

t

RP

Full page burst operation does not

Activate

Command

Bank A

Read

Command

Bank A

Activate

Command

Bank B

(Bank D)

The burst counter wraps from the highest order page address back to zero during this time interval

Read

Command

Bank B

(Bank D)

terminate when the burst length is satisfied; the burst counter increments and continues bursting beginning with the starting address

Precharge Command Bank B

(Bank D) Burst Stop Command

Activate

Command

Bank B

(Bank D)

Document : 1G5-0153 Rev.1 Page 60

Preliminary VG36648041CT

VIS

Full Page Read Cycle (2 of 2)

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CMOS Synchronous Dynamic RAM

Burst Length=Full Page, CAS Latency=3

CLK

CKE

CS

RAS

CAS

WE

BS

High

t

CK3

A10

ADD

Ra

Ca Rb

Ra

Ca

Rb

DQM

DQ

Hi-Z

Activate

Command

Bank A

Read

Command

Bank A

Activate

Command

Bank B

(Bank D)

QAa+2

QAa+1

QAa

The burst counter wraps from the highest order page address back to zero during this time interval

QAa-2

QAa-1

Read

Command

Bank B

(Bank D)

QAa+1

QAa

Full page burst operation does not teminate when the burst length is satisfied; the burst counter increments and continues bursting beginning with the starting address

QBa0

QBa+1

QBa+2

QBa+3

Precharge Command Bank B

(Bank D) Burst Stop Command

QBa+4

QBa+5

Activate

Command

Bank B

(Bank D)

Document : 1G5-0153 Rev.1 Page 61

Preliminary VG36648041CT

VIS

Full Page Write Cycle (1 of 2)

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CLK

CKE

High

CS

CMOS Synchronous Dynamic RAM

t

CK2

Burst Length=Full Page, CAS Latency=2

RAS

CAS

WE

BS

A10

ADD

DQM

DQ

Hi-Z

Ra

Ca Rb

QAa

QAa+1

Ra

QAa+2 QAa+3

QAa-1

QAa

QAa+1

Ca

QBa

QBa+1

QBa+2

QBa+3

QBa+4

QBa+5

QBa+6

t

BDL

Rb

Activate

Command

Bank A

Write

Command

Bank A

Activate

Command

Bank B

(Bank D)

The burst counter wraps from the highest order page address back to zero during this time interval

Write

Command

Bank B

(Bank D)

Full page burst operation does not terminate when the burst length is satisfied; the burst counter increments and continues bursting beginning with the starting address

Data is ignored

Precharge Command Bank B

(Bank D) (Bank D) Burst Stop Command

Activate

Command

Bank B

Document : 1G5-0153 Rev.1 Page 62

Preliminary VG36648041CT

VIS

Full Page Write Cycle (2 of 2)

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CLK

CKE

High

CS

CMOS Synchronous Dynamic RAM

t

CK

Burst Length=Full Page, CAS Latency=3

RAS

CAS

WE

BS

A10

ADD

DQM

DQ

Hi-Z

Ra

Ca

DAa

DAa+1

Ra

DAa+2 DAa+3

DAa-1

DAa

DAa+1

Ca

DBa

DBa+1 DBa+2

DBa+3

DBa+4

DBa+5

t

BDL

Rb

Data is ignored.

Activate

Command

Bank A

Write

Command

Bank A

Activate

Command

Bank B

(Bank D)

The burst counter wraps from the highest order page address back to zero during this time interval

Write

Command

Bank B

(Bank D)

Full page burst operation does not terminate when the burst length is satisfied; the burst counter increments and continues bursting beginning with the starting address

Precharge Command Bank B

(Bank D) Burst Stop Command

Activate

Command

Bank B

(Bank D)

Document : 1G5-0153 Rev.1 Page 63

VIS

Byte Write Operation

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

Preliminary VG36648041CT CMOS Synchronous Dynamic RAM

Burst Length=4, CAS Latency=2

CLK

CKE

CS

RAS

CAS

WE

BS

A10

High

RAa

t

CK2

ADD

RAa

CAa

CAb

CAz

DQM

DQ0~DQ7

Hi-Z

Activate Command

Bank A

Read

Command

Bank A

Upper Byte is masked

DQs are

masked

Write

Command

Bank A

Write Upper is masked

Read

Command

Bank A

DQs are

masked

DQs are

masked

Document : 1G5-0153 Rev.1 Page 64

Preliminary VG36648041CT

VIS

Burst Read and Single Write Operation

CMOS Synchronous Dynamic RAM

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

Burst Length=4, CAS Latency=2

CLK

CKE

CS

RAS

CAS

WE

BS

A10

High

RAa

t

CK2

ADD

RAa

CAa

CAb

CAc CAe

CAd

DQM

DQ0~DQ7

Hi-Z

DQs are

Activate Command

Bank A

Read

Command

Bank A

Single Write Command Bank A

Read

Command

Bank A

masked

Single Write Command Bank A

Document : 1G5-0153 Rev.1 Page 65

DQs are

masked

Preliminary VG36648041CT

VIS

Full Page Random Column Read

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CLK

CKE

CS

CMOS Synchronous Dynamic RAM

t

CK2

Burst Length=Full Page, CAS Latency=2

RAS

CAS

WE

BS

A10

ADD

DQM

DQ

Hi-Z

Ra

Ra Ca Ca

Cb Cb

QBa0

QAa0

QAb0 QAb1

QBb0

QBb1 QAc0

Cc Cc Rb

t

RP

QAc2

QAc1

QBc0

QBc1 QBc2

Rb

Activate

Command

Bank A

Activate

Command

Bank B

(Bank D) (Bank D)

Command

Read

Command

Bank A

Read

Bank B

Read

Command

Bank A

Read

Command

Bank B

(Bank D)

Read

Command

Bank A

Read

Command

Bank B

(Bank D)

Precharge

Command Bank B

(Precharge Termination)

(Bank D)

Activate

Command

Bank B

(Bank D)

Document : 1G5-0153 Rev.1 Page 66

Preliminary VG36648041CT

VIS

Full Page Random Column Write

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CMOS Synchronous Dynamic RAM

Burst Length=Full Page, CAS Latency=2

CLK

CKE

CS

RAS

CAS

WE

BS

t

CK2

A10

ADD

Ra

Ra Ca Ca

Cb Cb

Rb

Cc Cc Rb

t

RP

DQM

DQ

Hi-Z

Activate

Command

Bank A

Activate

Command

Bank B

(Bank D)

Command

QAa0

Write

Bank A

QBa0

Write

Command

Bank B

(Bank D)

Command

QAb0

Write

Bank A

QAb1

Command

Bank B

(Bank D)

QBb0 QBb1

Write

QAc0

Write

Command

Bank A

QAc1

QAc2

Write

Command

Bank B

(Bank D)

QBc0

QBc1

Command Bank B

QBc2

Precharge

Write Data is masked

(Bank D)

Command (Bank D)

(Precharge Termination)

Activate

Bank B

Document : 1G5-0153 Rev.1 Page 67

Preliminary VG36648041CT

VIS

Precharge Termination of a Burst (1 of 2)

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CMOS Synchronous Dynamic RAM

Burst Length=4,8 or Full Page, CAS Latency=2

CLK

CKE

CS

RAS

CAS

WE

BS

High

t

CK2

A10

ADD

RAa

RAa CAcCAa

t

DPLtRP

RAb

RAc

RAc CAb

t

RP

t

RP

DQM

DQ

Hi-Z

Activate

Command

Bank A

QAa0

QAa1

Write

Command

Bank A

Precharge Termination

of a Write Burst. Write

data is masked.

QAa2

Da3

Precharge Command Bank A

Activate

Command

Bank A

Read

Command

Bank A

QAb1

QAb0

Precharge

Command

Bank A

Precharge Termination

of a Read Burst.

QAb2

Activate

Command

Bank A

Read

Command

Bank A

QAc0

Precharge

Command

QAc1

Bank A

QAc2

Document : 1G5-0153 Rev.1 Page 68

Preliminary VG36648041CT

VIS

Precharge Termination of a Burst (2 of 3)

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CLK

CKE

High

CS

CMOS Synchronous Dynamic RAM

t

CK3

Burst Length=4,8 or Full Page, CAS Latency=3

RAS

CAS

WE

BS

A10

ADD

DQM

RAa

RAa RAcCAa

t

RCD

t

DPL

RAb

t

RP

CAb

t

RAS

RAc

t

RP

DQ

Hi-Z

Activate

Command

Bank A

Write

Command

Bank A

Write Data is masked

DAa1DAa0

Precharge Command Bank A

Precharge Termination

Command

of a Write Burst.

Activate

Bank A

Read

Command

Bank A

QAb0 QAb1

Activate

Command

Bank A

QAb2 QAb3

Activate Command

Bank A

Precharge Termination of a Read Burst.

Document : 1G5-0153 Rev.1 Page 69

Preliminary VG36648041CT

VIS

Ordering information

Part Number Cycle time Package

VG36648041BT-7 7ns 400mil

CMOS Synchronous Dynamic RAM

VG36648041BT-8 8ns

VG36648041BT-10 10ns

VG36648041BT-8

• VG

• 36

• 64

• 80

• 4

• 1

• B

• T

• 8

• VIS Memory Product

• Technology/Design Rule

• 64Mb

• Device Configuration, 80: x8

• Device Infernal Banks

• Interface Type, 1: LVTTL

• Mask/Design Version

• Package Type, T: TSOP

• Cycle time, 10: 10ns, 8: 8ns, 7: 7ns

Packaging Information

• 400mil, 54-Pin Plastic TSOP

54-Pin

Plastic TSOP

A A1 A2 b b1 c c1 D

e E E1 L R R1

MILLIMETERS

MIN. NOM.

0.05

0.95

1.00

0.30

0.12

22.09

22.22

0.71 REF.

0.80 BASIC

11.56

11.76

10.03

10.16

0.40

0.50

0.12

MAX.

------

1.20

---

0.15

1.05

0.45

---

0.40

---

0.21

---0.12

0.16

---

22.35

11.96

10.29

0.60

---

0.25

DIM

ZD

NOTE:

1. CONTROLLING DIMENSION : MILLIMETERS

2. DIMENSION D DOES NOT INCLUDE MOLD PROTRUSION. MOLD PROTRUSION SHALL NOT EXCEED 0.15mm(0.006") PER SIDE. DIMENSION E1 DOES NOT INCLUDE INTERLEAD PROTRUSION. INTERLEAD PROTRUSION SHALL NOT EXCEED 0.25mm(0.01") PER SIDE.

3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSIONS/INTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD TO

BE WIDER THAN THE MAX b DIMENSION BY MORE THAN 0.13mm.

DAMBAR INTRUSION SHALL NOT CAUSE THE LEAD TO BE NARROWER

THAN THE MIN b DIMENSION BY MORE THAN 0.07mm.

MIN.

0.002

0.037

0.012

0.005

0.870

0.0315 BASIC

0.455

0.395

0.016

0.005

INCHES

NOM.

------

---

0.039

---

0.875

0.028 REF.

0.463

0.400

0.020

---

--- ------ ---0.12 0.005

MAX.

0.047

0.006

0.041

0.018

0.016

0.008

0.006

0.880

0.471

0.405

0.024

0.010

RAD R1

B

L

SECTION B-B

c

c1

RAD R

0¢X~8

c

¢X

0.100(0.004")

28

27

e

A2

A1

E1

A

SEATING PLANE

DETAIL A

b

b1

BASE METAL

WITH PLATING

DETAIL A

E

54

1

ZD

b

D

Document : 1G5-0153 Rev.1 Page 70