Datasheet VG3617161ET-8, VG3617161ET-7, VG3617161ET-6 Datasheet (VIS)

VG3617161ET

1,048,576 x 16 - Bit

VIS

Description

The VG3617161ET is CMOS Synchronous Dynamic RAM organized as 524,288-word X 16-bit X 2-bank. It is fabricated with an advanced submicron CMOS technology and designed to operate from a single 3.3V power supply. This SDRAM is delicately designed with performance concern for current high-speed application. Programmable CAS Latency and Burst Length make it possible to be used in widely various domains. It is packaged by using JEDEC standard pinouts and standard plastic 50-pin TSOP II.

Features

• Single 3.3V +/- 0.3V power supply

• Clock frequency:166MHz, 143MHz, 125MHz

• Fully synchronous with all signals referenced to a positive clock edge

• Programmable CAS Iatency (2,3)

• Programmable burst length (1,2,4,8,& Full page)

• Programmable wrap sequence (Sequential/Interleave)

• Automatic precharge and controlled precharge

• Auto refresh and self refresh modes

• Dual internal banks controlled by A11(Bank select)

• Simultaneous and independent two bank operation

• I/O level : LVTTL interface

• Random column access in every cycle

• X16 organization

• Byte control by LDQM and UDQM

• 4096 refresh cycles/64ms

• Burst termination by burst stop and precharge command

CMOS Synchronous Dynamic RAM

Document:1G5-0189 Rev.1 Page 1

VIS

Pin Configuration

VG3617161ET

1,048,576 x 16 - Bit

CMOS Synchronous Dynamic RAM

50-Pin Plastic TSOP(II)(400 mil)

V

V LDQM

CAS

(BS)A

V

DD

DQ0

DQ1

SSQ

DQ2

DQ3

DDQ

DQ4 DQ5

SSQ

DQ6 DQ7

DDQ

WE

RAS

CS

A

V

DD

1 2

3 4

5 6 7 8

9 10 11 12 13 14 15 16 17 18

11

10

A

0

A

1

A

2

A

3

19 20 21 22

23 24 25

VG3617161ET

50 49

48 47

46 45 44 43 42

41 40 39 38 37

36 35 34 33 32 31 30 29 28

27 26

V

SS

DQ15 DQ14

V

SSQ DQ13 DQ12

V

DDQ DQ11

DQ10

V

SSQ DQ9 DQ8

V

DDQ

NC UDQM

CLK CKE

NC A9 A8

A7 A6

A5 A4

V

SS

Pin Description

(VG3617161ET)

Pin Name Function Pin Name Function

A0-A11 Address inputs

- Row address A0-A10

LDQM, UDQM

Lower DQ mask enable and Upper DQ mask enable

- Column address A0-A7

A11: Bank select DQ0~DQ15 Data-in/data-out CLK Clock input RAS Row address strobe CKE Clock enable CAS Column address strobe CS Chip select WE Write enable V

V

SS

V

DD

Ground V

Power

DDQ

SSQ

Supply voltage for DQ Ground for DQ

Document:1G5-0189 Rev.1 Page 2

VIS

Block Diagram

VG3617161ET

1,048,576 x 16 - Bit

CMOS Synchronous Dynamic RAM

CLK CKE

Address

CS RAS CAS

WE

Clock Generator

Row Address Buffer

Mode

Register

Control Logic

Command Decoder

& Refresh Counter

Column Address Buffer

& Burst Counter

Row Decoder

Data Control Circuit DQ

Bank B

Bank A

Sense Amplifier

Column Decoder & Latch Circuit

DQM

Buffer

Latch Circuit

Input & Output

Document:1G5-0189 Rev.1 Page 3

VIS

0VV

≤≤

µ

0VV

≤≤

µ

VG3617161ET

1,048,576 x 16 - Bit

CMOS Synchronous Dynamic RAM

Absolute Maximum Ratings

(1)

Parameter Symbol Value Unit

Voltage on any pin relative to Vss VIN,V Supply voltage relative to Vss VDD,V Short circuit output current I Power dissipation P Operating temperature T Storage temperature T

Recommended DC Operating Conditions (TA=0~70°C)

Parameter Symbol Min Typ Max Unit Note

Supply Voltage V Input High Voltage, all inputs V Input Low Voltage, all inputs V

DD

IH

IL

OUT

DDQ

OUT

D

OPT

STG

-1.0 to +4.6 V

-1.0 to +4.6 V 50 mA

1.0 W

0 to + 70 °C

-55 to + 125 °C

3.0 3.3 3.6 V

2.0 – VDD+0.3 V I

-0.3 – 0.8 V II

Note I.Overshoot limit : V II .Undershoot limit : VIL=V

DC Electrical Characteristics

Parameter Description Min. Max. Unit Note

I

IL

I

OL

V

OH

V

OL

(All other pins not under test = 0V)

IH(MAX.)=VDDQ

SSQ

INVDD

Output disable, ()

LVTTL Output ”H” Level Voltage(l

LVTTL Output ”L” Level Voltage(l

+2.0V with a pulse width < 3ns

-2.0V with a pulse width< 3ns and -1.5V with a pulse width< 5ns

Input Leakage Current

Output Leakage Current

OUTVDDQ

= -2mA) 2.4 - V

OUT

= 2mA) - 0.4 V

OUT

-5 5 A

Capacitance

(TA=25°C,f=1MHZ)

Parameter Symbol Typ Max Unit

Input capacitance(CLK) C

11

2.5 4 pF

Input capacitance(all input pins except data

C

12

2.5 5 pF

pins) Data input/output capacitance C

Document:1G5-0189 Rev.1 Page 4

I/O

4.0 6.5 pF

VG3617161ET

±

tRCt

()

≥

CKEV

IH

≥

IH

CKEV

≥

∞

≤

CKEV

≤

CKEV

≤

∞

≤

CKEV

IH

≥

CKEV

IH

≥

∞

≤

CKEV

IL

≤

CKEV

IL

≤

∞

≤

tRCtRC≥

CKE0.2V

≤

VIS

IDD Specifications (VDD = 3.3V 0.3V, TA = 0 ~ 70°C)

Description/test condition Symbol

Operating Current

RCmin

Address changed once during t Burst length = 1 (One bank active)

Precharge Standby Current in non power-down mode

Input signals are changed once during 2 clocks

Precharge Standby Current in non power-down mode

Input signals are stable

Precharge Standby Current in power-down mode

, outputs open

,

CSV

(min)

, t

(min)

(max)

CK

, t

CK

IH

IL

≥

(min), tCK =tCK

CLKV

= ,

= tCK(min)

CK(min)

IL

.

(min)

(max)

I

DD1

I

DD2N

I

DD2NS

I

DD2P

1,048,576 x 16 - Bit

CMOS Synchronous Dynamic RAM

-6 -7 -8 Unit Note

Min Max Min Max Min Max

115 105 95

40 40 40 3

35 35 35

mA

2 2 2

3,4

Precharge Standby Current in power-down mode

, t

= ,

IL

(max)

CK

CLKV

IL

(max)

I

Active Standby Current in non power-down mode

(min)

, CS V

IH(min)

, t

= t

CK

CK(min)

Input signals are changed once during 2 clocks

Active Standby Current in non power-down mode

, t

= ,

(min)

CK

CLKV

IL

(max)

I

Input signals are stable

Active Standby Current in power-down mode

, t

(max)

CK = tCK(min)

Active Standby Current in power-down mode

(max)

, t

CK =

,

CLKV

IL

(max)

I

Operating Current

(Page burst, and all banks activated) t

CCD

= t

CCD(min)

, outputs open, gapless data

Refresh Current

(t

REF

= 64ms)

(min)

Self Refresh Current I

DD2PS

I

DD3N

DD3NS

I

DD3P

DD3PS

I

DD4

I

DD5

DD6

2 2 2

50 50 50 3

40 40 40

35 35 35

150 140 130 4,5

100 90 80 3

1 1 1

Document:1G5-0189 Rev.1 Page 5

VIS

0.3V

±

VG3617161ET

1,048,576 x 16 - Bit

CMOS Synchronous Dynamic RAM

A.C Characteristics:

(6)(7)(8)(10)

(VDD=3.3V , VSS=0V, Ta=0 to 70°C)

Symbol A.C. Parameter -6 -7 -8

Unit

Note

ns

9 9

CLK CLK

ns

CLK

CLK CLK

ns

CLK

ms CLK CLK CLK

t

CH

t

CL

t

T

t

CK3

t

CK2

t

IS

t

IH

t

DS

t

DH

t

LZ

t

HZ3

t

HZ2

t

AC3

t

AC2

t

OH

t

RCD

t

RRD

t

CCD

t

DPL

t

RAS

t

RP

t

DAL3

t

DAL2

t

RC

t

RSC

t

REF

t

SRX

t

BDL

t

PDE

Min Max Min Max Min Max

Clock high time 2.5 2.5 3 Clock low time 2.5 2.5 3 Transition time (Rise and Fall) 0.5 10 0.5 10 0.5 10 Clock cycle time CL* = 3 6 7 8

CL* = 2 8 10 12

Address/Control Input setup time 1.5 1.75 2 Address/Control Input hold time 1 1 1 Data Input setup time 1.5 1.75 2 Data Input hold time 1 1 1 Data output low impedance 1 1 1 Data output high imped-

ance

Access time from CLK (positive edge)

Data output hold time 2.3 2.5 2.5 RAS to CAS delay 18 20 20 Row activate to row activate delay 12 14 16 CAS to CAS Delay time 1 1 1 Last data in to precharge 2 2 2 Row activate to precharge time 36 100,000 42 100,000 48 100,000 Precharge to refresh/row activate

command Data-in to ACT (REF) Command (CL = 3) 5 5 5

Data-in to ACT (REF) Command (CL = 2) 5 5 5 Row cycle time 54 63 72 Mode Register Set Cycle time 2 2 2 Refresh time 64 64 64 Minimum CKE ”High”for Self-Refresh exit 1 1 1 Last data in to burst STOP command 1 1 1 Power Down Exit set-up time 1 1 1

CL* = 3 5.5 5.5 6 CL* = 2 6 7 7 CL* = 3 5.5 6 6

CL* = 2 6 7 7

3 3 3

Note:

1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.

2. All voltages are referenced to VSS.

3. These parameters depend on the cycle rate and these values are measured by the cycle rate under the minimum value of tCK and tRC.

4. These parameters depend on the output loading. Specified values are obtained with the outputs open.

5. Assume minimum column address update cycle t

CCD

(min).

Document:1G5-0189 Rev.1 Page 6

VG3617161ET

VIS

6. Power-up sequence is described in Note 10.

7. A.C. Test Conditions Reference Level of Output Signals 1.4V

Output Load Reference to the Under Output Load (B)

Input Signal Levels 2.4V / 0.4V

Transition Time (Rise and Fall) of Input Signals 1ns

Reference Level of Input Signals 1.4V

1,048,576 x 16 - Bit

CMOS Synchronous Dynamic RAM

3.3V

1.2K

Ω

ZO=50

Output

30pF

LVTTL D.C. Test Load (A)

8. Transition times are measured between VIH and VIL. Transition (rise and fall) of input signals are fixed slope (1 ns).

9. tHZ defines the time at which the outputs achieve the open circuit condition and are not reference levels.

10. Power up sequence Power up must be performed in the following sequence.

1) Power must be applied to VDD and V CKE = ”H”, DQM = ”H”. The CLK signals must be started at the same time.

2) After power-up, a pause of 200u secouds minimum is required. Then, it is recommended that DQM is held “high” (VDD levels) to ensure DQ output to be in the high impedance.

870

Ω

DDQ

Output

LVTTL A.C. Test Load (B)

(simultaneously) when all input signals are held “NOP” state and

Ω

1.4V 50

30pF

Ω

3) Both banks must be precharged.

4) Mode Register Set command must be asserted to initialize the Mode Register.

5) A minimum of 8 Auto-Refresh dummy cycles must be required to stabilize the internal circuitry of the device. Sequence of 4 and 5 may be changed.

Document:1G5-0189 Rev.1 Page 7

VG3617161ET

VIS

Basic Features and Function description

1.Simplified State Diagram

Mode

Register

Set

MRS

IDLE

1,048,576 x 16 - Bit

CMOS Synchronous Dynamic RAM

Self

Refresh

y

r

t

n

e

F

L

t

E

S

ACT

i

x

e

F

L

E

S

C

K

REF

C

K

E

AUTO

Refresh

Power

Down

WRITE

SUSPEND

WRITE A

SUSPEND

Write

CKE

Write with

Auto Precharge

CKE

WRITE A

WRITE

B

S

T

READ

READ A

Active Power

Down

Read

CKE

Read with

Auto Precharge

CKE

READ

SUSPEND

READ A

SUSPEND

ROW

ACTIVE

T

S

B

rite

W

A

u

t

P

R

E

(

P

r

h

t

i

w

h

e

t

d

i

r

e

r

W

p

o

t

u

A

Read

R

e

a

d

w

o

i

P

t

h

r

e

c

h

a

r

g

e

c

h

a

r

g

e

t

e

r

m

i

n

a

t

i

o

n

)

A

e

g

r

a

PRE

Write

A

CKE

Re

R

u

e

t

o

P

r

e

c

a

e

R

o

t

u

(

E

R

P

ad

a

d

w

i

t

h

a

r

g

e

h

e

t

i

g

w

r

a

d

h

c

e

r

P

)

n

o

i

t

a

n

i

m

r

e

t

e

g

r

a

h

c

e

r

P

POWER

ON

Precharge

Automatic sequence

Manual input

Note: After the AUTO refresh operation, precharge operation is

performed automatically and enter the IDLE state

Document:1G5-0189 Rev.1 Page 8

VG3617161ET

VIS

2.Truth Table

2.1 Command Truth Table

1,048,576 x 16 - Bit

CMOS Synchronous Dynamic RAM

CKE

FUNCTION Symbol

n-1 n

CS RAS CAS WE A11 A10

Device deselect DESL H X H X X X X X X No operation NOP H X L H H H X X X Mode register set MRS H X L L L L L L V Bank activate ACT H X L L H H Read READ H X L H L H Read with auto precharge READA H X L H L H Write WRIT H X L H L L Write with auto precharge WRITA H X L H L L Precharge select bank PRE H X L L H L

BS BS BS BS BS BS

(2)

Row Row

(2)

L H L H

L X Precharge all banks PALL H X L L H L X H X Burst stop BST H X L H H L X X X

Note: (1) Column address: A0~A7 (2) BS: Bank Select. L means Bank A and H means Bank B.

2.2 DQM Truth Table

CKE DQM

FUNCTION Symbol

n-1 n-1 UDQM LDQM Data write/output enable ENB H X L Data mask/output disable MASK H X H Upper byte write enable/output enable ENBU H X L X Lower byte write enable/output enable ENBL H X X L Upper byte write inhibit/output disable MASKU H X H X Lower byte inhibit/output disable MASKL H X X H

A9-

A0

Col Col Col Col

(1)

2.3 CKE Truth Table

Current State Function Symbol

CKE

n-1 n

CS RAS CAS WE

Add-

ress

Activating Clock suspend mode entry H L X X X X X Any Clock suspend L L X X X X X Clock suspend Clock suspend mode exit L H X X X X X Idle CBR refresh command REF H H L L L H X Idle Self refresh entry SELF H L L L L H X Self refresh Self refresh exit L H L H H H X

L H H X X X X Idle Power down entry H L X X X X X Power down Power down exit L H X X X X X

H : High level, L : Low level, X : high or Low level(Don’t care), V : Valid Data input

Document:1G5-0189 Rev.1 Page 9

VG3617161ET

endRow

→

endRow

→

stopRow

→

endwrite

→

endWrite

→

stopRow

→

1,048,576 x 16 - Bit

VIS

2.4 Operative Command Table

Current state CS RAS CAS WE Address Command Action Notes

Idle H X X X X DESL Nop or Power down 2

L H H X X NOP or BST Nop or Power down 2 L H L H BA,CA,A10 READ/READA ILLEGAL 3 L H L L BA,CA,A10 WRIT/WRITA ILLEGAL 3 L L H H BR,RA ACT Row active L L H L BA,A10 PRE/PALL Nop L L L H X REF/SELF Refresh or Self refresh 4 L L L L Op-Code MPS Mode register access

Row active H X X X X DESL Nop

L H H X X NOP or BST Nop L H L H BA,CA,A10 READ/READA Begin read:Determine AP 5 L H L L BA,CA,A10 WRIT/WRITA Begin write:Determine AP 5 L L H H BA,RA ACT ILLEGAL 3 L L H L BA,A10 PRE/PALL Precharge 6 L L L H X REF/SELF ILLEGAL L L L L Op-Code MRS ILLEGAL

Read H X X X X DESL

CMOS Synchronous Dynamic RAM

(1/3)

Continue burst to active

L H H H X NOP L H H L X BST L H L H BA,CA,A10 READ/READA Term burst, new read:Determine AP 7

L H L L BA,CA,A10 WRIT/WRITA Term burst, start write:Determine AP 7,8 L L H H BA,RA ACT ILLEGAL 3 L L H L BA,A10 PRE/PALL Term burst,precharging L L L H X REF/SELF ILLEGAL L L L L Op-Code MRS ILLEGAL

Write H X X X X DESL

L H H H X NOP L H H L X BST L H L H BA,CA,A10 READ/READA Term burst, start read: determine AP 7,8

L H L L BA,CA,A10 WRIT/WRITA Term burst, new write:Determine AP 7 L L H H BA,RA ACT ILLEGAL 3 L L H L BA,A10 PRE/PALL Term burst precharging 9 L L L H X REF/SELF ILLEGAL L L L L Op-Code MRS ILLEGAL

Continue burst to active Burst active

Continue burst to recovering Continue burst to recovering Burst active

Document:1G5-0189 Rev.1 Page 10

VG3617161ET

endPreching

arg→endPreching

arg

→

endWrite

→

endWrite

→

NopEnter

→

NopEnter

→

NopEnter

→

NopEnter

→

NopEnter

→

NopEnter

→

NopEnter

→

1,048,576 x 16 - Bit

VIS

Current state CS RAS CA WE Address Command Action Notes Read with auto

precharge

Write with auto precharge

Precharging H X X X X DESL

Row activating H X X X X DESL

H X X X X DESL

L H H H X NOP L H H L X BST ILLEGAL L H L H BA,CA,A10 READ/READA ILLEGAL L H L L BA,CA,A10 WRIT/WRITA ILLEGAL L L H H BA,RA ACT ILLEGAL 3 L L H L BA,A10 PRE/PALL ILLEGAL 3 L L L H X PEF/SELF ILLEGAL L L L L Op-Code MRS ILLEGAL

H X X X X DESL

L H H H X NOP

L H H L X BST ILLEGAL L H L H BA,CA,A10 READ/READA ILLEGAL L H L L BA,CA,A10 WRIT/WRITA ILLEGAL L L H H BA,RA ACT ILLEGAL 3 L L H L BA,A10 PRE/PALL ILLEGAL 3 L L L H X REF/SELF ILLEGAL L L L L Op-code MRS ILLEGAL

L H H H X NOP L H H L X BST L H L H BA,CA,A10 READ/READA ILLEGAL 3

L H L L BA,CA,A10 WRIT/WRITA ILLEGAL 3 L L H H BA,RA ACT ILLEGAL 3 L L H L BA,A10 PRE/PALL

L L L H X REF/SELF ILLEGAL L L L L Op-Code MRS ILLEGAL

L H H H X NOP L H H L X BST L H L H BA,CA,A10 READ/READA ILLEGAL 3

L H L L BA,CA,A10 WRIT/WRITA ILLEGAL 3 L L H H BA,RA ACT ILLEGAL 3,10 L L H L BA,A10 PRE/PALL ILLEGAL 3 L L L H X REF/SELF ILLEGAL L L L L Op-Code MRS ILLEGAL

CMOS Synchronous Dynamic RAM

(2/3)

Continue burst to Continue burst to

Continue burst to recovering with auto precharge

idle after t

row active after t row active after t row active after t

RP

RCD

Document:1G5-0189 Rev.1 Page 11

VG3617161ET

NopEnter

→

NopEnter

→

NopEnter

→

NopEnter

→

NopEnter

→

NopEnter

→

NopEnter

→

NopEnter

→

NopEnter

→

NopEnter

→

1,048,576 x 16 - Bit

VIS

Current state CS RAS CA WE Address Command Action Notes Write

recovering

Write recovering with auto precharge

Refreshing H X X X X DESL

Mode register accessing

H X X X X DESL

L H H H X NOP L H H L X BST L H L H BA,CA,A10 READ/READA Start read, Determine AP 8

L H L L BA,CA,A10 WRIT/WRITA New write, Determine AP L L H H BA,RA ACT ILLEGAL 3 L L H L BA,A10 PRE/PALL ILLEGAL 3 L L L H X PEF/SELF ILLEGAL L L L L Op-Code MRS ILLEGAL

H X X X X DESL

L H H H X NOP L H H L X BST

L H L H BA,CA,A10 READ/READA ILLEGAL 3,8 L H L L BA,CA,A10 WRIT/WRITA ILLEGAL 3 L L H H BA,RA ACT ILLEGAL 3 L L H L BA,A10 REF/PALL ILLEGAL 3 L L L H X REF/SELF ILLEGAL L L L L Op-Code MRS ILLEGAL

L H H X X NOP/BST L H L X X READ/WRIT ILLEGAL

L L H X X ACT/PRE/PALL ILLEGAL L L L X X REF/SELF/MRS ILLEGAL

H X X X X DESL

L H H H X NOP L H H L X BST ILLEGAL

L H L X X READ/WRITE ILLEGAL L L X X X ACT/PRE/PALL/

REF/SELF/MRS

CMOS Synchronous Dynamic RAM

(3/3)

row active after t row active after t

row active after t

precharge after t precharge after t

precharge after t

idle after t idle after t

idle after 2 Clocks idle after 2 Clocks

ILLEGAL

RC

DPL

Note 1. All entries assume that CKE was active (High level)during the preceding clock cycle.

2. If both banks are idle, and CKE is inactive(Low level), the device will enter Power down mode. All input buffers except CKE will be disabled.

3. Illegal to bank in specified states; Function may be legal in the bank indicated by Bank Address (BA), depending on the state of that bank.

4. If both banks are idle, and CKE is inactive(Low level), the device will enter Self refresh mode. All input buffers except CKE will be disabled.

5. IIIegal if t

6. IIIegal if t

7. Must satisfy burst interrupt condition.

8. Must satisfy bus contention, bus turn around, and/or write recovery requirements.

9. Must mask preceding data if t

10. IIIegal if t

is not satisfied.

RCD

is not satisfied.

RAS

is not satisfied.

RRD

is not satisfied.

DPL

Document:1G5-0189 Rev.1 Page 12

VG3617161ET

PDIdle

→

VIS

2.5 Command Truth Table for CKE

1,048,576 x 16 - Bit

CMOS Synchronous Dynamic RAM

Current state

Self refresh (SR)

Self refresh recovery

Power down (PD)

Both banks idle

Any state other than listed above

CKE

RASnCS RAS

n-1

H X X X

L H H X L H L H L H L H L H L L L L X X

H H H X H H L H H H L H

H H L L H L H X H L L H H L L H H L L L

L H X X L L X X

H X X X

L H X X L L X X

H H H X

H H L H

H H L L

H H L L H H L L

H L H X

H L L H

H L L L

H L L L H L L L

L X X X

H H X X

H L X X

L H X X L L X X

CAS WE Address Action Notes

X X X INVALID,CLK(n-1)would exit S.R. X X X SR Recovery 2

H X X SR Recovery 2

L X X ILLEGAL 2 X X X ILLEGAL 2 X X X Maintain S.R. X X X Idle after t

H X X Idle after t

RC RC

L X X ILLEGAL X X X ILLEGAL X X X Begin clock suspend next cycle 5

H X X Begin clock suspend next cycle 5

L X X ILLEGAL X X X ILLEGAL X X X Exit clock suspend next cycle 2 X X X Maintain clock suspend X X INVALID, CLK(n-1) would exit P.D. X X X

EXIT

2

X X X Maintain power down mode X X Refer to operations in Operative

Command Table

X X Refer to operations in Operative

Command Table

H X Refer to operation in Operative

Command Table L H X Refresh L L Op-

Code

Refer to operations in Operative

Command Table X X Refer to operations in Operative

Command Table

H X Refer to operations in Operative

Command Table L H X Self refresh 3 L L Op-

Code

Refer to operations in Operative

Command Table X X X Power down 3

X X X Refer to operations in Operative

Command Table X X X Begin clock suspend next cycle 4 X X X Exit clock suspend next cycle X X X Maintain clock suspend

Note 1. H : Hight level, L : low level, X : High or low level(Don't care).

2. CKE Low to High transition will re-enable CLK and other inputs asynchronously. A minimum setup time must be satisfied before any command other than EXIT.

3. Power down and Self refresh can be entered only from the both banks idle state.

4. Must be legal command as defined in Operative Command Table. 5 .IIIegal if t

Document:1G5-0189 Rev.1 Page 13

is not satisfied.

SRX

VG3617161ET

1,048,576 x 16 - Bit

VIS

3.Initiallization

The synchronous DRAM is initialized in the power on sequence. Once power has been applied, a 200us minimum delay is needed in which stable power and input signals are maintained. During this delay, CKE and DQM recommend to be held high.

After the 200us delay, both banks must be precharged using the precharge command. Once precharge is completed and the minimum tRP is satisfied, the mode register can be programmed.

Minimum 8 CBR refresh cycles must be performed before or after the mode register set command.

4.Programming the Mode Register

The mode register is programmed by the mode register set command using address bits A11 through

A0 as data inputs. The register retains data until it is reprogrammed or until the device loses power.

The mode register has four fields;

Options : A11 through A7 CAS latency : A6 through A4 Wrap type : A3 Burst length : A2 through A0

Following mode register programming, no command can be asserted befor at least two clock cycles

have elapsed.

CMOS Synchronous Dynamic RAM

CAS Latency

CAS latency is the most critical parameter to be set. It tells the device how many clocks must elapse before the data will be available. The SDRAM is capable of reconfiguring its internal architecture based on the value of CAS latency.

The value is determined by the frequency of the clock and the speed grade of the device. The value can be programmed as 2 or 3.

Burst Length

Burst Length is the number of words that will be output or input in read or write cycle. After a read burst

is completed, the output bus will become high impedance.

The burst length is programmable as 1,2,4,8 or full page.

Wrap Type (Burst Sequence)

The wrap type specifies the order in which the burst data will be addressed. The order is programmable

as either “Sequential” or “Interleave”. The method chosen will depend on the type of CPU in the system.

Some microprocessor cache systems are optimized for sequential addressing and others for interleaved addressing. Both sequences support bursts of 1,2,4 and 8. Only the sequential burst. supports the full-page length.

Document:1G5-0189 Rev.1 Page 14

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5.Mode Register

VG3617161ET

1,048,576 x 16 - Bit

CMOS Synchronous Dynamic RAM

11

0 0

11

0

10

0

8

9

1

9

0

0 0 8

0 0

7

5

6

LTMODE

5

6

LTMODE

3

4

WT

3

4

WT

1

2

BL

0

Burst Read and Single Write

1

0

Mode Register Set

Burst length

Wrap type

X=Don’t care

Bits2-0

000 001

010 011

100 101 110

111

01Sequential

Interleave

WT=0

1 2

4 8 R R R

Full page

WT=1

1 2

4 8

R R R

R

Latency

mode

Remark R:Reserved

Bits6-4

000 001

010 011 100 101 110

111

CAS Iatency

R R

2 3 R R R

R

Document:1G5-0189 Rev.1 Page 15

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5.1 Burst Length and Sequence

(Burst Length= 2)

1,048,576 x 16 - Bit

CMOS Synchronous Dynamic RAM

Starting Address (column address A0, binary)

0 0,1 0,1 1 1,0 1,0

(Burst Length=4)

Starting Address (column address A1-A0, binary)

00 0,1,2,3 0,1,2,3 01 1,2,3,0 1,0,3,2 10 2,3,0,1 2,3,0,1 11 3,0,1,2 3,2,1,0

(Burst Length=8)

Starting Address (column address A2-A0, binary)

Sequential Addressing Sequence (decimal)

Interleave Addressing Sequence(decimal)

Interl eave Addressing

Sequence(decimal) 000 0,1,2,3,4,5,6,7 0,1,2,3,4,5,6,7 001 1,2,3,4,5,6,7,0 1,0,3,2,5,4,7,6 010 2,3,4,5,6,7,0,1 2,3,0,1,6,7,4,5 011 3,4,5,6,7,0,1,2 3,2,1,0,7,6,5,4 100 4,5,6,7,0,1,2,3 4,5,6,7,0,1,2,3 101 5,6,7,0,1,2,3,4 5,4,7,6,1,0,3,2 110 6,7,0,1,2,3,4,5 6,7,4,5,2,3,0,1 111 7,0,1,2,3,4,5,6 7,6,5,4,3,2,1,0

Full page burst is an extension of the above tables of sequential addressing, with the length being 256

words.

Document:1G5-0189 Rev.1 Page 16

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6.Address Bits of Bank-Select and Precharge

1,048,576 x 16 - Bit

CMOS Synchronous Dynamic RAM

A0

Row

(Activate command)

A0

Row (Precharge)

A0

Col.

(CAS strobes)

A2A1

A3

A4

A5

A6

A7

A8

A9

A10

A11

0

Select Bank A ”Activate” command

1

Select Bank B ”Activate” command

Result

A11

A10

0

0 0

1

0 1

Precharge Bank A

1

Precharge Bank B

x

Precharge All Banks

x:Don’t care

Disable Auto-Precharge (End of Burst) Enable Auto-Precharge (End of Burst)

Enable Read/Write commands for Bank A

0

Enable Read/Write commands for Bank B

1

Document:1G5-0189 Rev.1 Page 17

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7.PRECHARGE

VG3617161ET

1,048,576 x 16 - Bit

CMOS Synchronous Dynamic RAM

The PRECHARGE command can be asserted anytime after t

RAS(min)

is satisfied.

Soon after the PRECHARGE command is asserted, PRECHARGE operation is performed. The synchronous DRAM

enters the idle state after t

is satisfied. The parameter tRP is the time required to perform the PRECHARGE.

RP(min)

The earliest timing in a READ cycle that a PRECHARGE command can be asserted without losing any data in the

burst is as followed.

PRECHARGE

CLK

Command

CAS latency=2

DQ

Command

CAS latency=3

T0 T1

Read

T2

T3

Q0 Q3Q2

T4 T5

PRE

Q1

PRE

T6

Hi-Z

Burst lengh=4

T7

DQ

CAS latency= 2: One clock earlier than the last output data. 3: Two clocks earlier than the last output data.

In order to write all data to the memory cell correctly, the asynchronous parameter”t

The t

DPL(MIN.)

cycle. The minimum number of clocks are calculated by dividing t

specification defines the earliest time that a PRECHARGE command can be asserted after a WRITE

DPL(min.)

Q0

Q1

” must be satisfied.

DPL

by the clock cycle time.

Q2

In summary, the PRECHARGE command can be asserted relative to the reference clock of the last valid

data. In the following table, minus means clocks before the reference, plus means time after the reference.

CAS latency READ WRITE

2 -1 +t

DPL(min.)

Q3

(t

RAS

Hi-Z

is satisfied)

3 -2 +t

DPL(min)

Document:1G5-0189 Rev.1 Page 18

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1,048,576 x 16 - Bit

VIS

8.AUTO PRECHARGE

During a READ or WRITE command cycle, A10 controls whether AUTO PRECHARGE is selected. If A10 is high in the READ or WRITE command (READ with AUTO PRECHARGE command or WRITE with AUTO PRECHARGE command), AUTO PRECHARGE is selected and precharging begins automatically after the burst access.

In the WRITE cycle, t

DAL(min.)

charged.

When using AUTO PRECHARGE in the READ cycle, knowing when the PRECHARGE starts is important because the t

be asserted after t

must be satisfied. Once AUTO PRECHARGE has started, an active command to the bank can

RAS

has been satisfied.

RP(min.)

The timing at which the AUTO PRECHARGE cycle begins depends both on the CAS Iatency programmed into the mode register and on whether the cycle is READ or WRITE.

8.1 READ with AUTO PRECHARGE

During a READA cycle, the AUTO PRECHARGE begins one clock earlier(CAS Iatency of 2) or two

clocks earlier(CAS Iatency of 3) than the last data word output.

must be satisfied to assert the next active command to the bank being pre-

CMOS Synchronous Dynamic RAM

READ with AUTO PRECHARGE

CLK

Command

CAS latency=2

DQ

Command

CAS latency=3

DQ

T0 T1

READA B

Burst lengh=4

QB0

T3

QB1

QB0

QB0 QB1

T4 T5

Auto precharge starts

T2

T6

QB3QB2

QB2QB1

QB3

T7

Hi-Z

T8

Remark: READA means READ with AUTO PRECHARGE

Document:1G5-0189 Rev.1 Page 19

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8.2 WRITE with AUTO PRECHARGE

During a WRITA cycle, the AUTO PRECHARGE starts at t

the device

WRITE with AUTO PRECHRGE

T0 T1

CLK

1,048,576 x 16 - Bit

CMOS Synchronous Dynamic RAM

DPL(min.)

T2

T3

after the last data word input to

T4 T5

T6

Burst lengh=4 T7

T8

Command

CAS latency=2

DQ

Command

CAS latency=3

DQ

Remark WRITA means WRITE with AUTO PRECHARGE

WRITA B

DB0

WRITA B

DB0

DB1

AUTO PRECHARGE starts

t

DPL

DB3DB2

AUTO PRECHARGE starts

t

DPL

DB3DB2

Hi-Z_

In summary, the auto precharge cycle begins relative to a reference clock that indicates the last data word is valid. In the table below, minus means clocks before the reference; plus means clocks after the reference.

CAS latency READ WRITE

2 -1 +t

3 -2 +t

DPL(min.)

DPL(min)

Document:1G5-0189 Rev.1 Page 20

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9.READ/WRITE Command Interval

9.1 READ to READ command interval

When a new READ command is asserted during a READ cycle, it will be effective after the CAS latency,

even if the previous READ operation has not completed. READ will be interrupted by another READ.

A READ command can be asserted in every clock without restriction.

READ to READ Command Interval

CLK

T0 T1

T2

T3

CMOS Synchronous Dynamic RAM

T4 T5

1,048,576 x 16 - Bit

Burst lengh=4, CAS latency=2

T6

T7

T8

1 cycle

Read B

QA0

QB0

QB2QB1

Command

DQ

Read A

9.2 WRITE to WRITE Command Interval

When a new WRITE command is asserted during a WRITE cycle, the previous burst will be terminated

and the new burst will begin with the new WRITE command. WRITE will be interrupted by another WRITE.

A WRITE command can be asserted in every clock without restriction.

WRITE to WRITE Command Interval

Burst lengh=4, CAS latency=2

CLK

T0 T1

T2

T3

T4 T5

T6

QB3

Hi-Z_

T7

T8

1 cycle

Write B

QB0

QB2QB1

QB3

Hi-Z_

Command

DQ

Write A

QA0

Document:1G5-0189 Rev.1 Page 21

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9.3 WRITE to READ Command Interval

The WRITE command to READ command interval is a minimum of 1 cycle. Only the WRITE data preceding the READ command will be written. The data bus must be in high-impedance at least one cycle prior to the first D

WRITE to READ Command Interval

CLK

OUT

.

T0 T1

1 cycle

T2

T3

CMOS Synchronous Dynamic RAM

T4 T5

T6

1,048,576 x 16 - Bit

Burst lengh=4

T7

T8

Command

CAS latency=2

DQ

Command

CAS latency=3

DQ

WRITE A

DA0

Write A

DA0

Read B

Hi-Z

QB0

QB1

QB0

QB1

9.4 READ to WRITE Command Interval

During READ cycle, READ can be interrupted by WRITE. The data bus must be in high-impedance using DQM before the WRITE command. DQM must be high at least 3 clocks prior to the WRITE command. This restriction is necessary to avoid a data bus conflict.

QB3QB2

QB2

QB3

Document:1G5-0189 Rev.1 Page 22

VG3617161ET

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READ to WRITE Command Interval

1,048,576 x 16 - Bit

CMOS Synchronous Dynamic RAM

CLK

Command

DQM

DQ

CLK

Command

T0 T1

Hi-Z

T0 T1

Read

1 cycle

T2

D0

Write

CAS latency=2

T7

T8

T9

D1

T3

T4 T5

D3D2

T6

T2

T3

T6

Burst length=8, CAS latency=2

T7

Write

DQM

DQ

CLK

Command

DQM

DQ

Q0

T0 T1

Read

The minimum command interval = (4+1) cycles

T2

Q1

Q2

Hi-Z is

necessary

T3

Q2

T4 T5

Hi-Z is

necessary

D0

example: Burst length=4, CAS latency=3

T6

Write

D0

D1

T7

D1

D2

T8

D2

Document:1G5-0189 Rev.1 Page 23

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10.BURST TERMINATION

There are two methods to terminate a BURST operation other than using a READ or a WRITE command.

One is the BURST STOP command and the other is the PRECHARGE command.

10.1 BURST STOP Command

During a READ BURST. when the BURST STOP command is asserted, the BURST READ outputs are terminated and the data bus goes to high-impedance after the CAS latency from the BURST STOP command.

During a WRITE BURST. when the BURST STOP command is asserted, any data provided at that cycle will not be written. The BURST WRITE is effectively terminated and no further data can be written until a new WRITE command is asserted.

Burst Termination

CLK

T0 T1

T2

T3

1,048,576 x 16 - Bit

CMOS Synchronous Dynamic RAM

Burst lengh=X, CAS Intency=2,3

T4 T5

T6

T7

Command

CAS latency=1

DQ

CAS latency=2

DQ

CAS latency=3

DQ

Remark BST: Burst stop command

CLK

Read

T0 T1

Q0

T2

Q0

Q1

T3

BST

Q2

Q1

Q0

Hi-Z

Q2

Q1

T4 T5

Hi-Z

Q2

Burst lengh=X, CAS latency=1,2,3

T6

Hi-Z

T7

Command

CAS latency=1,2,3

DQ

Write

Q0

Q1

Q2

BST

Hi-Z_

Remark BST: Burst stop command

Document:1G5-0189 Rev.1 Page 24

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10.2 PRECHARGE TERMINATION

10.2.1 PRECHARGE TERMINATION in READ Cycle

During a READ cycle, the BURST READ operation can be terminated by a PRECHARGE command. When the PRECHARGE command is asserted, the BURST READ operation is terminated and PRECHARGE starts.

Read data will remain valid until zero clock(CAS latency of 1), one clock(CAS latency of 2)or two clocks(CAS latency of 3) after the PRECHARGE command and the same bank can be activated again after t

PRECHARGE TERMINATION in READ Cycle

from the PRECHARGE command.

RP(min)

1,048,576 x 16 - Bit

CMOS Synchronous Dynamic RAM

CLK

Command

CAS latency=1

DQ

Command

CAS latency=2

DQ

command

CAS latency=3

DQ

T0 T1

Read

Read PRE

T2

Q0 Q3

T3

Q1

Q0 Q3

Q2

Q1

Q0 Q3

T4 T5

PRE

PRE ACT

Q2

Q1

ACT

t

RP

t

RP

t

RP

Q2

Hi-Z

T6

t

RP

T7

Hi-Z

Burst lengh= X

T8

ACT

Hi-Z

Document:1G5-0189 Rev.1 Page 25

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10.2.2 PRECHARGE TERMINATION in WRITE Cycle

During a WRITE cycle, the BURST WRITE operation can be terminated by a PRECHARGE command. when the PRECHARGE command is asserted, the BURST WRITE operation in immediately terminated and PRECHARGE starts.

The same bank can be activated again after tRP(min.) from the PRECHARGE command. The DQM must be high to mask invalid data in.

When CAS latency is 1, 2 or 3, the data written prior to the PRECHARGE command will be correctly stored. However, invalid data may be written at the same clock as the PRECHARGE command. To prevent this from happening, DQM must be high at the same clock as the PRECHARGE command. This will mask the invalid data.

PRECHARGE TERMINATION in WRITE Cycle

T0 T1

CLK

1,048,576 x 16 - Bit

CMOS Synchronous Dynamic RAM

T2

T3

T4 T5

T6

Burst lengh = X

T7

T8

Command

CAS latency=1 DQM

DQ

Command

CAS latency=2

DQM

DQ

command

CAS latency=3

DQM

DQ

Write

D0 D3

Write

D0 D3

Write PRE ACT

D0 D3

D1

D2

PRE ACT

t

RP

D4

t

RP

PRE ACT

D4

t

RP

D4

Hi-Z

Document:1G5-0189 Rev.1 Page 26

VIS

VG3617161ET

1,048,576 x 16 - Bit

CMOS Synchronous Dynamic RAM

Timing Diagram

Document:1G5-0189 Rev.1 Page 27

VIS

Mode Register Set

VG3617161ET

1,048,576 x 16 - Bit

CMOS Synchronous Dynamic RAM

CLK

CKE

CS

RAS

CAS

WE

A11(BS)

T0

T1

T2

T3

T4

t

RSC

T5 T6

T7 T8

T9

T10

A10

A0-A9

DQM

DQ

Hi-Z

Precharge Command All Banks

t

RP

Key

Mode Register Set Command

Command

Document:1G5-0189 Rev.1 Page 28

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AC Parameters for Write Timing (1 of 2)

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

1,048,576 x 16 - Bit

CMOS Synchronous Dynamic RAM

Burst Length=4, CAS Latency=2

CLK

CKE

CS

RAS

CAS

WE

BS

t

CL

t

CH

t

CKS

CMS

t

CMH

t

CK2

Begin Auto Precharge Bank A

Begin Auto Precharge

(Bank D)

Bank B

t

CKH

A10

t

AS

AH

ADD

DQM

t

Activate Command

Bank A

RCD

t

RRD

QAa0

Write with Auto Precharge Command Bank A

t

RC

QAa1

QAa2 QAa3 QBa0

Activate Command Bank B

(Bank D)

t

DAL

QBa1

Write with Auto Precharge Command Bank B

(Bank D)

QBa2 QBa3

Activate Command Bank A

t

DS

QAb0

QAb1

Write without Auto Precharge Command Bank A

t

DPL

Precharge Command

Bank A

RP

Activate

Command

Bank A

Activate

Command

Bank B

(Bank D)

t

DH

QAb2

QAb3

DQ

Document:1G5-0189 Rev.1 Page 29

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AC Parameters for Write Timing (2 of 2)

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23

1,048,576 x 16 - Bit

CMOS Synchronous Dynamic RAM

Burst Length=4, CAS Latency=3

CLK

CKE

CS

RAS

CAS

WE

BS

t

CH

t

CKS

CL

t

CMS

t

CMH

t

CK3

Begin Auto Precharge Bank A

Begin Auto Precharge Bank B

(Bank D)

t

CKH

A10

t

AS

AH

ADD

DQM

t

RCD

DQ

Activate Command

Bank A

t

RRD

QAa0

Write with Auto Precharge Command Bank A

QAa1

Activate Command Bank B

(Bank D)

t

RC

QAa2

QAa3 QBa0 QBa1

t

DAL

Write with Auto Precharge Command Bank B

(Bank D)

QBa2

QBa3

Activate Command Bank A

t

DS

t

DH

QAb0 QAb1 QAb2

Write without Auto Precharge Command Bank A

QAb3

t

DPL

Precharge Command

Bank A

t

RP

Activate

Command

Bank A

Document:1G5-0189 Rev.1 Page 30

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AC Parameters for Read Timing (1 of 2)

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13

1,048,576 x 16 - Bit

CMOS Synchronous Dynamic RAM

Burst Length=2, CAS Latency=2

CLK

CKE

CS

RAS

CAS

WE

A11(BS)

A10

A0-A9

tCHt

t

CKS

CL

t

AS

RAa

t

AH

t

CK2

t

CMS

t

CMH

t

RRD

RBa

RBaCAaRAa

t

RAS

Begin Auto Precharge Bank B

CBa

t

RC

t

CKH

RAb

DQM

t

DQ

Hi-Z

Activate Command Bank A

t

RCD

Read Command Bank A

t

AC2

t

LZ

AC2

t

OH

QAa0

Activate Command Bank B

t

HZ

t

OH

QAa1

Read with

Auto Precharge

Bank B

QBa0

Precharge Command Bank A

t

RP

QBa1

t

HZ

Activate Command Bank A

Document:1G5-0189 Rev.1 Page 31

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AC Parameters for Read Timing (2 of 2)

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15

1,048,576 x 16 - Bit

CMOS Synchronous Dynamic RAM

Burst Length=2, CAS Latency=3

CLK

CKE

CS

RAS

CAS

WE

A11(BS)

A10

A0-A9

DQM

t

CH

t

CKS

t

CL

RAa

t

AS

RAa

t

AH

CK3

t

CMS

t

CMH

t

RRD

CAa

t

RAS

RBa

t

RC

CBa

Begin Auto Precharge Bank B

t

RP

RAb

t

CKH

t

AC3

t

OH

QAa1

t

HZ

t

OH

Read with Auto Precharge Command Bank B

Precharge Command

Bank A

QBa0

QBa1

t

HZ

Activate

Command

Bank A

DQ

Hi-Z

Activate Command Bank A

t

RCD

Read Command Bank A

t

AC3

t

LZ

Activate Command Bank B

QAa0

Document:1G5-0189 Rev.1 Page 32

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Power on Sequence and Auto Refresh (CBR)

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CLK

1,048,576 x 16 - Bit

CMOS Synchronous Dynamic RAM

CKE

CS

RAS

CAS

WE

A11(BS)

A10

High level is required

Minimum of 8 Refresh Cycles are required

t

RSC

Address Key

A0~A9

DQM

High Level is Necessary

t

RP

t

RC

DQ

Inputs must

be stable for 200us

Precharge Command

All Banks

1st Auto Refresh

Command

2nd Auto Refresh Command

Mode Register Set Command

Command

Document:1G5-0189 Rev.1 Page 33

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Clock Suspension During Burst Read (Using CKE) (1 of 2)

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

1,048,576 x 16 - Bit

CMOS Synchronous Dynamic RAM

Burst Length=4, CAS Latency=2

CLK

CKE

CS

RAS

CAS

WE

A11(BS)

t

CK2

Hi-Z

RAa

Activate

Command

Bank A

CAa

Read Command

Bank A

QAa0 QAa1

Suspended

Clock 1 Cycle

QAa2

Clock

Suspended

2 Cycles

QAa3

t

HZ

Clock

Suspended

3 Cycles

A10

A0~A9

DQM

DQ

Document:1G5-0189 Rev.1 Page 34

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Clock Suspension During Burst Read (Using CKE) (2 of 2)

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

1,048,576 x 16 - Bit

CMOS Synchronous Dynamic RAM

Burst Length=4, CAS Latency=3

CLK

CKE

CS

RAS

CAS

WE

A11(BS)

t

CK3

Hi-Z

RAa

Activate

Command

Bank A

CAa

Read

Command

Bank A

QAa0

QAa1

Clock

Suspended

1 Cycle

QAa2 QAa3

Clock

Suspended

2 Cycles

t

HZ

Clock

Suspended

3 Cycles

A10

A0~A9

DQM

DQ

Document:1G5-0189 Rev.1 Page 35

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Clock Suspension During burst Write (Using CKE) (1 of 2)

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

1,048,576 x 16 - Bit

CMOS Synchronous Dynamic RAM

Burst Length=4, CAS Latency=2

CLK

CKE

CS

RAS

CAS

WE

A11(BS)

t

CK2

A10

A0~A9

RAa

CAa

DQM

DQ

Hi-Z

Activate

Command

Bank A

QAa0 QAa1

Clock

Suspended

1 Cycle

Write

Command Bank A

Clock

Suspended

2 Cycles

QAa2

Clock

Suspended

3 Cycles

QAa3

Document:1G5-0189 Rev.1 Page 36

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VIS

Clock suspension during Burst write (Using CKE) (2 of 2)

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

1,048,576 x 16 - Bit

CMOS Synchronous Dynamic RAM

Burst Length=4, CAS Latency=3

CLK

CKE

CS

RAS

CAS

WE

A11(BS)

t

CK3

Hi-Z

RAa

Activate

Command

Bank A

QAa0

Suspended

Write

Command Bank A

CAa

QAa1 QAa2

Clock 1 Cycle

Suspended

Clock 2 Cycles

Clock

Suspended

3 Cycles

t

QAa3

A10

A0~A9

DQM

DQ

Document:1G5-0189 Rev.1 Page 37

VG3617161ET

VIS

Power Down Mode and Clock Mask

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

1,048,576 x 16 - Bit

CMOS Synchronous Dynamic RAM

Burst Length=4, CAS Latency=2

CLK

CKE

CS

RAS

CAS

WE

BS

t

CK2

t

CKS

t

CKH

VALID

t

CKS

RAa

Hi-Z

RAa

Activate

Command

Bank A

Power Down

Mode Entry

ACTIVE

STANDBY

CAa

Read Command Bank A

Power Down Mode Exit

QAa0

QAa1

Clock Mask

Start

QAa2

Clock Mask

End

t

HZ

QAa3

Precharge

Command

Power Down

Mode Entry

Precharge Standby

Power

Down

Mode Exit

Command

A10

A0~A9

DQM

DQ

Document:1G5-0189 Rev.1 Page 38

VIS

Auto Refresh (CBR)

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CLK

t

CKE

CS

VG3617161ET

1,048,576 x 16 - Bit

CMOS Synchronous Dynamic RAM

Burst Length=4, CAS Latency=2

CK2

RAS

CAS

WE

BS

A10

ADD

DQM

DQ

Hi-Z

RAa

t

RP

t

RC

t

RC

CAa

Q0

Q1

Q2

Q3

Precharge

Command

All Banks

CBR Refresh Command

CBR Refresh

Command

Activate Command

Write

Command

Document:1G5-0189 Rev.1 Page 39

VG3617161ET

VIS

Self Refresh (Entry and Exit)

1,048,576 x 16 - Bit

CMOS Synchronous Dynamic RAM

CLK

CKE

CS

RAS

CAS

WE

CLK can be Stopped

*

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

t

CKS

t

SRX

t

SRX

t

CKS

BS

A10

ADD

DQM

DQ

Hi-Z

All Banks must be idle

Self refresh

Entry

Self Refresh

Exit

t

RC

Self Refresh

Entry

Self Refresh

Exit

t

RC

Activate

Command

* Clock can be stopped at CKE=Low. If clock is stopped, it must be restarted/stable for 4 clock cycles before CKE=High

Document:1G5-0189 Rev.1 Page 40

VG3617161ET

VIS

Random Column Read (Page Within same Bank)(1 of 2)

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

1,048,576 x 16 - Bit

CMOS Synchronous Dynamic RAM

Burst Length=4, CAS Latency=2

CLK

CKE

CS

RAS

CAS

WE

A11(BS)

t

CK2

A10

A0~A9

RAa

CAa

CAb

CAc

RAa

RAd

CAd

DQM

DQ

Hi-Z

Active

Command

Bank A

Read

Command

Bank A

QAa0 QAa1

QAa2 QAa3

Read

Command

Bank A

QAb0

QAb1

Read

Command

Bank A

QAc0

QAc1

Precharge

Command

Bank A

QAc2

QAc3

Activate

Command

Bank A

Read

Command

Bank A

QAd0

QAd1

QAd2

Document:1G5-0189 Rev.1 Page 41

QAd3

VG3617161ET

VIS

Random Column Read (Page Within same Bank)(2 of 2)

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

1,048,576 x 16 - Bit

CMOS Synchronous Dynamic RAM

Burst Length=4, CAS Latency=3

CLK

CKE

CS

RAS

CAS

WE

A11(BS)

t

CK3

A10

A0~A9

RAa

CAa

CAb

CAc RAd

RAd

CAd

DQM

DQ

Hi-Z

Activate

Command

Bank A

Read

Command

Bank A

QAa0 QAa1

Read

Command

Bank A

QAa2

QAa3

Read

Command

Bank A

QAb0

QAb1

QAc0

QAc1

Precharge

Command

Bank A

QAc2 QAc3

Activate

Command

Bank A

Read

Command

Bank A

Document:1G5-0189 Rev.1 Page 42

VG3617161ET

VIS

Random Column Write (Page Within same Bank) (1 of 2)

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

1,048,576 x 16 - Bit

CMOS Synchronous Dynamic RAM

Burst Length=4, CAS Latency=2

CLK

CKE

CS

RAS

CAS

WE

A11(BS)

t

CK2

A10

A0~A9

RAa

RBa

CBa

CBb

CBc RBd

RAd

CBd

DQM

DQ

Hi-Z

Activate

Command

Bank B

DBa0

Write

Command

Bank B

DBa1

DBa2

DBb0

DBa3

Write

Command

Bank B

DBb1

Write

Command

Bank B

DBc0

DBc1

DBc2 DBc3

Precharge

Command

Bank B

Activate

Command

Bank B

DBd0

DBd1

Write

Command

Bank B

DBd2

DBd3

Document:1G5-0189 Rev.1 Page 43

VG3617161ET

VIS

Random Column Write (Page Within same Bank) (2 of 2)

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

1,048,576 x 16 - Bit

CMOS Synchronous Dynamic RAM

Burst Length=4, CAS Latency=3

CLK

CKE

CS

RAS

CAS

WE

A11(BS)

t

CK3

A10

A0~A9

RBa

CBa

CBb

RBd

CBc RBd

CBd

DQM

DQ

Hi-Z

Activate

Command

Bank B

DBa0

Write

Command

Bank B

DBa1

DBa2

DBb0

DBa3

Write

Command

Bank B

DBb1

DBc0

Write

Command

Bank B

DBc1

DBc2

DBc3

Precharge

Command

Bank B

Activate

Command

Bank B

DBd0

DBd1

Write

Command

Bank B

Document:1G5-0189 Rev.1 Page 44

DBd2

VG3617161ET

VIS

Random Row Read (Interleaving Banks) (1 of 2)

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

1,048,576 x 16 - Bit

CMOS Synchronous Dynamic RAM

Burst Length=8, CAS Latency=2

CLK

CKE

CS

RAS

CAS

WE

A11(BS)

High

t

CK2

A10

A0~A9

RBa

t

RCD

CBa

t

AC2

RAa

CAa

t

RP

RBb

CBb

DQM

DQ

Hi-Z

Activate

Command

Bank B

Read

Command

Bank B

QBa0

QBa1

QBa2

QBa4

QBa3

Activate

Command

Bank A

QBa5

QBa6

Read

Command

Bank A

QBa7

Precharge

Command

Bank B

QAa0

Active

Command

Bank B

QAa1

QAa2

QAa3

QAa4

QAa5

QAa6

QAa7

Read

Command

Bank B

QBb0

Document:1G5-0189 Rev.1 Page 45

QBb1

VG3617161ET

VIS

Random Row Read (Interleaving Banks) (2 of 2)

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

1,048,576 x 16 - Bit

CMOS Synchronous Dynamic RAM

Burst Length=8, CAS Latency=3

CLK

CKE

CS

RAS

CAS

WE

A11(BS)

High

t

CK3

A10

A0~A9

RBa

t

RCD

CBa

t

AC3

RAa

CAa

RBb

t

RP

CBb

DQM

DQ

Hi-Z

Activate

Command

Bank B

Read

Command

Bank B

QBa0

QBa2

QBa1

Activate

Command

Bank A

QBa3

QBa5

QBa4

Read

Command

Bank A

QBa6

Precharge

Command

Bank B

QBa7

QAa0

QAa1

QAa2

Activate

Command

Bank B

QAa3

QAa4

QAa6

QAa5

Read

Command

Bank B

QAa7

Precharge

Command

Bank B

Document:1G5-0189 Rev.1 Page 46

QBb0

VG3617161ET

VIS

Random Row Write (Interleaving Banks) (1 of 2)

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

1,048,576 x 16 - Bit

CMOS Synchronous Dynamic RAM

Burst Length=8, CAS Latency=2

CLK

CKE

CS

RAS

CAS

WE

A11(BS)

High

t

CK2

A10

A0~A9

DQM

DQ

RAa

Hi-Z

Activate

Command

Bank A

t

RCD

QAa0

Write

Command

Bank A

CAa

QAa1 QAa2

QAa3

QAa4

RBa

QAa5

QAa6

Activate

Command

Bank B

t

DPL

QAa7

QBa0 QBa1

Write

Command

Bank B

CBa

Precharge

Command

Bank A

t

RP

QBa2

Command

Bank A

RAb

QBa3 QBa4

Active

QBa5

QBa6 QBa7

Command

DAb0 DAb1

Write

Bank A

CAb

t

DPL

DAb2

Precharge

Command

Bank B

DAb3

Document:1G5-0189 Rev.1 Page 47

DAb4

VG3617161ET

VIS

Random Row Write (Interleaving Banks) (2 of 2)

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

1,048,576 x 16 - Bit

CMOS Synchronous Dynamic RAM

Burst Length=8, CAS Latency=3

CLK

CKE

CS

RAS

CAS

WE

A11(BS)

High

t

CK3

A10

A0~A9

DQM

DQ

RAa

Hi-Z

Activate

Command

Bank A

t

RCD

CAa

DAa0 DAa1

Write

Command

Bank A

DAa2

DAa3

RBa RAb

RBa

RBa RAb CBa

t

DPL

DAa4

DAa5

Activate

Command

Bank B

DAa6

DBa0

DAa7

Write

Command

Bank B

DBa1

Precharge

Command

DBa2 DBa3

Bank A

t

RP

DBa4

QBa5 DBa6

Activate

Command

Bank A

CAb

DBb7 DAb0

Write

Command

Bank A

t

DPL

DAb1

Precharge

Command

DAb2

Bank B

Document:1G5-0189 Rev.1 Page 48

DAb3

VG3617161ET

VIS

Read and Write Cycle (1 of 2)

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

1,048,576 x 16 - Bit

CMOS Synchronous Dynamic RAM

Burst Length=4, CAS Latency=2

CLK

CKE

CS

RAS

CAS

WE

A11(BS)

t

CK2

A10

A0~A9

RAa

CAa

CAb

CAc

DQM

DQ

Hi-Z

Activate

Command

Bank A

Read

Command

Bank A

QAa0 QAa1

QAa2

QAa3

DAb0

Write

Command

Bank A

DAb1

The Write Data

is Masked with a

Zero Clock

latency

DAb3

Read

Command

Bank A

QAc0

QAc1

The Read Data

is Masked with

QAc3

Two Clocks

Latency

Document:1G5-0189 Rev.1 Page 49

VG3617161ET

VIS

Read and Write Cycle (2 of 2)

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

1,048,576 x 16 - Bit

CMOS Synchronous Dynamic RAM

Burst Length=4, CAS Latency=3

CLK

CKE

CS

RAS

CAS

WE

A11(BS)

t

CK3

A10

A0~A9

RAa

CAa

CAb

CAc

DQM

DQ

Hi-Z

Activate

Command

Bank A

Read

Command

Bank A

QAa0

QAa1

QAa2

QAa3

DAb0

Write

Command

Bank A

DAb1

The Write Data

is Masked with a

Zero Clock

latency

DAb3

Read

Command

Bank A

QAc0

QAc1

The Read Data

is Masked with

Two Clock

Latency

Document:1G5-0189 Rev.1 Page 50

QAc3

VG3617161ET

VIS

Interleaved Column Read Cycle (1 of 2)

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

1,048,576 x 16 - Bit

CMOS Synchronous Dynamic RAM

Burst Length=4, CAS Latency=2

CLK

CKE

CS

RAS

CAS

WE

A11(BS)

t

CK2

A10

A0~A9

DQM

DQ

Hi-Z

RAa

t

Activate

Command

Bank A

RCD

Read

Command

Bank A

CAa

RBa

t

AC2

QAa0 QAa1

Activate

Command

Bank B

CBa CBb CBc CAb CBd

QAa3

QAa2

Read

Command

Bank B

QBa0

QBa1

Read

Command

Bank B

QBb0 QAb0

Read

Command

Bank B

QBc0

Read

Command

Bank A

QBc1

QBb1 QBd0

Read

Command

Bank B

Precharge Command

Bank A

QAb1

QBd1

QBd2

QBd3

Precharge Command

Bank B

Document:1G5-0189 Rev.1 Page 51

VG3617161ET

VIS

Interleaved Column Read Cycle (2 of 2)

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

1,048,576 x 16 - Bit

CMOS Synchronous Dynamic RAM

Burst Length=4, CAS Latency=3

CLK

CKE

CS

RAS

CAS

WE

A11(BS)

t

CK3

A10

A0~A9

DQM

DQ

Hi-Z

RAa

Activate

Command

Bank A

t

RCD

t

RRD

Command

CAa

Read Bank A

Activate

Command

RBa

Bank B

t

AC3

QAa0

CBa CBb

QAa1

QAa2

Read

Command

Bank B

QBa0

QAa3

Read

Command

Bank B

CBc

QBa1 QAb3

Read

Command

Bank B

CAb

QBb0 QAb0

QBc0

QBb1

Read

Command

Bank A

QBc1

Precharge

Command

Bank B

QAb2

QAb1

Precharge Command

Bank A

Document:1G5-0189 Rev.1 Page 52

VG3617161ET

VIS

Interleaved Column Write Cycle (1 of 2)

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

1,048,576 x 16 - Bit

CMOS Synchronous Dynamic RAM

Burst Length=4, CAS Latency=2

CLK

CKE

CS

RAS

CAS

WE

A11(BS)

t

CK2

A10

A0~A9

RAa

t

RCD

CAa

RBa

CBa CBb

CBc

CAb

CBd

t

RP

DPL

DQM

t

RRD

DQ

Hi-Z

Activate

Command

Bank A

DAa0 DAa1

Write

Command

Bank A

DAa3

DAa2

Activate

Command

Bank B

DBa0

Write

Command

Bank B

DBb0 DAb0

DBa1 DBd1

Write

Command

Bank B

DBb1

DBc0

Write

Command

Bank B

DBc1

Command

Bank A

Write

DAb1

DBd0

Precharge

Command

Bank A

Write

Command

Bank B

DBd2 DBd3

Precharge Command

Bank B

Document:1G5-0189 Rev.1 Page 53

VG3617161ET

VIS

Interleaved Column Write Cycle (2 of 2)

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

1,048,576 x 16 - Bit

CMOS Synchronous Dynamic RAM

Burst Length=4, CAS Latency=3

CLK

CKE

CS

RAS

CAS

WE

A11(BS)

t

CK3

A10

A0~A9

RAa

t

RCD

CAa

RBa

CBa CBb

CBc

CAb

t

DPL

CBd

t

DPL

DQM

DQ

Hi-Z

Activate

Command

Bank A

t

RRD

DAa0 DAa1

Write

Command

Bank A

Activate

Command

Bank B

DAa2

DAa3

Command

DBa0

Write

Bank B

DBa1

DBb0 DAb0

Write

Command

Bank B

DBc0

DBb1 DAd0

Write

Command

Bank B

DBc1

Command

Write

Bank A

DAb1

Write

Command

Bank B

Precharge Command

Bank A

QAd1

t

RP

QAd2 QAd3

Precharge Command

Bank B

Document:1G5-0189 Rev.1 Page 54

VG3617161ET

VIS

Auto Precharge after Read Burst (1 of 2)

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

1,048,576 x 16 - Bit

CMOS Synchronous Dynamic RAM

Burst Length=4, CAS Latency=2

CLK

CKE

CS

RAS

CAS

WE

A11(BS)

High

t

CK2

Start Auto Precharge Bank B

Start Auto Precharge Bank A

Start Auto Precharge Bank B

A10

A0~A9

RAa

CAa

RBa

CBa CAb

RBb RAc

RBb

CBb

RAc

CAc

DQM

DQ

Hi-Z

Activate

Command

Bank A

Read

Command

Bank A

QAa0

Activate

Command

Bank B

QAa1

QAa2

Read with

Auto Precharge

Command

Bank A

QAa3

QBa0

QBa2 QAb2

QBa1 QBb1

Read with

Auto Precharge

Command

Bank A

QBa3

QAb0

QAb1

Activate

Command

Bank B

QAb3

Read with

Auto Precharge

Command

Bank B

QBb0

Activate

Command

Bank A

Auto Precharge

QBb2 QBb3

Read with

Command

Bank A

QAc1

QAc0 QAc2

Document:1G5-0189 Rev.1 Page 55

VG3617161ET

VIS

Auto Precharge after Read Burst (2 of 2)

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

1,048,576 x 16 - Bit

CMOS Synchronous Dynamic RAM

Burst Length=4, CAS Latency=3

CLK

CKE

CS

RAS

CAS

WE

A11(BS)

High

t

CK3

Start Auto Precharge Bank B

Start Auto Precharge

Bank A

Start Auto Precharge Bank B

A10

A0~A9

RAa

RBa

CBa

CAb

RBb

CBbCAa

DQM

DQ

Hi-Z

Activate

Command

Bank A

Read

Command

Bank A

Activate

Command

Bank B

QAa0 QAa1

Read with Auto Precharge Command

Bank B

QAa2

QAa3

QBa0

QBa1

QBa2 QAb2

Read with

Auto Precharge

Command

Bank A

Activate Command

QAb0

QBa3 QBb0

Bank B

QAb1

Read with

Auto Precharge

Command

Bank B

QAb3

QBb1

QBb2 QBb3

Document:1G5-0189 Rev.1 Page 56

VG3617161ET

VIS

Auto Precharge after Write Burst (1 of 2)

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

1,048,576 x 16 - Bit

CMOS Synchronous Dynamic RAM

Burst Length=4, CAS Latency=2

CLK

CKE

CS

RAS

CAS

WE

A11(BS)

High

t

CK2

Start Auto Precharge

Bank B

Start Auto Precharge Bank A

Start Auto Precharge Bank B

A10

A0~A9

RAa

RBa

CBa

CAb

RBb

CBbCAa

RAc

RAc CAc

DQM

DQ

Hi-Z

Activate

Command

Bank A

DAa0

Write

Command

Bank A

DAa1

DAa2

Activate

Command

Bank B

DBa0

DAa3

Write with

Auto Precharge

Command

Bank B

DBa2 DAb2

DBa1 DBb1

DAb0

Write with Command

Bank A

DAb1

DBa3

Auto Precharge

DAb3

Activate

Command

Bank B

Auto Precharge

DBb0

Write with

Command

Bank B

DBb2 DBb3

Activate

Command

Bank A

DAc0 DAc1 DAc2 DAc3

Write with

Auto Precharge

Bank A

Start Auto

Precharge

Document:1G5-0189 Rev.1 Page 57

Bank A

VG3617161ET

VIS

Auto Precharge after Write Burst (2 of 2)

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

1,048,576 x 16 - Bit

CMOS Synchronous Dynamic RAM

Burst Length=4, CAS Latency=3

CLK

CKE

CS

RAS

CAS

WE

A11(BS)

High

t

CK3

Start Auto Precharge Bank B

Start Auto Precharge Bank A

Start Auto Precharge Bank B

A10

A0~A9

RAa

CAa

RBa

CBa

CAb

RBb

CBb

DQM

DQ

Hi-Z

Activate

Command

Bank A

DAa0 DAa1

Activate

Command

Bank B

Write

Command

Bank A

DAa2

DBa0

DAa3

Write with

Auto Precharge

Command

Bank B

DBa1

DBa2 DAb2

DAb0

DBa3

Write with

Auto Precharge

Command

Bank A

DAb1

DAb3

Command

Activate

Bank B

DBb1

DBb0

Write with

Auto precharge

Command

Bank B

DBb2

DBb3

Document:1G5-0189 Rev.1 Page 58

VG3617161ET

VIS

Full Page Read Cycle (1 of 2)

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

1,048,576 x 16 - Bit

CMOS Synchronous Dynamic RAM

Burst Length=Full Page, CAS Latency=2

CLK

CKE

CS

RAS

CAS

WE

A11(BS)

High

t

CK2

A10

A0~A9

DQM

DQ

RAa

Hi-Z

Activate

Command

Bank A

CAa

Read

Command

Bank A

RBa

QAa

Activate

Command

Bank B

QAa+1

QAa+2

The burst counter wraps from the highest order page address back to zero during this time interval

QAa-2

QAa-1

CBa

QAa

Read

Command

Bank B

QAa+1

QBa QBa+1

Full page burst operation does not terminate when the burst length is satisfied; the burst counter increases and continues bursting beginning with the starting address

QBa+2

QBa+3

QBa+4

QBa+51

Precharge Command Bank B

Burst Stop Command

QBa+6

t

RP

RBb

Activate

Command

Bank B

Document:1G5-0189 Rev.1 Page 59

VG3617161ET

VIS

Full Page Read Cycle (2 of 2)

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

1,048,576 x 16 - Bit

CMOS Synchronous Dynamic RAM

Burst Length=Full Page, CAS Latency=3

CLK

CKE

CS

RAS

CAS

WE

A11(BS)

High

t

CK3

A10

A0~A9

DQM

DQ

RAa

Hi-Z

Activate

Command

Bank A

CAa

Read

Command

Bank A

RBa

Activate

Command

Bank B

QAa

QAa+2

QAa+1

The burst counter wraps from the highest order page address back to zero during this time interval

QAa-2

Read

Command

Bank B

CBa

QAa+1

QAa

QAa-1

Full page burst operation does not teminate when the burst length is satisfied; the burst counter increases and continues bursting beginning with the starting address

QBa0

QBa+1

QBa+2

QBa+3

Precharge Command Bank B

Burst Stop Command

QBa+4

t

RP

QBa+5

RBb

Activate

Command

Bank B

Document:1G5-0189 Rev.1 Page 60

VG3617161ET

VIS

Full Page Write Cycle (1 of 2)

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

1,048,576 x 16 - Bit

CMOS Synchronous Dynamic RAM

Burst Length=Full Page, CAS Latency=2

CLK

CKE

CS

RAS

CAS

WE

A11(BS)

High

t

CK2

A10

A0~A9

DQM

DQ

RAa

Hi-Z

Activate

Command

Bank A

RBa

CAa RBb

DAa

Write

Command

Bank A

RBa

DAa+1

DAa+2

DAa+3

Activate

Command

Bank B

The burst counter wraps from the highest order page address back to zero during this time interval

DAa-1

DAa

DAa+1

CBa

DBa+1

DBa

Write

Command

Bank B

DBa+2

Full page burst operation does not terminate when the burst length is satisfied; the burst counter increases and continues bursting beginning with the starting address

DBa+3

DBa+4

Data is ignored

DBa+5

DBa+6

t

BDL

Precharge Command Bank B

Burst Stop Command

RBb

Activate

Command

Bank B

Document:1G5-0189 Rev.1 Page 61

VG3617161ET

VIS

Full Page Write Cycle (2 of 2)

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

1,048,576 x 16 - Bit

CMOS Synchronous Dynamic RAM

Burst Length=Full Page, CAS Latency=3

CLK

CKE

CS

RAS

CAS

WE

A11(BS)

High

t

CK3

A10

A0~A9

DQM

DQ

RAa

Hi-Z

Activate

Command

Bank A

CAa

DAa

Write

Command

Bank A

RBa

DAa+1

DAa+2

DAa+3

Activate

Command

Bank B

The burst counter wraps from the highest order page address back to zero during this time interval

DAa-1

DAa

DAa+1

Command

Bank B

CBa

DBa+1

DBa

Write

DBa+2

Full page burst operation does not terminate when the burst length is satisfied; the burst counter increases and continues bursting beginning with the starting address

DBa+3

DBa+4

DBa+5

t

BDL

Burst Stop Command

Data is ignored.

Precharge Command Bank B

RBb

Activate

Command

Bank B

Document:1G5-0189 Rev.1 Page 62

VIS

Byte Write Operation

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

VG3617161ET

1,048,576 x 16 - Bit

CMOS Synchronous Dynamic RAM

Burst Length=4, CAS Latency=2

CLK

CKE

CS

RAS

CAS

WE

A11(BS)

A10

High

RAa

t

CK2

A0~A9

RAa

CAa

CAb

CAz

LDQM

UDQM

DQ0~DQ7

Hi-Z

DQ8~DQ15

Hi-Z

Activate Command

Bank A

Read

Command

Bank A

Upper Byte is masked

Lower Byte is masked

Write

Command

Bank A

Write Upper is masked

Read

Command

Bank A

Lower Byte is masked

Document:1G5-0189 Rev.1 Page 63

VG3617161ET

VIS

Burst Read and Single Write Operation

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

1,048,576 x 16 - Bit

CMOS Synchronous Dynamic RAM

Burst Length=4, CAS Latency=2

CLK

CKE

CS

RAS

CAS

WE

A11(BS)

A10

High

RAa

t

CK2

A0~A9

RAa

CAa

CAb

CAc

CAd

CAe

LDQM

UDQM

DQ0~DQ7

Hi-Z

DQ8~DQ15

Hi-Z

Activate Command

Bank A

Read

Command

Bank A

Single Write Command Bank A

Read

Command

Bank A

Lower Byte is masked

Upper Byte is masked

Single Write Command Bank A

Document:1G5-0189 Rev.1 Page 64

Lower Byte is masked

VG3617161ET

VIS

Full Page Random Column Read

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

1,048,576 x 16 - Bit

CMOS Synchronous Dynamic RAM

Burst Length=Full Page, CAS Latency=2

CLK

CKE

CS

RAS

CAS

WE

A11(BS)

t

CK2

A10

A0~A9

RAa

RBa

RBa CAa CBa

CAb CBb

CBc CAc

RBb

t

RP

DQM

DQ

Hi-Z

Activate

Command

Bank A

Activate

Command

Bank B

Command

Read

Bank A

Read

Command

Bank B

Command

QAa0

Read

Bank A

QBa0

Read

Command

Bank B

QAb0

QAb1

Command

Bank A

QBb0

Read

QBb1 QAc0

QAc1

Read

Command

Bank B

QAc2

QBc1 QBc2

QBc0

Precharge

Command Bank B

(Precharge Termination)

Activate

Command

Bank B

Document:1G5-0189 Rev.1 Page 65

VG3617161ET

VIS

Full Page Random Column Write

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

1,048,576 x 16 - Bit

CMOS Synchronous Dynamic RAM

Burst Length=Full Page, CAS Latency=2

CLK

CKE

CS

RAS

CAS

WE

A11(BS)

t

CK2

A10

A0~A9

RAa

RBa

RBa CAa CBa

CAb CBb

CBc CAc

RBb

t

RP

DQM

DQ

Hi-Z

Activate

Command

Bank A

Activate

Command

Bank B

Command

QAa0

Write

Bank A

QBa0

Write

Command

Bank B

Command

QAb0

Write

Bank A

QAb1

Write

Command

Bank B

QBb0 QBb1

QAc0

Write

Command

Bank A

QAc1

QAc2

Write

Command

Bank B

QBc0

QBc1

QBc2

Precharge

Command Bank B

(Precharge Termination)

Write Data is masked

Command

Activate

Bank B

Document:1G5-0189 Rev.1 Page 66

VG3617161ET

VIS

Precharge Termination of a Burst (1 of 2)

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

1,048,576 x 16 - Bit

CMOS Synchronous Dynamic RAM

Burst Length=4,8 or Full Page, CAS Latency=2

CLK

CKE

CS

RAS

CAS

WE

A11(BS)

High

t

CK2

A10

A0~A9

RAa

CAa

t

DPL

t

RAb

RP

RAc

RAc CAb

t

RP

CAc

t

RP

DQM

DQ

Hi-Z

Activate

Command

Bank A

QAa0

QAa1

Write

Command

Bank A

Precharge Termination

of a Write Burst. Write

data is masked.

QAa2

Da3

Precharge Command Bank A

Activate

Command

Bank A

Read

Command

Bank A

QAb1

QAb0

Precharge

Command

Bank A

Precharge Termination

of a Read Burst.

QAb2

Activate

Command

Bank A

Read

Command

Bank A

QAc0

Precharge Command

QAc1

Bank A

QAc2

Document:1G5-0189 Rev.1 Page 67

VG3617161ET

VIS

Precharge Termination of a Burst (2 of 2)

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

1,048,576 x 16 - Bit

CMOS Synchronous Dynamic RAM

Burst Length=4,8 or Full Page, CAS Latency=3

CLK

CKE

CS

RAS

CAS

WE

A11(BS)

High

t

CK3

A10

A0~A9

DQM

DQ

RAa

Hi-Z

Activate

Command

Bank A

t

RCD

CAa

Write

Command

Bank A

Write Data is masked

t

DPL

DAa1DAa0

Precharge Command Bank A

Precharge Termination

t

RP

Command

Bank A

of a Write Burst.

RAb

Activate

CAb

t

Read

Command

Bank A

RAS

QAb0

Activate

Command

Bank A

QAb1

QAb2

Precharge Termination of a Read Burst.

t

RP

QAb3

Command

RAc

Activate

Bank A

Document:1G5-0189 Rev.1 Page 68

VIS

Ordering information

Part Number Frequency@CL3 Package

VG3617161ET

1,048,576 x 16 - Bit

CMOS Synchronous Dynamic RAM

VG3617161ET-6 VG3617161ET-7 VG3617161ET-8

166MHz 143MHz 125MHz

VG3617161ET- 6

• VG • VIS Memory Product

• 36 • Technology/Design Rule

• 17161 • Device Type/Configuration

• E • Mask/Design Version

• T • Package Type, T: TSOP

• 6 • Cycle time, 6: 6ns, 7: 7ns, 8: 8ns

Packaging Information

• 400mil, 50-Pin Plastic TSOP

MILLIMETERS

DIM

MIN.

A ---

0.05A1

0.95

A2 b 0.30 b1 0.30

0.12c

c1 0.11

20.82D

ZD

e

11.56

E E1 10.03 L 0.40

0.11

R

0.11

R1

NOTE:

1. CONTROLLING DIMENSION : MILLIMETERS

2. DIMENSION D DOES NOT INCLUDE MOLD PROTRUSION. MOLD PROTRUSION SHALL NOT EXCEED 0.15mm(0.006") PER SIDE.

DIMENSION E1 DOES NOT INCLUDE INTERLEAD PROTRUSION.

INTERLEAD PROTRUSION SHALL NOT EXCEED 0.25mm(0.01") PER SIDE.

3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSIONS/INTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD TO BE WIDER THAN THE MAX b DIMENSION BY MORE THAN 0.13mm. DAMBAR INTRUSION SHALL NOT CAUSE THE LEAD TO BE NARROWER THAN THE MIN b DIMENSION BY MORE THAN 0.07mm.

MAX.NOM. MIN.

1.20

---

0.15---

1.05

1.00

0.45

---

0.40

---

0.21

---

0.16

---

21.08

20.95

0.875 REF.

0.80 BASIC

11.9611.76 0.455

10.29

10.16

0.60

0.50

---

--- 0.004 ---

---

0.002

0.037

0.012

0.005

0.0045

0.820

0.0344 REF.

0.0315 BASIC

0.395

0.016

INCHES

NOM.

---

0.039

---

0.825

0.400

0.020

---

MAX.

0.047

0.006

0.041

0.018

0.016

0.008

0.006

0.830

0.4710.463

0.405

0.024

0.0100.0040.25

50

1 25

ZD

400mil 50-Pin

Plastic TSOPII

26

D

48- eb

0.100(0.004)

E1

A2

A1

DETAIL A

b

b1

A

SEATING PLANE

RAD R1

L

SECTION B-B

c1

BASE METAL

WITH PLATING

DETAIL A

E

RAD R

c

B

0°~5°

c

Document:1G5-0189 Rev.1 Page 69