Page 1
VG36128401A
0.3V
±
Preliminary VG36128801A
VG36128161A
VIS
Description
The device is CMOS Synchronous Dynamic RAM organized as 8,388,608 - word x 4 -bit x 4 - bank,
4,194,304 - word x 8 - bit x 4 - bank, or 2,097,152 - word x 16 - bit x 4 - bank. These various organizations
provide wide choice for different applications. It is designed with the state-of-the-art technology to meet standard PC100 or high speed PC133 requirement. Four internal independent banks greatly increase the performance efficiency. It is packaged in JEDEC standard pinout and standard plastic 54-pin TSOP package.
Features
• Single 3.3V () power supply
• High speed clock cycle time : 7.5ns/10ns
• Fully synchronous with all signals referenced to a positive clock edge
• Programmable CAS Iatency (2,3)
• Programmable burst length (1,2,4,8,& Full page)
• Programmable wrap sequence (Sequential/Interleave)
• Automatic precharge and controlled precharge
• Auto refresh and self refresh modes
• Quad Internal banks controlled by BA0 & BA1 (Bank select)
• Each Bank can be operated simultaneously and independently
• I/O level : LVTTL compatible
• Random column access in every cycle
• x4, x8, x16 organization
• Input/Output controlled by DQM ( LDQM, UDQM )
• 4,096 refresh cycles/64ms
• Burst termination by burst stop and precharge command
• Burst read/single write option
CMOS Synchronous Dynamic RAM
The information shown is subject to change without notice.
Document : 1G5-0154 Rev.1 Page 1
Page 2
VIS
Pin Configuration
VG36128401A
Preliminary VG36128801A
VG36128161A
CMOS Synchronous Dynamic RAM
VG36128401 (X 4)
VG36128801 (X 8)
VG36128161 (X 16)
V
DD
NC
V
DDQ
NC
DQ1
V
SSQ
NC
DQ2
V
DDQ
NC
DQ3
V
SSQ
NC
V
DD
NC
WE
CAS
RAS
CS
BA0
BA1
A
10
A
0
A
1
A
2
A
3
V
DD
V
DD
DQ0
V
DDQ
NC
DQ1
V
SSQ
NC
DQ2
V
DDQ
NC
DQ3
V
SSQ
NC
V
DD
NC
WE
CAS
RAS
CS
BA0
BA1
A
10
A
0
A
1
A
2
A
3
V
DD
V
DD
DQ0
V
DDQ
DQ1
DQ2
V
SSQ
DQ3
DQ4
V
DDQ
DQ5
DQ6
V
SSQ
DQ7
V
DD
LDQM
WE
CAS
RAS
CS
BA0
BA1
A
10
A
0
A
1
A
2
A
3
V
DD
15
16
12
13
14
17
18
19
20
21
22
23
24
25
26
27
1
2
3
4
5
6
7
8
9
10
11
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
V
SS
DQ15
V
SSQ
DQ14
DQ13
V
DDQ
DQ12
DQ11
V
SSQ
DQ10
DQ9
V
DDQ
DQ8
V
SS
NC
UDQM
CLK
CKE
NC
A
11
A
9
A
8
A
7
A
6
A
5
A
4
V
SS
V
SS
DQ7
V
SSQ
NC
DQ6
V
DDQ
NC
DQ5
V
SSQ
NC
DQ4
V
DDQ
NC
V
SS
NC
DQM
CLK
CKE
NC
A
11
A
9
A
8
A
7
A
6
A
5
A
4
V
SS
V
SS
DQ7
V
SSQ
NC
DQ6
V
DDQ
NC
DQ5
V
SSQ
NC
DQ4
V
DDQ
NC
V
SS
NC
DQM
CLK
CKE
NC
A
11
A
9
A
8
A
7
A
6
A
5
A
4
V
SS
Pin Description
VG36128801/VG36128161
Pin Name Function Pin Name Function
A0 - A
11
BAO, BA1
Address inputs
Bank select
DQM,
LDQM,
Upper DQ Mask enable,
Lower DQ Mask enable
UDQM,
DQ0 ~ DQ
15
Data - in/data - out CLK Clock input
RAS Row address strobe CKE Clock enable
CAS Column address strobe CS Chip select
WE Write enable V
V
SS
V
DD
Ground V
Power (+ 3.3V)
DDQ
SSQ
Supply voltage for DQ
Ground for DQ
Document : 1G5-0154 Rev.1 Page 2
Page 3
VIS
Block Diagram
VG36128401A
Preliminary VG36128801A
VG36128161A
CMOS Synchronous Dynamic RAM
CLK
CKE
Address
CS
RAS
CAS
WE
Clock
Generator
Row
Address
Buffer
Mode
Register
Control Logic
Command Decoder
&
Refresh
Counter
Column
Address
Buffer
&
Burst
Counter
Row Decoder
Data Control Circuit
(Bank D)
(Bank C)
Bank B
Bank A
Sense Amplifier
Column Decoder &
Latch Circuit
DQM
DQ
Buffer
Latch Circuit
Input & Output
Document : 1G5-0154 Rev.1 Page 3
Page 4
VG36128401A
<
<
<
Preliminary VG36128801A
VG36128161A
VIS
Absolute Maximum D.C. Ratings
Voltage on any pin relative to Vss VIN, V
Supply voltage relative to Vss VDD, V
Short circuit output current I
Power dissipation P
Operating temperature T
Storage temperature T
Caution: Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent
damage. The device is not meant to be operated under conditions outside the limits described in the
operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended
periods may affect device reliability.
Maximum A.C. Operating Requirements for LVTTL Compatible
Input High Voltage V
Input Low Voltage V
CMOS Synchronous Dynamic RAM
Parameter Symbol Value Unit
OUT
DDQ
OUT
D
OPT
STG
Parameter Symbol Min Max Unit Notes
IH
IL
2.0 V
-0.3 0.8 V 2
-0.5 to + 4.6 V
-0.5 to + 4.6 V
50 mA
1.0 W
0 to + 70
-55 to + 125
+ 0.3 V 1
DD
¢J
¢J
Note: 1. Overshoot limit: VIH(max)=V
2. Undershoot limit: VIL(min)=V
+2.0V with a pulse with
DDQ
-2.0V with a pulse with and -1.5v with a pulse
SSQ
3ns
3ns
Recommended DC Operating Conditions for LVTTL Compatible
Parameter Symbol Min Typ Max Unit
Supply Voltage V
Input High Voltage, all inputs V
Input Low Voltage, all inputs V
Capacitance
(Ta=25°C, f = 1MHZ)
Parameter Symbol Min Max Unit Notes
Input capacitance (CLK) C
Input capacitance (all input pins except data
pins.)
Data input/output capacitance C
Notes : 1. Capacitance measured with effective capacitance measuring method.
DD, VDDQ
IH
IL
11
C
12
I/O
3.0 3.3 3.6 V
2.0
-0.3
2.5 4 pF 1
2.5 5 pF 1
4.0 6.5 pF 1
¡Ð
¡Ð
5ns
V
+ 0.3 V
DD
0.8 V
Document : 1G5-0154 Rev.1 Page 4
Page 5
VG36128401A
≥
≤
≤∞≥≥≥∞≤≤≤∞≥
≥
≥
∞
≤
≥
≤
≥
≤
≥
≤
Preliminary VG36128801A
VG36128161A
VIS
DC Characteristics (Recommended Operating Conditions unless otherwise noted)
Parameter Symbol Test Conditions
Operating current
Precharge standby
current in Power
down mode
Precharge standby
current in Nonpower
down mode
Active standby current
in Power
down mode
Active standby
current in Nonpower
down mode
Operating current
(Burst mode)
Refresh current I
Self refresh Current I
Input Ieakage current
(Inputs)
Intput leakage current
(I/O pins)
Output Low Voltage V
Output High Voltage V
CMOS Synchronous Dynamic RAM
-75 -8H Unit Notes
Min Max Min Max
I
CC1
I
CC2P
I
CC2PS
I
CC2N
I
CC2NS
I
CC3P
I
CC3PS
I
CC3N
I
CC3NS
I
CC4
CC5
CC6
Burst length = 1
One bank active
tRCt
RC(MIN.)
CKE V
CKE V
CKE V
CS V
, Io = 0mA
IL(MAX.) tCK
IL(MAX.) tCK
IH(MIN.) tCK
IH(MIN.)
Input signals are changed one
time during 2 CLK cycles.
CKE V
CLK V
IH(MIN.) tCK
IL(MAX.)
Input signals are stable.
CKE V
CKE V
CKE V
CS V
IL(MAX.) tCK
IL(MAX.) tCK
IH(MIN.) tCK
IH(MIN.)
Input signals are changed one
time during 2CLKs
CKE V
CLK V
IH(MIN.) tCK
IL(MAX.)
Input signals are stable.
t
CKtCK(MIN.)
Io = 0mA
All banks Active
tRC = 4 x t
RC(MIN)
CKE 0.2V
l
LI
VIN0, V
INVDD(MAX.)
Pins not under test = 0V
l
LO
V
DQ# in H - Z., Dout Disabled
OLIOL
OHIOH
0, V
OUT
OUTVDD(MAX.)
= 2mA 0.4 0.4 V 4
= -2mA 2.4 2.4 V 4
x4 120 100 mA 1
x 8 125 105
x16 135 115
= min.
=
= min.
=
= min.
=
= min.
=
x4 115 105
x 8 130 120 mA 2
x16 160 150
-1 1 -1 1 uA
-1.5 1.5 -1.5 1.5 uA
2 2 mA
2 2
20 20 mA
7 7
7 7 mA
5 5
30 30 mA
20 20
190 190 mA 3
1 1 mA
Notes : 1. I
Document : 1G5-0154 Rev.1 Page 5
depends on output loading and cycle rates. Specified values are obtained with the output open.
CC1
In addition to this, I
2. I
depends on output loading and cycle rates. Specified values are obtained with the output open.
CC4
In addition to this, I
3. I
is measured on condition that addresses are changed only one time during t
CC5
4. For LVTTL compatible.
is measured on condition that addresses are changed only one time during t
CC1
is measured on condition that addresses are changed only one time during t
CC4
CK(MIN.)
.
CK(MIN.)
.
CK(MIN.)
.
Page 6
VIS
±
VG36128401A
Preliminary VG36128801A
VG36128161A
CMOS Synchronous Dynamic RAM
AC Characteristics : (Ta = 0 to 70°C V
Test Conditions for LVTTL Compatible :
AC input Levels (VIH/VIL) 2.0/0.8V Input timing reference level/
Input rise and fall time 1ns Output load condition 50pF
AC Test Load Circuits (for LVTTL interface) :
V
DDQ
Device
Under
Test
V
V
DDQ
OUT
= 3.3V 0.3V ,V
DD
Z = 50
= 0V)
SS
Output timing reference level
Ω
1.4V
50PF
Document : 1G5-0154 Rev.1 Page 6
Page 7
VG36128401A
±
Preliminary VG36128801A
VG36128161A
VIS
AC Characteristics : (Ta = 0 to 70°C VDD = 3.3V0.3V, VSS = 0V)
symbol A.C. Parameter -75 -8H
t
RC
t
RCD
t
RP
t
RRD
t
RAS
t
CK2
t
CK3
t
CH
t
CL
t
AC2
t
AC3
t
T
t
CCD
t
OH
t
LZ
t
HZ2
t
HZ3
t
IS
t
IH
t
SRX
t
PDE
t
RSC
t
DPL
t
DAL2
t
DAL3
t
BDL
t
REF
Row cycle time 60 70
RAS to CAS delay 20 20
Precharge to refresh/row activate command 15 20
Row activate to row activate delay 15 20
Row activate to precharge time 37.5 100,000 50 100,000
Clock cycle time
Clock high time 2.25 3
Clock low time 2.25 3
Access time from CLK
(positive edge)
Transition time of CLK (Rise and Fall) 1 10 1 10
CAS to CAS Delay time 1 1 CLK
Data output hold time 2.5 3
Data output low impedance 0 0
Data output high impedance
Data/Address/Control Input setup time 1 2
Data/Address/Control Input hold time 0.5 1
Minimum CKE ”High”for Self-Refresh exit 1 1 CLK
Power Down Exit set-up time 2 2 ns
Mode Register Set Cycle 2 2 CLK
Data-in to precharge 2 1 CLK
Data-in to ACT (REF) Command CL2 2clk+t
Last data in to burst stop 1 1 CLK
Refresh time 64 64 ms
CMOS Synchronous Dynamic RAM
Min. Max. Min. Max.
CL2 7.5 10
CL3 7.5 10
CL2 5 6
CL3 5 6
CL2 4 6
CL3 4 6
RP
CL3 2clk+t
RP
1clk+t
1clk+t
RP
RP
unit note
ns
ns
ns
ns
9
Document : 1G5-0154 Rev.1 Page 7
Page 8
VG36128401A
Preliminary VG36128801A
VG36128161A
VIS
Basic Features and Function Description
1.Simplified State Diagram
CMOS Synchronous Dynamic RAM
Mode
Register
Set
MRS
IDLE
Self
Refresh
y
r
t
n
e
F
L
t
E
S
ACT
i
x
e
F
L
E
S
C
K
REF
C
K
E
E
AUTO
Refresh
WRITE
SUSPEND
WRITEA
SUSPEND
Write (Write recovery)
CKE
CKE
Auto Precharge
CKE
Write with
CKE
WRITE
WRITEA
Power
Down
B
S
T
READ
READA
Active
Power
Down
Read
CKE
CKE
Read with
Auto Precharge
CKE
CKE
READ
SUSPEND
READA
SUSPEND
ROW
ACTIVE
T
S
B
e
t
i
r
W
r
e
t
i
r
W
Read (write recovery)
A
u
P
R
E
(
P
h
e
t
i
g
r
w
y
a
r
h
e
e
t
v
i
o
r
c
e
W
o
t
u
A
R
e
a
d
w
t
o
P
r
e
c
h
r
e
c
h
a
r
g
e
t
e
r
m
i
n
a
PRE
c
e
r
p
Write
i
t
h
a
r
g
e
A
(
w
r
i
t
t
i
o
n
)
CKE
CKE
R
A
R
u
t
o
P
r
a
e
R
o
t
u
e
r
e
c
r
P
(
E
R
P
e
a
e
a
d
e
c
h
a
d
P
o
v
a
h
c
e
d
w
i
t
h
r
g
e
h
t
e
i
g
w
r
a
h
c
e
r
e
r
y
)
)
n
o
i
t
a
n
i
m
r
e
t
e
g
r
POWER
ON
Precharge
Precharge
Automatic sequence
Manual input
Note: After the AUTO refresh operation, precharge operation is
performed automatically and enter the IDLE state.
Document : 1G5-0154 Rev.1 Page 8
Page 9
VG36128401A
Preliminary VG36128801A
VG36128161A
VIS
2. Truth Table
2.1 Command Truth Table
FUNCTION Symbol
Device deselect DESL H X H X X X X X X
No operation NOP H X L H H H X X X
Mode register set MRS H X L L L L L L V
Bank activate ACT H X L L H H V V V
Read READ H X L H L H V L V
Read with auto precharge READA H X L H L H V H V
Write WRIT H X L H L L V L V
Write with auto precharge WRITA H X L H L L V H V
Precharge select bank PRE H X L L H L V L X
Precharge all banks PALL H X L L H L X H X
Burst stop BST H X L H H L X X X
CBR (Auto) refresh REF H H L L L H X X X
Self refresh SELF H L L L L H X X X
CMOS Synchronous Dynamic RAM
CKE
n -1 n
CS RAS CAS WE BA
(1)
A10
A11
A9 - A0
2.2 DQM Truth Table
CKE DQM
FUNCTION Symbol
Data write/output enable ENB H X L
Data mask/output disable MASK H X H
Upper byte write enable/output enable ENBU H X L X
Lower byte write enable/output enable ENBL H X X L
Upper byte write inhibit/output disable MASKU H X H X
Lower byte write inhibit/output disable MASKL H X X H
2.3 CKE Truth Table
Current State Function Symbol
Activating Clock suspend mode entry H L X X X X X
Any Clock suspend L L X X X X X
Clock suspend Clock suspend mode exit L H X X X X X
Idle CBR refresh command REF H H L L L H X
Idle Self refresh entry SELF H L L L L H X
Self refresh Self refresh exit L H L H H H X
Idle Power down entry H L X X X X X
Power down Power down exit L H X X X X X
n -1 n -1 U L
CKE
CS RAS CAS WE
L H H X X X X
Add -
ressn - 1 n
H : High level, L : Low level
X : High or Low level (Don’t care), V : Valid Data input
Document : 1G5-0154 Rev.1 Page 9
Page 10
VG36128401A
→→→
→→→
Preliminary VG36128801A
VG36128161A
VIS
2.4 Operative Command Table Notes 1
Current
state
Idle H X X X X DESL Nop or Power down 2
Row active H X X X X DESL Nop
Read H X X X X DESL
Write H X X X X DESL
CMOS Synchronous Dynamic RAM
(1/3)
CS RAS CAS WE Address Command Action Notes
L H H X X NOP or BST Nop or Power down 2
L H L H BA, CA, A10 READ/READA ILLEGAL 3
L H L L BA, CA, A10 WRIT/WRITA ILLEGAL 3
L L H H BR, RA ACT Row active
L L H L BA, A10 PRE/PALL Nop
L L L H X REF/SELF Refresh or Self refresh 4
L L L L Op - Code MPS Mode register access
L H H X X NOP or BST Nop
L H L H BA, CA, A10 READ/READA Begin read : Determine AP 5
L H L L BA, CA, A10 WRIT/WRITA Begin write : Determine AP 5
L L H H BA, RA ACT ILLEGAL 3
L L H L BA, A10 PRE/PALL Precharge 6
L L L H X REF/SELF ILLEGAL
L L L L Op - Code MRS ILLEGAL
Continue burst to end Row active
L H H H X NOP
L H H L X BST
L H L H BA, CA, A10 READ/READA Term burst, new read : Determine AP 7
L H L L BA, CA, A10 WRIT/WRITA Term burst, start write : Determine AP 7,8
L L H H BA, RA ACT ILLEGAL 3
L L H L BA, A10 PRE/PALL Term burst, precharging
L L L H X REF/SELF ILLEGAL
L L L L Op - Code MRS ILLEGAL
L H H H X NOP
L H H L X BST
L H L H BA, CA, A10 READ/READA Term burst, start read : determine AP 7,8
L H L L BA, CA, A10 WRIT/WRITA Term burst, new write : Determine AP 7
L L H H BA, RA ACT ILLEGAL 3
L L H L BA, A10 PRE/PALL Term burst, precharging 9
L L L H X REF/SELF ILLEGAL
L L L L Op - Code MRS ILLEGAL
Continue burst to end Row active
Burst end Row active
Continue burst to end Write recovering
Continue burst to end Write recovering
Burst stop Row active
Document : 1G5-0154 Rev.1 Page 10
Page 11
VG36128401A
→
→→→
→→→
→→→
→
Preliminary VG36128801A
VG36128161A
VIS
Current state CS RAS CA WE Address Command Action Notes
Read with auto
precharge
Write with auto
precharge
precharging H X X X X DESL
Row activating H X X X X DESL
CMOS Synchronous Dynamic RAM
H X X X X DESL
L H H H X NOP
L H H L X BST Illegal for single bank, but legal for
L H L H BA, CA, A10 READ/READA Illegal for single bank, but legal for
L H L L BA, CA, A10 WRIT/WRITA ILLEGAL
L L H H BA, RA ACT ILLEGAL 3
L L H L BA, A10 PRE/PALL ILLEGAL 3
L L L H X PEF/SELF ILLEGAL
L L L L Op - Code MRS ILLEGAL
H X X X X DESL
L H H H X NOP
L H H L X BST ILLEGAL
L H L H BA, CA, A10 READ/READA Illegal for single bank, but legal for
L H L L BA, CA, A10 WRIT/WRITA Illegal for single bank, but legal for
L L H H BA, RA ACT ILLEGAL 3
L L H L BA, A10 PRE/PALL ILLEGAL 3
L L L H X PEF/SELF ILLEGAL
L L L L Op - Code MRS ILLEGAL
L H H H X NOP
L H H L X BST
L H L H BA, CA, A10 READ/READA ILLEGAL 3
L H L L BA, CA, A10 WRIT/WRITA ILLEGAL 3
L L H H BA, RA ACT ILLEGAL 3
L L H L BA, A10 PRE/PALL
L L L H X PEF/SELF ILLEGAL
L L L L Op - Code MRS ILLEGAL
L H H H X NOP
L H H L X BST
L H L H BA, CA, A10 READ/READA ILLEGAL 3
L H L L BA, CA, A10 WRIT/WRITA ILLEGAL 3
L L H H BA, RA ACT ILLEGAL 3,9
L L H L BA, A10 PRE/PALL ILLEGAL 3
L L L H X PEF/SELF ILLEGAL
L L L L Op - Code MRS ILLEGAL
Continue burst to end Prcharging
Continue burst to end Prcharging
multibanks interleave
multibanks interleave
Continue burst to endWrite
recovering with auto precharge
Continue burst to endWrite
recovering with auto precharge
multibanks interleave
multibanks interleave
NopEnter idle after t
NopEnter idle after t
NopEnter idle after t
NopEnter idle after t
NopEnter row active idle after t
NopEnter row active idle after t
NopEnter row active idle after t
RP
RP
RP
RP
RCD
RCD
RCD
(2/3)
Document : 1G5-0154 Rev.1 Page 11
Page 12
VG36128401A
→→→
→→→→→
Preliminary VG36128801A
VG36128161A
VIS
Current state CS RAS CA WE Address Command Action Notes
CMOS Synchronous Dynamic RAM
(3/3)
Write
recovering
Write
recovering
with auto
precharge
Auto
Refreshing
Mode register setting
H X X X X DESL
L H H H X NOP
L H H L X BST
L H L H BA, CA, A10 READ/READA Start read, Determine AP 8
L H L L BA, CA, A10 WRIT/WRITA New write, Determine AP
L L H H BA, RA ACT ILLEGAL 3
L L H L BA, A10 PRE/PALL ILLEGAL 3
L L L H X PEF/SELF ILLEGAL
L L L L Op - Code MRS ILLEGAL
H X X X X DESL
L H H H X NOP
L H H L X BST
L H L H BA, CA, A10 READ/READA ILLEGAL 3,8
L H L L BA, CA, A10 WRIT/WRITA ILLEGAL 3
L L H H BA, RA ACT ILLEGAL 3
L L H L BA, A10 REF/PALL ILLEGAL 3
L L L H X REF/SELF ILLEGAL
L L L L Op - Code MRS ILLEGAL
H X X X X DESL Nop Enter idle after t
L H H X X NOP/BST Nop Enter idle after t
L H L X X READ/WRIT ILLEGAL
L L H X X ACT/PRE/PALL ILLEGAL
L L L X X REF/SELF/MRS ILLEGAL
H X X X X DESL
L H H H X NOP
L H H L X BST ILLEGAL
L H L X X READ/WRITE ILLEGAL
L L X X X ACT/PRE/
PALL/
Nop Enter row active after t
Nop Enter row active after t
Nop Enter row active after t
Nop Enter precharge after t
Nop Enter precharge after t
Nop Enter precharge after t
RC
RC
Nop Enter idle after 2 Clocks
Nop Enter idle after 2 Clocks
ILLEGAL
DPL
DPL
DPL
DPL
DPL
DPL
Note 1. All entries assume that CKE was active (High level) during the preceding clock cycle.
2. If both banks are idle, and CKE is inactive (Low level), the device will enter Power down mode.
All input buffers except CKE will be disabled.
3. Illegal to bank in specified states; Function may be legal in the bank indicated by Bank Address (BA),
depending on the state of that bank.
4. If both banks are idle, and CKE is inactive (Low level), the device will enter Self refresh mode.
All input buffers except CKE will be disabled.
5. Illegal if t
6. Illegal if t
7. Must satisfy burst interrupt condition.
8. Must satisfy bus contention, bus turn around, and/or write recovery requirements.
9. Must mask preceding data which don’t satisfy t
10. Illegal if t
11. Illegal for single bank, but for multibanks interleave
Document : 1G5-0154 Rev.1 Page 12
is not satisfied.
RCD
is not satisfied.
RAS
is not satisfied.
RRD
DPL
.
Page 13
VIS
→
VG36128401A
Preliminary VG36128801A
VG36128161A
CMOS Synchronous Dynamic RAM
2.5 Command Truth Table for CKE
CKE
Current state
Self refresh
(S.R.)
Self refresh
recovery
Power down
(P.D.)
Both banks idle
Any state other
than listed above
Note 1. H : Hight level, L : low level, X : High or low level (Don't care)
2. CKE Low to High transition will re-enable CLK and other inputs asynchronously. A minimum setup time
must be satisfied before any command other than EXIT.
3. Power down and Self refresh can be entered only from the both banks idle state.
4. Must be legal command as defined in Operative Command Table.
5. IIIegal if t
SREX
RASnCS RAS
n - 1
H X X X
L H H X
L H L H
L H L H
L H L L
L L X X
H H H X
H H L H
H H L H
H H L L
H L H X
H L L H
H L L H
H L L L
L H X X
L L X X
H X X X
L H X X
L L X X
H H H X
H H L H
H H L L
H H L L
H H L L
H L H X
H L L H
H L L L
H L L L
H L L L
L X X X
H H X X
H L X X
L H X X
L L X X
is not satisfied.
Note 1
CAS WE Address Action Notes
X X X INVALID, CLK (n-1)would exit S.R.
X X X S.R. Recovery 2
H X X S.R. Recovery 2
L X X ILLEGAL
X X X ILLEGAL
X X X Maintain S.R.
X X X Idle after t
H X X Idle after t
L X X ILLEGAL
X X X ILLEGAL
X X X Begin clock suspend next cycle 5
H X X Begin clock suspend next cycle 5
L X X ILLEGAL
X X X ILLEGAL
X X X Exit clock suspend next cycle 2
X X X Maintain clock suspend
X X INVALID, CLK(n-1) would exit P.D.
X X X
X X X Maintain power down mode
X X Refer to operations in Operative
X X Refer to operations in Operative
H X Refer to operations in Operative
L H X Auto Refresh
L L Op-Code Refer to operations in Operative
X X Refer to operations in Operative
X X Refer to operations in Operative
H X Refer to operations in Operative
L H X Self refresh 3
L L Op-Code Refer to operations in Operative
X X X Power down 3
X X X Refer to operations in Operative
X X X Begin clock suspend next cycle 4
X X X Exit clock suspend next cycle
X X X Maintain clock suspend
EXIT P.D. Idle
Command Table
Command Table
Command Table
Command Table
Command Table
Command Table
Command Table
Command Table
Command Table
RC
RC
2
Document : 1G5-0154 Rev.1 Page 13
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VG36128401A
Preliminary VG36128801A
VG36128161A
VIS
5.Mode Register (Address Input for Mode Set)
CMOS Synchronous Dynamic RAM
13
12
0 Reserved
0
13
12
x
x
13
12
x
x
10
11
0 0
11 10
x
x
11
10
x x 0
9 8
0 0
9
1
9
8
0
8
0 0
7
1
7 6
0
7 6
6
5
5
LTMODE
5
LTMODE
3
4
3 2
4
WT
3
4
WT
2 1
2
0
JEDEC Standard Test Set
1
0
BL
1
BL
Burst Read and Single Write (for Write Through Cache)
0
Burst Read and Burst Write X = Don’t care
Burst length
Wrap type
Bits2 - 0
000
001
010
011
100
101
110
111
0
1
WT = 0
1
2
4
8
R
R
R
Full page
Sequential
Interleave
WT = 1
1
2
4
8
R
R
R
R
Latency
mode
Bits6 - 4
000
001
010
011
100
101
110
111
Remark R : Reserved
CAS Iatency
R
R
2
3
R
R
R
R
Document : 1G5-0154 Rev.1 Page 14
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VG36128401A
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VG36128161A
VIS
5.1 Burst Length and Sequence
(Burst of Two)
Starting Address
(column address A0, binary)
(Burst of Four)
Starting Address
(column address A1 - A0, binary)
CMOS Synchronous Dynamic RAM
0 0, 1 0, 1
1 1, 0 1, 0
00 0, 1, 2, 3 0, 1, 2, 3
01 1, 2, 3, 0 1, 0, 3, 2
10 2, 3, 0, 1 2, 3, 0, 1
11 3, 0, 1, 2 3, 2, 1, 0
Sequential Addressing
Sequence (decimal)
Sequential Addressing
Sequence (decimal)
Interleave Addressing Sequence (decimal)
Interleave Addressing Sequence (decimal)
(Burst of Eight)
Starting Address
(column address A2 - A0, binary)
000 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7
001 1, 2, 3, 4, 5, 6, 7, 0 1, 0, 3, 2, 5, 4, 7, 6
010 2, 3, 4, 5, 6, 7, 0, 1 2, 3, 0, 1, 6, 7, 4, 5
011 3, 4, 5, 6, 7, 0, 1 ,2 3, 2, 1, 0, 7, 6, 5, 4
100 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3
101 5, 6 ,7, 0, 1, 2, 3, 4 5, 4, 7, 6, 1, 0, 3, 2
110 6, 7 ,0 ,1 ,2 ,3 ,4 ,5 6, 7, 4, 5, 2, 3, 0, 1
111 7, 0, 1, 2, 3, 4, 5, 6 7, 6, 5, 4, 3, 2, 1, 0
Full page burst is an extension of the above tables of Sequential Addressing, with the length being 2048 /
1024 / 512 for 32M x 4 / 16M x 8 / 8M X16 devices, respectively.
Sequential Addressing
Sequence (decimal)
Interleave Addressing Sequence (decimal)
Document : 1G5-0154 Rev.1 Page 15
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VG36128401A
Preliminary VG36128801A
VG36128161A
VIS
6 Address Bits of Bank-Select and precharge
6.1 Quad banks controlled by A12 & A13
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13
Row
(Activate command)
CMOS Synchronous Dynamic RAM
A12 A13 Result
0 0
0 1
1 0
1 1
Select Bank A
“Activate “ command
Select Bank B
“Activate” command
Select Bank C
“Activate” command
Select Bank D
“Activate” command
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13
Row
(Precharge command)
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13
Col.
(CAS strobes)
A10 A12 A13 Result
0 0 0 Precharge Bank A
0 0 1 Precharge Bank B
0 1 0 Precharge Bank C
0 1 1 Precharge Bank D
1 X X Precharge All Banks
0 Disables Auto - Precharge (End of Burst)
1 Enables Auto - Precharge (End of Burst)
A12 A13 Result
0 0
0 1
1 0
1 1
Enables Read/Write
commands for Bank A
Enables Read/Write
commands for Bank B
Enables Read/Write
commands for Bank C
Enables Read/Write
commands for Bank D
Document : 1G5-0154 Rev.1 Page 16
Page 17
VIS
7.Precharge
VG36128401A
Preliminary VG36128801A
VG36128161A
CMOS Synchronous Dynamic RAM
The precharge command can be asserted anytime after t
Soon after the precharge command is asserted, the precharge operation is performed and the synchronous DRAM
enters the idle state after t
The earliest timing in a read cycle that a precharge command can be asserted without losing any data in the burst is
as follows.
PrechargeE
CLK
Command
CAS latency = 2
DQ
is satisfied. The parameter tRP is the time required to perform the precharge.
RP(min.)
T0 T1
Read
RAS(min)
T2
Q0
is satisfied.
T3
Q1
T4 T5
PRE
T6
Q3Q2
Burst lengh=4
T7
Hi - Z
Command
CAS latency = 3
DQ
CAS latency = 2 : One clock earlier than the last output data.
3 : Two clocks earlier than the last output data.
In order to write all data to the memory cell correctly, the asynchronous parameter ”t
fied. The t
minimum number of clocks can be calculated by dividing t
last data word is valid. In the following table, minus means clocks before the reference; plus means time
after the reference.
DPL(min.)
In summary, the precharge command can be asserted relative to the reference clock that indicates the
specification defines the earliest time that a precharge command can be asserted. The
CAS latency Read Write
Read
Q0
DPL(min.)
2 -1 + t
3 -2 + t
by the clock cycle time.
DPL(min.)
DPL(min.)
PRE
Q1
Q2
” must be satis-
DPL
(t
Q3
RAS
is satisfied)
Hi - Z
Document : 1G5-0154 Rev.1 Page 17
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VG36128401A
Preliminary VG36128801A
VG36128161A
VIS
8.Auto Precharge
During a read or write command cycle, A10 controls whether auto precharge is selected. If A10 is high
in the read or write command (Read with Auto precharge command or Write with Auto precharge command), auto precharge is selected and begins automatically after the burst access.
In the write cycle, t
being precharged.
When using auto precharge in the read cycle, knowing when the precharge starts is important because
the next activate command to the bank being precharged cannot be executed until the precharge cycle
ends. Once auto precharge has started, an activate command to the bank can be asserted after tRP has
been satisfied.
A Read or Write command without auto - precharge can be terminated in the midst of a burst operation.
However, a Read or Write command with auto - precharge can not be interrupted by the same bank commands before the entire burst operation is completed. Therefore use of the same bank Read, Write, Precharge or Burst Stop command is prohibited during a read or write cycle with auto - precharge. It should be
noted that the device will not respond to the Auto - Precharge command if the device is programmed for full
page burst read or write cycles.
The timing when the auto precharge cycle begins depends both on both the CAS Iatency programmed
into the mode register and whether the cycle is read or write.
CMOS Synchronous Dynamic RAM
DAL(min.)
must be satisfied before asserting the next activate command to the bank
8.1 Read with Auto Precharge
During a READA cycle, the auto precharge begins one clock earlier (CL = 2) or two clocks earlier
(CL = 3) than the last word output.
READ with AUTO PRECHARGE
T0 T1
CLK
Command
CAS latency = 2
DQ
Command
READA B
READA B
QB0
T3
QB1
T2
No New Command to Bank B
No New Command to Bank B
T4
Auto precharge starts
Auto precharge starts
T5
QB3QB2
T6
Burst lengh = 4
T7
Hi - Z
T8
CAS latency = 3
DQ
Remark READA means READ with AUTO PRECHARGE
Document : 1G5-0154 Rev.1 Page 18
QB0
QB1
QB2
QB3
Hi - Z
Page 19
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VG36128161A
VIS
8.2 Write with Auto Precharge
During a write cycle, the auto precharge starts at the timing that is equal to the value of t
after the last data word input to the device.
WRITE with AUTO PRECHRGE
CLK
Command
CAS latency = 2
CMOS Synchronous Dynamic RAM
T0 T1
WRITA B
T2
No New Command to Bank B
T3
T4 T5
AUTO PRECHARGE starts
t
DPL
T6
DPL(min.)
Burst lengh = 4
T7
T8
DQ
Command
CAS latency = 3
DQ
Remark WRITA means WRITE with AUTO Precharge
DB0
WRITA B
DB0
DB1
No New Command to Bank B
DB1
DB2
DB3DB2
AUTO PRECHARGE starts
t
DPL
DB3
In summary, the auto precharge cycle begins relative to a reference clock that indicates the last data
word is valid.
In the table below, minus means clocks before the reference; plus means clocks after the reference.
CAS latency Read Write
2 -1 + t
3 -2 + t
DPL(min.)
DPL(min.)
Hi - Z_
Hi - Z
Document : 1G5-0154 Rev.1 Page 19
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VG36128401A
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VG36128161A
VIS
8.3 Multibank Operation- Read with Auto Precharge
During a READA cycle interrupted by a Read, Write command of another banks, the auto-pre-
charge scheduled time would not be changed.
Multibank Operation
CLK
Command
CAS latency=2
CMOS Synchronous Dynamic RAM
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14
READA A Read B
Burst lengh=8
Auto precharge bank A starts
DQ
Command
CAS latency=3
DQ
READA A
QA0 QA1
Read B
QA0
QB0
QA1
QB0
Similiar top.21
QB2 QB3 QB4 QB5 QB6 QB7 QB1
Auto precharge bank A starts
QB2 QB3 QB4 QB5 QB6 QB7 QB1
Hi-Z
Hi-Z
Document : 1G5-0154 Rev.1 Page 20
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VG36128401A
Preliminary VG36128801A
VG36128161A
VIS
8.4 Multibank Operation- Write with Auto Precharge
During a WRITEA cycle interrupted by a Read, Write command of another banks, the auto-pre-
charge scheduled time would not be changed.
Multibank Operation
CLK
Command
CAS latency=2
CMOS Synchronous Dynamic RAM
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10
WRITA A
Burst lengh=8
Auto precharge bank A starts
Read B
DQ
Command
CAS latency=3
DQ
Multibank Operation
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11
CLK
Command
CAS latency=2
DQ
DA1
DA1
DA1
DB0
DA0
WRITA A
DA0
WRITA A Write B
DA0
Read B
DB1
DB2
DB0
DB3
DB1
DB0
DB4
DB2 DB3
DB1
Auto precharge bank A starts
DB6
DB5
DB4
Auto precharge bank A starts
DB2
DB3
DB7
DB5
DB4
Burst lengh=8
Hi-Z
Hi-Z
Hi-Z
Auto precharge bank A starts
Command
CAS latency=3
DQ
WRITA A Write B
DA0
DA1
DB0
DB1
DB2
DB3
DB4
DB5 DB6 DB7
Document : 1G5-0154 Rev.1 Page 21
Hi-Z
Page 22
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VG36128161A
VIS
9.Read/Write Command Interval
9.1 Read to Read command interval
During a read cycle when a new read command is asserted, it will be effective after the CAS latency,
even if the previous read operation has not completed. READ will be interrupted by another READ.
Each read command can be asserted in every clock without any restriction.
READ to READ Command Interval
CLK
CMOS Synchronous Dynamic RAM
T0 T1
Burst lengh=4, CAS latency=2
T2
T3
T4 T5
T6
T7
T8
1 cycle
Read B
QA0
QB0
QB2QB1
Command
DQ
Read A
9.2 Write to Write Command Interval
During a write cycle, when a new Write command is asserted, the previous burst will terminated and the
new burst will begin with a new write command. WRITE will be interrupted by another WRITE.
Each write command can be asserted in every clock without any restriction.
WRITE to WRITE Command Interval
T0 T1
T2
T3
T4 T5
QB3
Burst lengh=4, CAS latency=2
T6
Hi-Z_
T7
T8
CLK
1 cycle
Write B
QB0
QB2QB1
QB3
Hi-Z_
Command
DQ
Write A
QA0
Document : 1G5-0154 Rev.1 Page 22
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VG36128161A
VIS
9.3 Write to Read Command Interval
The write command to read command interval is also a minimum of 1 cycle. Only the write data before
the read command will be written. The data bus must be Hi-Z at least one cycle prior to the first D
WRITE to READ Command Interval
CLK
CMOS Synchronous Dynamic RAM
T0 T1
1 cycle
.
OUT
Burst lengh=4
T2
T3
T4 T5
T6
T7
T8
Command
CAS latency=2
DQ
Command
CAS latency=3
DQ
WRITE A
DA0
Write A
DA0
Read B
Read B
9.4 Read to Write Command Interval
During a read cycle, READ can be interrupted by WRITE.
DQM must be in High at least 3 clocks prior to the write command. There is a restriction to avoid a data
conflict. The data bus must be Hi-Z using DQM before Write.
Hi-Z
Hi-Z
QB0
QB1
QB0
QB1
QB3QB2
QB2
QB3
Document : 1G5-0154 Rev.1 Page 23
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VG36128401A
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VG36128161A
VIS
READ to WRITE Command Interval
CMOS Synchronous Dynamic RAM
CLK
Command
DQM
DQ
CLK
Command
T0 T1
Hi-Z
T0 T1
Read
Read
1 cycle
T2
D0
Write
CAS latency=2
T7
T8
T8
T9
D1
T3
T4 T5
T4 T5
D3D2
T6
T2
T3
T6
Burst length=8, CAS latency=2
T7
Write
DQM
DQ
CLK
Command
DQM
DQ
Q0
T0 T1
Read
The minimum command interval = (4+1) cycles
T2
Q2
Q2
Hi-Z is
necessary
T4 T5
Hi-Z is
necessary
example: Burst length=4, CAS latency=3
Write
D0
Q1 D0
T3
D1
T6
T7
D1
D2
T8
D2
Document : 1G5-0154 Rev.1 Page 24
Page 25
VIS
10.BURST Termination
There are two methods to terminate a burst operation other than using a read or a write command.
One is the burst stop command and the other is the precharge command.
10.1 BURST Stop Command
During a read burst. when the burst stop command is asserted, the burst read data are terminated and the data bus goes to high-impedance after the CAS latency from the burst stop command.
During a write burst, when the burst stop command is asserted, any data provided at that cycle
will not be written. The burst write is effectively terminated and no further data can be written until a
new write command is asserted.
Burst Termination
VG36128401A
Preliminary VG36128801A
VG36128161A
CMOS Synchronous Dynamic RAM
CLK
Command
CAS latency=2
DQ
CAS latency=3
DQ
Remark BST: Burst stop command
T0 T1
Read
T0 T1
T2
T2
Q0
T3
T3
BST
Q1
Q0
T4 T5
Q2
Q1
T4 T5
Burst lengh=X, CAS Intency=2,3
T6
Hi-Z
Q2
Burst lengh=X, CAS latency=2,3
T6
T7
Hi-Z
T7
CLK
Command
CAS latency=2,3
DQ
Write
Q0
Q0
Q1
Q2
BST
Hi-Z_
Remark BST: Burst command
Document : 1G5-0154 Rev.1 Page 25
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VG36128401A
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VG36128161A
VIS
10.2 PRECHARGE TERMINATION
10.2.1 PRECHARGE TERMINATION in READ Cycle
precharge command is asserted, the burst read operation is terminated and precharge starts.
mand.
mand.
Precharge Termination in READ Cycle
CMOS Synchronous Dynamic RAM
During READ cycle, the burst read operation is terminated by a precharge command. When the
The same bank can be activated again after tRP from the precharge command.
When CAS latency is 2,the read data will remain valid until one clock after the precharge com-
When CAS latency is 3, the read data will remain valid until two clocks after the precharge com-
CLK
Command
CAS latency=2
DQ
command
CAS latency=3
DQ
T0 T1
Read
Read
T2
T3
Q0 Q3
T4 T5
PRE ACT
Q1
Q0 Q3
Q2
PRE ACT
Q1
T6
t
RP
t
RP
Q2
T7
Hi-Z
Burst lengh= X
T8
Hi-Z
Document : 1G5-0154 Rev.1 Page 26
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VG36128161A
VIS
10.2.2 Precharge Termination in WRITE Cycle
PRECHARGE TERMINATION in WRITE Cycle
CMOS Synchronous Dynamic RAM
During WRITE cycle, the burst write operation is terminated by a precharge command. When the precharge command is asserted, the burst write operation is terminated and precharge starts.
The same bank can be activated again after tRP from the precharge command. The
DQM must be high to mask invalid data in.
During WRITE cycle, the write data written prior to the precharge command will be
correctly stored. However, invalid data may be written at the same clock as the precharge command. To prevent this from happening, DQM must be high at the same
clock as the precharge command. This will mask the invalid data.
CLK
Command
CAS latency = 2
DQM
DQ
command
CAS latency = 3
DQM
DQ
T0 T1
Write
D0 D3
Write
D0 D3
D1
D1
T2
D2
D2
T3
T4 T5
PRE ACT
D4
PRE ACT
D4
T6
Hi - Z
t
RP
Hi - Z
t
RP
Burst lengh = X
T7
T8
Document : 1G5-0154 Rev.1 Page 27
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VIS
,
VG36128401A
Preliminary VG36128801A
VG36128161A
CMOS Synchronous Dynamic RAM
Timing Diagram
Document : 1G5-0154 Rev.1 Page 28
Page 29
VIS
Mode Register Set
CLK
CKE
CS
VG36128401A
Preliminary VG36128801A
VG36128161A
CMOS Synchronous Dynamic RAM
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10
t
RSC
RAS
CAS
WE
BS
A10
ADD
DQM
DQ
Hi-Z
t
RP
Address Key
Precharge
Command
All Banks
Document : 1G5-0154 Rev.1 Page 29
Mode Register
Set
Command
Command
Page 30
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VIS
AC Parameters for Write Timing (1 of 2)
CMOS Synchronous Dynamic RAM
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
Burst Length=4, CAS Latency=2
CLK
CKE
CS
RAS
CAS
WE
BS
t
CH
t
CKS
t
CL
t
CMS
t
CMH
t
CK2
Begin Auto Precharge
Bank A
Begin Auto Precharge
(Bank D)
Bank B
t
CKH
A10
t
t
AS
AH
ADD
DQM
t
RCD
DQ
Activate
Command
Bank A
t
RRD
QAa0
Write with
Auto Precharge
Command
Bank A
t
RC
QAa1
QAa2 QAa3 QBa0
Activate
Command
Bank B
(Bank D)
t
DAL
Write with
Auto Precharge
Command
Bank B
(Bank D)
QBa1
QBa2 QBa3
Activate
Command
Bank A
t
DS
QAb0 QAb1 QAb2
Write without
Auto Precharge
Command
Bank A
t
t
DPL
Precharge
Command
Bank A
RP
Activate
Command
Bank A
Activate
Command
Bank B
(Bank D)
t
DH
QAb3
Document : 1G5-0154 Rev.1 Page 30
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VIS
AC Parameters for Write Timing (2 of 2)
CMOS Synchronous Dynamic RAM
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
Burst Length=4, CAS Latency=3,4
CLK
CKE
CS
RAS
CAS
WE
BS
t
CL
t
CH
t
t
CKS
CMS
t
CMH
t
CK3
Begin Auto Precharge
Bank A
Begin Auto Precharge
Bank B
(Bank D)
t
CKH
A10
t
t
AS
AH
ADD
DQM
t
RCD
DQ
Activate
Command
Bank A
t
RRD
QAa0
Write with
Auto Precharge
Command
Bank A
QAa1
Activate
Command
Bank B
(Bank D)
t
RC
QAa2
QAa3 QBa0 QBa1
t
DAL
Write with
Auto Precharge
Command
Bank B
(Bank D)
t
DS
QBa2
QBa3 QAb0 QAb1 QAb2
Activate
Command
Bank A
Write without
Auto Precharge
Command
Bank A
t
QAb3
DPL
Precharge
Command
Bank A
t
DH
t
RP
Activate
Command
Bank A
Document : 1G5-0154 Rev.1 Page 31
Page 32
VG36128401A
Preliminary VG36128801A
VG36128161A
VIS
AC Parameters for Read Timing (1 of 2)
CMOS Synchronous Dynamic RAM
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13
Burst Length=2, CAS Latency=2
CLK
CKE
CS
RAS
CAS
WE
BS
A10
tCHt
t
CKS
CL
t
AS
t
AH
t
CK2
t
CMS
t
CMH
Bank B
Begin Auto
Precharge
(Bank D)
t
CKH
ADD
t
RRD
t
RAS
t
RC
DQM
DQ
Hi-Z
Activate
Command
Bank A
t
RCD
Read
Command
Bank A
t
t
LZ
AC2
t
AC2
t
OH
QAa0
Activate
Command
Bank B
(Bank D)
t
HZ
t
OH
QAa1
Read with
Auto Precharge
Command
(Bank D)
Bank B
QBa0
Precharge
Command
Bank A
t
RP
t
HZ
QBa1
Activate
Command
Bank A
Document : 1G5-0154 Rev.1 Page 32
Page 33
VG36128401A
Preliminary VG36128801A
VG36128161A
VIS
AC Parameters for Read Timing (2 of 2)
CLK
CKE
CS
CMOS Synchronous Dynamic RAM
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15
t
CH
t
CKS
t
CL
t
CK3
t
CMS
t
CMH
Burst Length=2, CAS Latency=3
Begin Auto
Precharge
(Bank D)
Bank B
t
CKH
RAS
CAS
WE
BS
A10
ADD
DQM
t
AH
t
AS
t
RRD
t
RAS
t
RC
t
RP
t
t
OH
AC3
t
HZ
t
OH
Read with
Auto Precharge
Command
Bank B
(Bank D)
Precharge
Command
Bank A
QBa0
QBa1
t
HZ
Command
DQ
Hi-Z
Activate
Command
Bank A
t
RCD
Read
Command
Bank A
t
AC3
t
LZ
Activate
Command
Bank B
(Bank D)
QAa0 QAa1
Document : 1G5-0154 Rev.1 Page 33
Activate
Bank A
Page 34
VG36128401A
Preliminary VG36128801A
VG36128161A
VIS
Power on Sequence and Auto Refresh (CBR)
CLK
CMOS Synchronous Dynamic RAM
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CKE
CS
RAS
CAS
WE
BS
A10
High level
is required
Minimum of 2 Refresh Cycles are required
t
RSC
Address Key
ADD
DQM
DQ
Hi-Z
High Level is Necessary
Precharge
Command
Inputs
All Banks
must
be stable
for 100us
t
RP
1st Auto
Refresh
Command
2nd Auto
Refresh
Command
t
RC
Register
Mode
Set Command
Command
Document : 1G5-0154 Rev.1 Page 34
Page 35
VG36128401A
Preliminary VG36128801A
VG36128161A
VIS
Clock Suspension During Burst Read (Using CKE) (1 of 2)
CMOS Synchronous Dynamic RAM
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
Burst Length=4, CAS Latency=2
CLK
CKE
CS
RAS
CAS
WE
BS
t
CK2
A10
ADD
RAa
RAa
CAa
DQM
t
HZ
Hi-Z
DQ
Activate
Command
Bank A
Read
Command
Bank A
QAa0 QAa1 QAa2 QAa3
Clock
Suspended
1 Cycle
Clock
Suspended
2 Cycles
Clock
Suspended
3 Cycles
Document : 1G5-0154 Rev.1 Page 35
Page 36
VG36128401A
Preliminary VG36128801A
VG36128161A
VIS
Clock Suspension During Burst Read (Using CKE) (2 of 2)
CLK
CKE
CS
CMOS Synchronous Dynamic RAM
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t
CK3
Burst Length=4, CAS Latency=3
RAS
CAS
WE
BS
A10
ADD
DQM
DQ
Hi-Z
RAa
RAa
CAa
QAa0
QAa1
QAa2 QAa3
t
HZ
Activate
Command
Bank A
Read
Command
Bank A
Clock
Suspended
1 Cycles
Clock
Suspended
2 Cycles
Clock
Suspended
3 Cycles
Document : 1G5-0154 Rev.1 Page 36
Page 37
VG36128401A
Preliminary VG36128801A
VG36128161A
VIS
Clock Suspension During Burst Write (Using CKE) (1 of 2)
CMOS Synchronous Dynamic RAM
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
Burst Length=4, CAS Latency=2
CLK
CKE
CS
RAS
CAS
WE
BS
t
CK2
A10
ADD
RAa
RAa
CAa
DQM
DQ
Hi-Z
Activate
Command
Bank A
DAa0 DAa1 DAa2 DAa3
Suspended
Write
Command
Bank A
Clock
1 Cycle
Clock
Suspended
2 Cycles
Clock
Suspended
3 Cycles
Document : 1G5-0154 Rev.1 Page 37
Page 38
VG36128401A
Preliminary VG36128801A
VG36128161A
VIS
Clock Suspension During Burst Write (Using CKE) (2 of 2)
CMOS Synchronous Dynamic RAM
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
Burst Length=4, CAS Latency=3
CLK
CKE
CS
RAS
CAS
WE
BS
t
CK
A10
ADD
RAa
RAa
CAa
DQM
DQ
Hi-Z
Activate
Command
Bank A
DAa0 DAa1 DAa2 DAa3
Suspended
Write
Command
Bank A
Clock
1 Cycle
Clock
Suspended
2 Cycles
Clock
Suspended
3 Cycles
Document : 1G5-0154 Rev.1 Page 38
Page 39
VG36128401A
Preliminary VG36128801A
VG36128161A
VIS
Power Down Mode and Clock Mask
CMOS Synchronous Dynamic RAM
Burst Length=4, CAS Latency=2
CLK
CKE
CS
RAS
CAS
WE
CLK can be Stopped
*
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t
CK2
t
CKS
t
CKH
VALID
t
CKS
BS
A10
ADD
DQM
DQ
Hi-Z
RAa
RAa
RAa
Activate
Command
Bank A
Power Down
Mode Entry
ACTIVE
STANDBY
Read
Command
Bank A
Power Down
Mode Exit
CAa
QAa0
QAa1
Clock Mask
Start
QAa2
Clock Mask
End
t
HZ
QAa3
Precharge
Command
Power Down
Mode Entry
Precharge
Standby
Power
Down
Mode
Exit
Command
Document : 1G5-0154 Rev.1 Page 39
Page 40
VIS
Auto Refresh (CBR)
CLK
CKE
CS
VG36128401A
Preliminary VG36128801A
VG36128161A
CMOS Synchronous Dynamic RAM
Burst Length=4, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t
CK2
RAS
CAS
WE
BS
A10
ADD
DQM
DQ
Hi-Z
RAa
RAa
t
RP
t
RC
t
RC
CAa
Q0 Q1
Q2
Q3
Precharge
Command
All Banks
CBR Refresh
Command
CBR Refresh
Command
Activate
Command
Read
Command
Document : 1G5-0154 Rev.1 Page 40
Page 41
VG36128401A
Preliminary VG36128801A
VG36128161A
VIS
Self Refresh (Entry and Exit)
CMOS Synchronous Dynamic RAM
CLK
CKE
CS
RAS
CAS
WE
CLK can be Stopped
*
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t
CKS
t
SRX
t
SRX
t
CKS
BS
A10
ADD
DQM
DQ
Hi-Z
All Banks
must be idle
Self refresh
Entry
Self Refresh
Exit
t
RC
Self Refresh
Entry
Self Refresh
Exit
t
RC
Activate
Command
* Clock can be stopped at CKE=Low. If clock is stopped, it must be restarted/stable for 4 clock cycles before CKE=High
Document : 1G5-0154 Rev.1 Page 41
Page 42
VG36128401A
Preliminary VG36128801A
VG36128161A
VIS
Random Column Read (Page Within same Bank)(1 of 2)
CLK
CKE
CS
CMOS Synchronous Dynamic RAM
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t
CK2
Burst Length=4, CAS Latency=2
RAS
CAS
WE
BS
A10
ADD
DQM
DQ
Hi-Z
RAa
RAa
CAa
QAa0 QAa1
CAb CAc
QAa2 QAa3 QAb0
QAc0 QAc1 QAc2
QAb1
QAc3
RAa
RAd
RAd
CAd
QAd0
QAd1
QAd2
QAd3
Precharge
Command
Bank A
Read
Command
Bank A
Read
Command
Bank A
Read
Command
Bank A
Precharge
Command
Bank A
Activate
Command
Bank A
Read
Command
Bank A
Document : 1G5-0154 Rev.1 Page 42
Page 43
VG36128401A
Preliminary VG36128801A
VG36128161A
VIS
Random Column Read (Page Within same Bank)(2 of 2)
CLK
CKE
CS
CMOS Synchronous Dynamic RAM
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t
CK3
Burst Length=4, CAS Latency=3
RAS
CAS
WE
BS
A10
ADD
DQM
DQ
Hi-Z
RAa
RAa
CAa
CAb CAc RAd
QAa0 QAa1 QAa2
QAb0 QAb1 QAc0
QAa3
QAc1
QAc2 QAc3
RAd
CAd
Activate
Command
Bank A
Read
Command
Bank A
Read
Command
Bank A
Read
Command
Bank A
Precharge
Command
Bank A
Activate
Command
Bank A
Read
Command
Bank A
Document : 1G5-0154 Rev.1 Page 43
Page 44
VG36128401A
Preliminary VG36128801A
VG36128161A
VIS
Random Column Write (Page Within same Bank) (1 of 2)
CLK
CKE
CS
CMOS Synchronous Dynamic RAM
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t
CK2
Burst Length=4, CAS Latency=2
RAS
CAS
WE
BS
A10
ADD
DQM
DQ
Hi-Z
Ra
Ra
Ca
Da0
Da1 Da2
Cb Cc Rd
Db0 Db1 Dc0
Da3
Dc1
Dc2 Dc3
Rd
Cd
Dd0
Dd1
Dd2 Dd3
Activate
Command
Bank B
(Bank D)
Write
Command
Bank B
(Bank D) (Bank D)
Write
Command
Bank B
Write
Command
Bank B
(Bank D)
Precharge
Command
Bank B
(Bank D)
Activate
Command
Bank B
(Bank D) (Bank D)
Write
Command
Bank B
Document : 1G5-0154 Rev.1 Page 44
Page 45
VG36128401A
Preliminary VG36128801A
VG36128161A
VIS
Random Column Write (Page Within same Bank) (1 of 2)
CLK
CKE
CS
CMOS Synchronous Dynamic RAM
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t
CK
Burst Length=4, CAS Latency=3
RAS
CAS
WE
BS
A10
ADD
DQM
DQ
Hi-Z
Ra
Ra
Ca
Da0
Da1 Da2
Da3
Cb
Db0 Db1
Rd
Cc Cd
Dc1
Dc2 Dc3
Dc0
Rd
Dd0
Dd1
Activate
Command
Bank B
(Bank D) (Bank D)
Write
Command
Bank B
Write
Command
Bank B
(Bank D)
Write
Command
Bank B
(Bank D)
Precharge
Command
Bank B
(Bank D)
Activate
Command
Bank B
(Bank D)
Write
Command
Bank B
(Bank D)
Document : 1G5-0154 Rev.1 Page 45
Page 46
VG36128401A
Preliminary VG36128801A
VG36128161A
VIS
Random Row Read (Interleaving Banks)(1 of 2)
CLK
CKE
High
CS
CMOS Synchronous Dynamic RAM
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t
CK2
Burst Length=8, CAS Latency=2
RAS
CAS
WE
BS
A10
ADD
DQM
DQ
Hi-Z
t
RCD
t
AC2
QBa1 QBa2
QBa3
QBa5 QBa6 QBa7
QBa4
t
RP
QAa0
QAa1
QAa2
QAa3 QAa4
QAa5
QAa6 QAa7
QBb1
QBb0QBa0
Activate
Command
Bank B
(Bank D)
Read
Command
Bank B
(Bank D)
Activate
Command
Bank A
Precharge
Command
Bank B
(Bank D)
Read
Command
Bank A
Active
Command
Bank B
(Bank D)
Read
Command
Bank B
(Bank D)
Document : 1G5-0154 Rev.1 Page 46
Page 47
VG36128401A
Preliminary VG36128801A
VG36128161A
VIS
Random Row Read (Interleaving Banks) (2 of 3)
CMOS Synchronous Dynamic RAM
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
Burs tLength=8, CAS Latency=3
CLK
CKE
CS
RAS
CAS
WE
BS
High
t
CK3
A10
ADD
DQM
DQ
Hi-Z
Activate
Command
Bank B
(Bank D)
t
RCD
Read
Command
Bank B
(Bank D)
t
AC3
QBa2
QBa1
Activate
Command
Bank A
QBa3
QBa5
QBa4
Read
Command
Bank A
QBa6 QBa7
Precharge
Command
Bank B
(Bank D)
t
RP
QAa0 QAa1
QAa2
QAa3
Activate
Command
Bank B
(Bank D)
QAa4
QAa6
QAa5
Read
Command
Bank B
(Bank D)
QAa7
Precharge
Command
Bank A
Document : 1G5-0154 Rev.1 Page 47
QBb0QBa0
Page 48
VG36128401A
Preliminary VG36128801A
VG36128161A
VIS
Random Row Write (Interleaving Banks) (1 of 2)
CMOS Synchronous Dynamic RAM
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
Burst Length=8, CAS Latency=2
CLK
CKE
CS
RAS
CAS
WE
BS
High
t
CK2
A10
ADD
DQM
DQ
Hi-Z
Activate
Command
Bank A
t
RCD
Write
Command
Bank A
QAa1 QAa2
QAa3
QAa4
QAa5
QAa6 QAa7
Activate
Command
Bank B
(Bank D)
t
DPL
QBa0 QBa1
Precharge
Command
Bank A
Write
Command
Bank B
(Bank D)
t
RP
QBa2
Command
Bank A
QBa3 QBa4
Active
QBa5
QBa6 QBa7
Command
QAb0 QAb1
Write
Bank A
t
DPL
QAb2QAa0
Precharge
Command
Bank B
(Bank D)
QAb3
Document : 1G5-0154 Rev.1 Page 48
QAb4
Page 49
VG36128401A
Preliminary VG36128801A
VG36128161A
VIS
Random Row Write (Interleaving Banks) (2 of 2)
CMOS Synchronous Dynamic RAM
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
Burst Length=8, CAS Latency=3
CLK
CKE
CS
RAS
CAS
WE
BS
High
t
CK
A10
ADD
DQM
DQ
Hi-Z
Activate
Command
Bank A
t
RCD
QAa0 QAa1
Write
Command
Bank A
QAa2
QAa3
RBa
QAa4
QAa5 QAa6
Activate
Command
Bank B
(Bank D)
QAa7 QBa0
Write
Command
Bank B
(Bank D)
t
DPL
QBa1
QBa2 QBa3
Precharge
Command
Bank A
t
RP
QBa4
QBa5 QBa6
Activate
Command
Bank A
QBb7 QAb0
Write
Command
Bank A
t
DPL
QAb1
Command
(Bank D)
QAb2
Precharge
Bank B
Document : 1G5-0154 Rev.1 Page 49
QAb3
Page 50
VG36128401A
Preliminary VG36128801A
VG36128161A
VIS
Read and Write Cycle (1 of 2)
CLK
CKE
CS
CMOS Synchronous Dynamic RAM
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t
CK2
Burst Length=4, CAS Latency=2
RAS
CAS
WE
BS
A10
ADD
DQM
RAa
RAa
CAb
CAc CAa
DQ
Hi-Z
Activate
Command
Bank A
Write
Command
Bank A
QAa0
QAa1
QAa2
QAa3
DAb0
Write
Command
Bank A
DAb1
The Write Data
is Masked with a
Zero Clock
latency
DAb3 QAc0
Read
Command
Bank A
QAc1
The Read Data
is Masked with
QAc3
Two Clocks
Latency
Document : 1G5-0154 Rev.1 Page 50
Page 51
VG36128401A
Preliminary VG36128801A
VG36128161A
VIS
Read and Write Cycle (2 of 2)
CMOS Synchronous Dynamic RAM
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
Burst Length=4, CAS Latency=3
CLK
CKE
CS
RAS
CAS
WE
BS
t
CK3
A10
ADD
RAa
RAa
CAa
CAb
CAc
DQM
DQ
Hi-Z
Activate
Command
Bank A
Read
Command
Bank A
QAa0 QAa1
QAa2
QAa3
DAb0 DAb1
Write
Command
Bank A
DAb3
The Write Data
is Masked with a
Zero Clock
Latency
Read
Command
Bank A
QAc0
QAc1
The Read Data
is Masked with
a Two Clock
Latency
Document : 1G5-0154 Rev.1 Page 51
QAc3
Page 52
VG36128401A
Preliminary VG36128801A
VG36128161A
VIS
Interleaved Column Read Cycle (1 of 2)
CMOS Synchronous Dynamic RAM
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
Burst Length=4, CAS Latency=2
CLK
CKE
CS
RAS
CAS
WE
BS
t
CK2
A10
ADD
DQM
DQ
Ra Ra
Ra
t
Hi-Z
Activate
Command
Bank A
RCD
Command
Bank A
Cb
Read
Ra
t
AC2
QAa0 QAa1
Activate
Command
Command
Bank B
(Bank D) (Bank D)
Ca Cb Cc Cb Cd
QAa2
Read
Bank B
QBa0
QAa3
Command
(Bank D)
Read
Bank B
QBa1
QBb0 QAb0
Read
Command
Bank B
(Bank D)
QBc0
QBb1 QBd0
Read
Command
Bank A
QBc1
Command
Bank B
(Bank D)
Read
QAb1
Precharge
Command
Bank A
QBd1
QBd2
Precharge
Command
Bank B
(Bank D)
QBd3
Document : 1G5-0154 Rev.1 Page 52
Page 53
VG36128401A
Preliminary VG36128801A
VG36128161A
VIS
Interleaved Column Read Cycle (2 of 2)
CMOS Synchronous Dynamic RAM
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
Burst Length=4, CAS Latency=3
CLK
CKE
CS
RAS
CAS
WE
BS
t
CK3
A10
ADD
Ra Ra
Ra
Ra
Ca
Ca Cb Cc
Cb
DQM
t
DQ
Hi-Z
Activate
Command
Bank A
RCD
t
RRD
Read
Command
Bank A
Activate
Command
(Bank D)
Bank B
t
AC3
QAa1
QAa0
Read
Command
Bank B
(Bank D) (Bank D)
QAa3
QAa2
Command
Bank B
Read
QBa0
QBb0 QAb0
QBa1 QAb3
Read
Command
Bank B
(Bank D)
QBc0
QBb1 QAb2
Read
Command
Bank A
QBc1
Precharge
Command
Bank B
(Bank D)
QAb1
Precharge
Command
Bank A
Document : 1G5-0154 Rev.1 Page 53
Page 54
VG36128401A
Preliminary VG36128801A
VG36128161A
VIS
Interleaved Column Write Cycle (1 of 2)
CLK
CKE
CS
CMOS Synchronous Dynamic RAM
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t
CK2
Burst Length=4, CAS Latency=2
RAS
CAS
WE
BS
A10
ADD
DQM
Ra Ra
Ra
t
RCD
t
RRD
Ca
Ra
Ca Cb Cc
Cb
Cb
t
t
RP
DPL
DQ
Hi-Z
Activate
Command
Bank A
DAa0 DAa1
Write
Command
Bank A
DAa3
DAa2
Activate
Command
Bank B
(Bank D)
DBa0 DBa1 DBd1
Write
Command
Bank B
(Bank D)
DBb0 DAb0
Write
Command
Bank B
(Bank D)
DBb1
DBc0 DBc1
Write
Command
Bank B
(Bank D)
Write
Command
Bank A
DAb1
DBd0
Precharge
Command
Bank A
Write
Command
Bank B
(Bank D)
DBd2 DBd3
Precharge
Command
Bank B
(Bank D)
Document : 1G5-0154 Rev.1 Page 54
Page 55
VG36128401A
Preliminary VG36128801A
VG36128161A
VIS
Interleaved Column Write Cycle (2 of 2)
CLK
CKE
CS
CMOS Synchronous Dynamic RAM
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t
CK
Burst Length=4, CAS Latency=3
RAS
CAS
WE
BS
A10
ADD
DQM
Ra Ra
Ra
Ra
t
t
Ca
RCD
RRD
Ca Cb Cc
Cb
t
DPL
Cd
t
DPL
t
RP
DQ
Hi-Z
Activate
Command
Bank A
QAa0 QAa1
Write
Command
Bank A
Activate
Command
Bank B
(Bank D)
QAa2
QAa3
Command
(Bank D)
QBa0 QBa1
Write
Bank B
QBb0 QAb0
Write
Command
Bank B
(Bank D)
QBc0 QBc1
QBb1 QBd0
Write
Command
Bank B
(Bank D)
Write
Command
Bank A
QAb1
QBd1
Write
Command
Bank B
(Bank D)
Precharge
Command
Bank A
QBd2 QBd3
Precharge
Command
Bank B
(Bank D)
Document : 1G5-0154 Rev.1 Page 55
Page 56
VG36128401A
Preliminary VG36128801A
VG36128161A
VIS
Auto Precharge after Read Burst (1 of 2)
CMOS Synchronous Dynamic RAM
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
Burst Length=4, CAS Latency=2
CLK
CKE
CS
RAS
CAS
WE
BS
High
t
CK2
Start Auto Precharge
(Bank D)
Bank B
Start Auto Precharge
Bank A
Start Auto Precharge
(Bank D)
Bank B
A10
ADD
Ra Ra
Ra
Ca
Ra
Ca Cb Rb
Rb Rc
Cb
Rc
Cc
DQM
DQ
Hi-Z
Activate
Command
Bank A
Read
Command
Bank A
QAa0
Activate
Command
Bank B
(Bank D)
QAa1
QAa2
Read with
Auto Precharge
Command
Bank B
(Bank D)
QAa3
QBa0
QBa2 QAb2
QBa1 QBb1
Read with
Auto Precharge
Command
Bank A
QAb0
QBa3 QBb0
Activate
Command
Bank B
(Bank D)
QAb1
Auto Precharge
Read with
Command
Bank B
(Bank D)
QAb3
Activate
Command
Bank A
Auto Precharge
QBb2 QBb3
Read with
Command
Bank A
QAc1
QAc0 QAc2
Document : 1G5-0154 Rev.1 Page 56
Page 57
VG36128401A
Preliminary VG36128801A
VG36128161A
VIS
Auto Precharge after Write Burst (2 of 2)
CLK
CMOS Synchronous Dynamic RAM
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t
CK3
Burst Length=4, CAS Latency=3
CKE
CS
RAS
CAS
WE
BS
A10
High
Ra
Ra
Rb
Start Auto
Precharge
Bank A
Start Auto Precharge
(Bank D) (Bank D)
Bank B
Start Auto Precharge
Bank B
ADD
Ra
Ca
Ra
Ca
Cb
Rb
RBb
Cb
DQM
DQ
Hi-Z
Activate
Command
Bank A
Activate
Command
Bank B
(Bank D)
Read
Command
Bank A
QAa0 QAa1
Read with
Auto Precharge
Command
Bank B
QAa2
(Bank D)
QAa3
QBa0
QBa1
QBa2 QAb2
Read with
Auto Precharge
Command
Bank A
QBa3
Command
(Bank D)
QAb0
Activate
Bank B
QAb1
Auto precharge
Bank B
QAb3
Write with
Command
(Bank D)
QBb0
QBb1 QBb2
Document : 1G5-0154 Rev.1 Page 57
Page 58
VG36128401A
Preliminary VG36128801A
VG36128161A
VIS
Auto Precharge after Write Burst (1 of 2)
CMOS Synchronous Dynamic RAM
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
Burst Length=4, CAS Latency=2
CLK
CKE
CS
RAS
CAS
WE
BS
High
t
CK2
Start Auto Precharge
(Bank D)
Bank B
Start Auto Precharge
Bank A
Start Auto Precharge
(Bank D)
Bank B
A10
ADD
Ra
Ra
Ra
Ra
Ca
Cb
Rb
Rb
Rc
Cb Ca
Rc Cc
DQM
DQ
Hi-Z
Activate
Command
Bank A
QAa0 QAa1
Write
Command
Bank A
QAa3
QAa2
Activate
Command
Bank B
(Bank D)
QBa0 QBa1 QBb1
Write with
Auto Precharge
Command
Bank B
(Bank D)
QBa2 QAb2
QAb0 QAb1
QBa3
Write with
Auto Precharge
Command
Bank A
Activate
Command
Bank B
(Bank D)
QBb0
QAb3
Write with
Auto Precharge
Command
Bank B
(Bank D)
QBb2 QBb3
Activate
Command
Bank A
QAc0 QAc1 QAc2 QAc3
Write with
Auto Precharge
Bank A
Start Auto
Precharge
Document : 1G5-0154 Rev.1 Page 58
Bank A
Page 59
VG36128401A
Preliminary VG36128801A
VG36128161A
VIS
Auto Precharge after Write Burst (2 of 2)
CLK
CMOS Synchronous Dynamic RAM
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t
CK
Burst Length=4, CAS Latency=3
CKE
CS
RAS
CAS
WE
BS
A10
High
Ra
Ra
Start Auto Precharge
Bank B
(Bank D)
Rb
Start Auto
Precharge
Bank A
Start Auto Precharge
(Bank D)
Bank B
ADD
Ra
Ca
Ra
Ca
Cb
Rb
RBb
Cb
DQM
DQ
Hi-Z
Activate
Command
Bank A
QAa0 QAa1
Activate
Command
Bank B
(Bank D)
Read
Command
Bank A
QAa2
QBa0
QAa3
Read with
Auto Precharge
Command
Bank B
QAb0
QBa1
(Bank D)
QBa3
QBa2 QAb2
Read with
Auto Precharge
Command
Bank A
QAb1
QAb3
Activate
Command
Bank B
(Bank D)
QBb0
QBb1 QBb2
Write with
Auto precharge
Command
(Bank D)
Bank B
QBb3
Document : 1G5-0154 Rev.1 Page 59
Page 60
VG36128401A
Preliminary VG36128801A
VG36128161A
VIS
Full Page Read Cycle (1 of 2)
CLK
High
CKE
CS
CMOS Synchronous Dynamic RAM
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t
CK2
Burst Length=Full Page, CAS Latency=2
RAS
CAS
WE
BS
A10
ADD
DQM
DQ
Hi-Z
Ra
Ra
Ra
QAa-1
Ca
QAa+1 QBa QBa+1
QAa
QBa+2
QBa+3
QBa+4 QBa+51
QBa+6
Ca Rb
Ra
QAa
QAa+1
QAa+2
QAa-2
Rb
t
RP
Full page burst operation does not
Activate
Command
Bank A
Read
Command
Bank A
Activate
Command
Bank B
(Bank D)
The burst counter wraps
from the highest order
page address back to zero
during this time interval
Read
Command
Bank B
(Bank D)
terminate when the burst length is
satisfied; the burst counter
increments and continues bursting
beginning with the starting address
Precharge
Command
Bank B
(Bank D)
Burst Stop
Command
Activate
Command
Bank B
(Bank D)
Document : 1G5-0154 Rev.1 Page 60
Page 61
VG36128401A
Preliminary VG36128801A
VG36128161A
VIS
Full Page Read Cycle (2 of 2)
CMOS Synchronous Dynamic RAM
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
Burst Length=Full Page, CAS Latency=3
CLK
CKE
CS
RAS
CAS
WE
BS
High
t
CK3
A10
ADD
Ra
Ra
Ra
Ca Rb
Ra
Ca
Rb
DQM
DQ
Hi-Z
Activate
Command
Bank A
Read
Command
Bank A
Activate
Command
Bank B
(Bank D)
QAa+2
QAa+1
QAa
The burst counter wraps
from the highest order
page address back to zero
during this time interval
QAa-2
Command
Bank B
(Bank D)
QAa+1
QAa
QAa-1
Full page burst operation
Read
does not teminate when
the burst length is satisfied;
the burst counter increments
and continues bursting
beginning with the starting
address
QBa0
QBa+1
QBa+2
QBa+3
Precharge
Command
Bank B
(Bank D)
Burst Stop
Command
QBa+4
QBa+5
Activate
Command
Bank B
(Bank D)
Document : 1G5-0154 Rev.1 Page 61
Page 62
VG36128401A
Preliminary VG36128801A
VG36128161A
VIS
Full Page Write Cycle (1 of 2)
CLK
CKE
High
CS
CMOS Synchronous Dynamic RAM
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t
CK2
Burst Length=Full Page, CAS Latency=2
RAS
CAS
WE
BS
A10
ADD
DQM
DQ
Hi-Z
Ra
Ra
Ra
Ca Rb
QAa
QAa+1
Ra
QAa+2 QAa+3
QAa-1
QAa
QAa+1
Ca
QBa
QBa+1
QBa+2
QBa+3
QBa+4
QBa+5
QBa+6
t
BDL
Rb
Activate
Command
Bank A
Write
Command
Bank A
Activate
Command
Bank B
(Bank D)
The burst counter wraps
from the highest order
page address back to zero
during this time interval
Write
Command
Bank B
(Bank D)
Full page burst operation
does not terminate when
the burst length is satisfied;
the burst counter increments
and continues bursting
beginning with the starting
address
Data is ignored
Precharge
Command
Bank B
(Bank D) (Bank D)
Burst Stop
Command
Activate
Command
Bank B
Document : 1G5-0154 Rev.1 Page 62
Page 63
VG36128401A
Preliminary VG36128801A
VG36128161A
VIS
Full Page Write Cycle (2 of 2)
CLK
CKE
High
CS
CMOS Synchronous Dynamic RAM
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t
CK
Burst Length=Full Page, CAS Latency=3
RAS
CAS
WE
BS
A10
ADD
DQM
DQ
Hi-Z
Ra
Ra
Ca
DAa
DAa+1
Ra
Ra
DAa+2 DAa+3
DAa-1
DAa
DAa+1
Ca
DBa
DBa+1 DBa+2
DBa+3
DBa+4
DBa+5
t
BDL
Rb
Rb
Data is ignored.
Activate
Command
Bank A
Write
Command
Bank A
Activate
Command
Bank B
(Bank D)
The burst counter wraps
from the highest order
page address back to zero
during this time interval
Write
Command
Bank B
(Bank D)
Full page burst operation
does not terminate when
the burst length is satisfied;
the burst counter increments
and continues bursting
beginning with the starting
address
Precharge
Command
Bank B
(Bank D)
Burst Stop
Command
Activate
Command
Bank B
(Bank D)
Document : 1G5-0154 Rev.1 Page 63
Page 64
VIS
Byte Write Operation
VG36128401A
Preliminary VG36128801A
VG36128161A
CMOS Synchronous Dynamic RAM
Burst Length = 4, CAS Latency = 2
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
CS
RAS
CAS
WE
BS
A10
High
RAa
t
CK2
ADD
RAa
CAa
CAb
CAz
LDQM
UDQM
DQ0~DQ7
DQ8~DQ15
Hi-Z
Hi-Z
Activate
Command
Bank A
Read
Command
Bank A
Upper Byte
is masked
Lower Byte
is masked
Write
Command
Bank A
Write Upper
is masked
Read
Command
Bank A
Lower Byte
is masked
Lower Byte
is masked
Document : 1G5-0154 Rev.1 Page 64
Page 65
VG36128401A
Preliminary VG36128801A
VG36128161A
VIS
Burst Read and Single Write Operation
CMOS Synchronous Dynamic RAM
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
Burst Length = 4, CAS Latency = 2
CLK
CKE
CS
RAS
CAS
WE
BS
A10
High
RAa
t
CK2
ADD
RAa
CAa
CAb
CAc
CAd
CAe
LDQM
UDQM
DQ0~DQ7
DQ8~DQ15
Hi-Z
Hi-Z
Activate
Command
Bank A
Read
Command
Bank A
Single Write
Command
Bank A
Single Write
Command
Bank A
Read
Command
Bank A
Lower Byte
is masked
Upper Byte
is masked
Single Write
Command
Bank A
Document : 1G5-0154 Rev.1 Page 65
Lower Byte
is masked
Page 66
VG36128401A
Preliminary VG36128801A
VG36128161A
VIS
Full Page Random Column Read
CLK
CKE
CS
CMOS Synchronous Dynamic RAM
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t
CK2
Burst Length=Full Page, CAS Latency=2
RAS
CAS
WE
BS
A10
ADD
DQM
DQ
Hi-Z
Ra
Ra
Ra
Ra Ca Ca
Cb Cb
QBa0
QAa0
QAb0 QAb1
QBb0
QBb1 QAc0
Cc Cc Rb
t
RP
QAc2
QAc1
QBc0
QBc1 QBc2
Rb
Activate
Command
Bank A
Activate
Command
Bank B
(Bank D) (Bank D)
Command
Read
Command
Bank A
Read
Bank B
Read
Command
Bank A
Read
Command
Bank B
(Bank D)
Read
Command
Bank A
Read
Command
Bank B
(Bank D)
Precharge
Command Bank B
(Precharge Termination)
(Bank D)
Activate
Command
Bank B
(Bank D)
Document : 1G5-0154 Rev.1 Page 66
Page 67
VG36128401A
Preliminary VG36128801A
VG36128161A
VIS
Full Page Random Column Write
CMOS Synchronous Dynamic RAM
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
Burst Length=Full Page, CAS Latency=2
CLK
CKE
CS
RAS
CAS
WE
BS
t
CK2
A10
ADD
Ra
Ra
Ra
Ra Ca Ca
Cb Cb
Rb
Cc Cc Rb
t
RP
DQM
DQ
Hi-Z
Activate
Command
Bank A
Activate
Command
Bank B
(Bank D)
Command
QAa0
Write
Bank A
QBa0
Write
Command
Bank B
(Bank D)
Command
QAb0
Write
Bank A
QAb1
Command
Bank B
(Bank D)
QBb0 QBb1
Write
QAc0
Write
Command
Bank A
QAc1
QAc2
Write
Command
Bank B
(Bank D)
QBc0
QBc1
Command Bank B
QBc2
Precharge
Write Data
is masked
(Bank D)
Command
(Bank D)
(Precharge Termination)
Activate
Bank B
Document : 1G5-0154 Rev.1 Page 67
Page 68
VG36128401A
Preliminary VG36128801A
VG36128161A
VIS
Precharge Termination of a Burst (1 of 2)
CMOS Synchronous Dynamic RAM
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
Burst Length=4,8 or Full Page, CAS Latency=2
CLK
CKE
CS
RAS
CAS
WE
BS
High
t
CK2
A10
ADD
DQM
DQ
RAa
RAa CAcCAa
Hi-Z
Activate
Command
Bank A
QAa0
QAa1
Write
Command
Bank A
Precharge Termination
of a Write Burst. Write
data is masked.
QAa2
t
DPLtRP
Da3
Precharge
Command
Bank A
RAb
RAb
Activate
Command
Bank A
Read
Command
Bank A
t
RP
QAb1
QAb0
Precharge
Command
Bank A
Precharge Termination
of a Read Burst.
QAb2
Activate
Command
Bank A
RAc
RAc CAb
Read
Command
Bank A
QAc0
Precharge
Command
QAc1
Bank A
t
RP
QAc2
Document : 1G5-0154 Rev.1 Page 68
Page 69
VG36128401A
Preliminary VG36128801A
VG36128161A
VIS
Precharge Termination of a Burst (2 of 2)
CLK
CKE
High
CS
CMOS Synchronous Dynamic RAM
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t
CK3
Burst Length=4,8 or Full Page, CAS Latency=3
RAS
CAS
WE
BS
A10
ADD
DQM
RAa
RAa RAcCAa
t
RCD
t
DPL
RAb
RAb
t
RP
CAb
t
RAS
RAc
t
RP
DQ
Hi-Z
Activate
Command
Bank A
Write
Command
Bank A
Write Data
is masked
DAa1DAa0
Precharge
Command
Bank A
Precharge Termination
Command
of a Write Burst.
Activate
Bank A
Read
Command
Bank A
QAb0 QAb1
Activate
Command
Bank A
QAb2 QAb3
Activate
Command
Bank A
Precharge Termination
of a Read Burst.
Document : 1G5-0154 Rev.1 Page 69
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