Datasheet V96SSC-33LP Datasheet (V3 Semiconductor)

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V96SSC

Rev. B1

HIGH-INTEGRA TIO N SYSTEM CONTROLLER

FOR i960Sx/Jx AND PowerPC™ 401Gx

PROCESSORS

V3 Semiconductor reserves the right to change the specificati ons of this product wit hout notice. V96SSC and V96xPBC are trademarks of V3 Semiconductor. All other trademarks are the propert

of their respective owners.

• Direct interface to i960Sx/Jx and PPC401Gx processors

• High-performance burst DRAM controller

• Two-channel fly-by DMA controller

• Serial communications unit

• Programmable chip-select/strobe generation

• Support for 8/16-bit boot PROMs

• Two 32-bit general purpose timers

• Pulse width modulat ion capabilit

• System watchdog and heartbeat timers

• 16 general purpose I/O bits

• Eight input port s and eight output ports

• Interrupt control unit

• Local bus speeds up to 33MHz

• Low cost 100-pin EIAJ PQFP package

• Fastest time to market for i960Sx and i960Jx based designs

The V96SSC High-Integration System Contro ller is a single-chip device that simplifies the design of systems based on i960Sx, i960Jx or PPC401Gx embedded microprocessors. The V96SSC replac es many lower integration components with a single, high-integration device.

Nearly all i960 or PowerPC processor based systems will require DRAM for code and data storage. The V96SSC includes a highperformance DRAM controller which is programmable to accommodate a wide range of DRAM speeds and architectures.

The eight chip-select/strobes further simplif

peripheral/memo ry connection. Each se lect has programmable timing and a total of four waitstate generators are provided.

Beyond simplifying memory and peripheral control, the V96SSC also includes many of the peripherals needed to build a high-performance i960 or PPC401Gx based system: DMA channels, synchronous/ asynchronous seri al port ,

eneral purpose and system heartbeat timers, bit

I/O ports, and an interrupt controller. In addition, the V96SSC includes special

features to enhance system integrity. The bus watch timer prevents system hangs on access to unpopulated memory. A watchdog timer is also included to recover from software upsets.

Due to its small footprint, and glueless interface, the V96SSC provides the best features of an integrated processor without any performance compromises!

LOCAL BUS

IRQs

DRAM

ARRAY

PROM

ADDR

CHIP SELECTS

AND STROBES

DMA REQUEST

LOCAL BUS

PCI BUS

SYSTEM

CONTROLLER

V96SSC

DEVICE

NETWORKING

V960PBC or V961PBC

CONTROLLER

PCI BRIDGE

PPC401Gx

i960Sx/Jx

CPU

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V96SSC

This document contains the product codes, pinouts, package mechanical information, DC characteristics, and AC characteristics for the V96SSC. Detailed functional information is contained in the User’s Manual.

V3 Semiconductor retains the rights to change documentation, specifications, or device functionality at any time without notice. Please verify that you have the latest copy of all documents before finalizing a design.

1.0 Product Codes

2.0 Functional Description

The V96SSC consists of the foll o wing functional units :

• Direct i960 and PPC401Gx Processors Bus Interface Unit

• Burst DRAM Controller

• DMA Controller

• Serial Communications Unit

• Chip Select/Strobe Unit

• General Purpose Timer/Counters

• System Watchdog and System Heartbeat Timers

• Interrupt Control Un it

• I/O Control Unit and Internal Signal Multiplexer

A block diagram of the V96SSC is shown in Figure 1. Each of the functional units is described briefly in the sections below. The V96SSC Data Sheet provides information regarding AC and DC specifications, pinout, and packaging. Detailed information regarding hardware and softwar e interfacing can be found in the V96SSC User’s Manual

Table 1: Product Codes

Product Code Processor Bus Type Package Frequency

V96SSC-33LP

i960SA/SB

i960JA/JD/JF

PPC401GF

16-bit multiplexed 32-bit multiplexed 32-bit multiplexed

100-pin EIAJ PQFP 33MHz

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V96SSC

Figure 1: V96SSC Block Diagram

2.1 Direct i960 Sx/Jx and PPC401Gx Processors Bus Interface Units

The V96SSC is desi gned t o co nnect di rect ly to i96 0Sx/J x and PP C401 Gx p roces so rs. No “gl ue l ogic” is required. Care was taken during the design of the V96SSC to insure full AC timing compatibility with these processors running with bus speeds up to 33MHz. Even the pinout of the V96SSC has been designed with ease of connection in mind.

At the beginning of each processor bus cycle the V96SSC samples the BTYPE[1:0] pins. As it’s shown in the following table, these pins indicate what type of bus cycle is being run. Because the bus type is dynamically detected, the V96SSC may be used in systems using bot h 16-bit and 32-bit masters.

Table 2: BTYPE[1:0] Pin Decoding

BTYPE[1:0] CPU Mode Boot Address Description

00 i960SA/SB A[31, 26:24]=”0000”

16-bit data bus, BE[1:0] valid for current cycle, both processor and V96SSC use 2x clock

01 PPC401Gx A[31, 26:24]=”1111”

32-bit data bus, BE[3:0] valid for current cycle, processor uses 1X clock and V96SSC uses 2X clock

A31,A[26:16]

AD[15:0]

BE[1:0]

ADS

ALE

BLAST

W/R

BTYPE[1:0]

HLDA

HOLD

INT

RESOUT

RESET

CLK2

SYSTEM

HEARTBEAT/

WATCHDOG

TIMERS

BUS WATCH

i960

PROCESSOR

INTERFACE

SERIAL

COMM

UNIT

DRAM

CONTROL

MA[11:0] RAS[1:0] CAS[3:0] WE OE[1:0] LE

I/O[15:0]

DREQ0 DACK0 DREQ1 DACK1

DMA

TWO

CHANNEL

CHIP SELECT

STROBE

LOGIC

32-BIT

TIMERS (2)

MUX

I/O

and

BIT I/O

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V96SSC

In i960Sx systems, the low order address signals are latched internal ly from the AD[15:0] bus upon assertion of ALE. The high-orde r address lines are demul tiplexed on the i960Sx proces sor, and are routed directly to the V96SSC’s high order address inpu ts. The i960Jx processor uses a 32-bit multiplexed address/data bus, therefore for i960Jx bus accesses, the V96SSC latches the high order address signals internally on the assertion of ALE.

All accesses to V96SSC’s internal registers are performed via the AD[15:0] lines. In 32-bit i960Jx systems, the internal registers are typic ally accessed in a 32 bit r egion where ac cess to the internal registers is done by soft wa re 1 6 bi ts a t a ti me (BTY PE= "10" ). Al terna tely, it can be ma pp ed i nto a 16 bit region using BTYPE="11". While the V96SSC is internally a 16-bit device, it is capable of supporting 32-bit memory and peripheral devi ces.

V96SSC also supports direct interface to PPC401Gx. When BTYPE=”01” then the boot address matches that of the PPC401Gx. In this mode a cycle can be initiated with either an ALE or ADS pulse. Since the PPC401Gx has only an ALE output and lacks an ADS (AS) pin, ADS on the V96SSC ca n be tied high by a pull-up resistor.

2.2 Burst DRAM Controller

The V96SSC’s DRAM controller provides the following features:

• Support for fast page mode, extended data out, and Ramtron’s enhanced DRAM architectures

• Two DRAM banks of up t o 64MByte each (128MBytes total)

• Programmable DRAM bank address base and size

• Programmabl e ro w/column mult ip l ex i ng mo de

• Programmable RASx and CASx timings

• Support for 16-bit and 32-bit DRAM arrays

• Support for extended burst cycles up to 256 bytes transactions in length

• Programmable page caching to eliminate RAS cycles for subsequent accesses to the same DRAM page

• Programmable refresh counter

• 1-0-0-0 read and 0-0-0-0 write performance at 33MHz

The burst DRAM controller is designed to support traditional fast page mode DRAMs (FPM), the new extended data out page mode DRAMs (EDO), and Ramtron’s ultra high-performance enhanced DRAM (Ramtron E DRAM) devices. A wide varie ty of DRAM s peeds and orga nizations may be

i960Jx

(32 bit bus)

A[31, 26:24]=”1110”

32-bit data bus, BE[3:0] valid for current cycle, processor uses 1X clock and V96SSC uses 2X clock

i960Jx

(16 bit bus)

A[31, 26:24]=”1110”

32-bit data bus, BE3 and BE0 valid for current cycle, processor uses 1X clock and V96SSC uses 2X clock

Table 2: BTYPE[1:0] Pin Decoding

BTYPE[1:0] CPU Mode Boot Address Description

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accommodated due to the V96SSC’s flexib ility. Two DRAM banks are provided. Each bank has its ow n progra mmable addre ss base and size. The

mapping of memory address lines to row and column addresses is also programmable for each bank. The twelve mixed address lines (MA[11:0]) are shared by both banks. Each bank may be independently enabled and/or write protected. Both banks share a common DRAM signal timing generator that controls all DRAM timing parameters. DRAM array width can be set to either 16-bit or 32-bits; the V96SSC controls lane steering logic in mixed width systems.

FPM, EDO, and Ramtron EDRAMs a re a natural fit for burst bus p rocessors such as i960 or PPC401Gx family. The V96SSC takes advantage of fast page mode accesses for every burst transaction, insuring the highest transfer rate possible. The V96SSC also supports extended burst peripherals, such as networking controllers, up to a maximum length of 64Byte data cycles.

The DRAM controller also includes page cache management logic. This logic detects subsequent burst accesses within the same DRAM page, and eliminates the RAS precharge time and row address cycles for these accesses. Removing these cycles can reduce the average wait-state profile for many applications. The “aggressiveness” of the caching algorithm is programmable, and page caching can be completely disabled. The page size is programmable from 512 to 81 92 bytes.

2.3 DMA Controller

Two independent DMA Channels are provided in the V96SSC. The DMA Controller generates fly-by cycles to transfer data directly from the DRAM to the selected peripheral, or vice-versa. Each cha nnel includes a req uest i nput (D REQx), an acknowledge output (DACKx), and an end-of-process outpu t (EOPx, accessible via the I/O Multiplexer). Each channel can also be assigned to a chip select/strobe channel to provide the necessary strobing signals to the DMA target/source peripheral.

The DMA buffer start and stop addresses ar e program mable, as i s the direc tion of tran sfer (read or write). Transfers may be initiated either via the DREQx pins or through software.

The DMA Controller’s programmable throttle count allows long transfers to be periodically interrupted to allow the processor access to the bus for code fetches, etc.

2.4 Serial Communications Unit (SCU)

The V96SSC’s Serial Communications Unit offers both synchronous and asynchronous modes. In asynchronous mod e, the Serial C ommuni cations U nit fun ctions a s an ind ustry standard , ful l duplex UART. Transmission and reception are double buffered to help prevent data overruns. Interrupts are generated on receiver buffer full, transmit buffer empty, buffer overrun error, and framing error.

In synchronous (SPI) mode, data is moved into, or out of, the SCU’s buffers on transitions of the serial clock output pin (SCLK). Data word length is programmable from 1 to 16 bits. An interrupt is generated upon completi on of a n SPI t ransfe r. SPI mode is ideal f or co nnecting to serial i nterf ace per ipher als such as A/D converters.

The clock referenc e for the Seri al Communica tions Unit can be either the independ ent baud rate generator or general purpose timer 1.

2.5 Chip Select/Strobe Unit

The Chip Select/Strobe Unit provides all the logic necessary to interface a wide ar ray of peripherals and memory components to the i960Sx/Jx processor. Address decoding, wait-state generation, chipselect, and read/wr ite strobe gen eration a re handled c ompletely b y the V96SSC; no glue log ic is

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V96SSC

needed. Eight output strobes/selects are available as output pins from the I/O Multiplexer. There are eight memory decode registers, each with the following options:

• Base address and size (minimum granularity 64K)

• Region data width

• Read/Write enable

Each memory decode register has an associated Region Timing Control register. This register assigns timings for synchronous mode strobes as well as for wait-state generation. The following timings are programmable f or each region:

• Strobe assert from bus cycle start

• Strobe de-assert from bus cycle start

• READY delay from cycle start (wait-states)

• Back-to-Back cycle delay

Each of the 8 chip select/strobe output pins is assigned to one of four programmable memory ranges. These strobe signals can be used as asynchronous chip-selects, or combined with the timing values for the region to create read and write strobes. Each strobe has the following programmable options:

• Address match register assignment

• Access type: read, write, both

• Timing: asynchronous, synchronous

• Sub-decode : finer granular ity decoding

The chip select/strobe unit is also tied to the DMA Controller. Each DMA channel can be assigned to a particular decode region and its associated timing.

2.6 General Purpose Timers (GPT)

Two identical 32-bit gene ral p urpo se t imer s a re in tegr ate d in the V9 6SSC. Thes e ti mer s may be us ed for a number of applications including: periodic interrupt generation, event counting, and pulse width modulation.

The timers decrement every clock cycle, from a 32-bit preload value until a terminal count of zero is reached. A maskable interrupt is generated on terminal count. The timer may be programmed to halt on terminal count, or to reload and restart counting.

Each timer has an external input (TIx) and external output pin (TOx). The TIx pin can be used as an edge or level sensitive start trigger. The TOx pin has the following modes:

• Latched low

• Short and long puls e low on terminal count

• Toggle on terminal count

• Pulse width modula tion

• One shot

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V96SSC

2.7 Watchdog and System Heartbeat Timers

The V96SSC’s watchdog timer is used to recover a system that has crashed due to a software upset. If the watchdog timer is not periodically reset by “trusted” system software, the V96SSC assumes that a software crash has occurred and resets the processor by driving the RSTOUT pin low. The V96SSC’s “system heartbeat” is a fixed-delay periodic interrupt to the processor that is used as a time reference by real-time operating systems.

2.8 Bus Watch Timer (BWT)

Additional system security is provided by the Bus Watch Timer. When enabled, the BWT monitors the READY pin (and, optionally, the PREADY pin) for every bus access initiated by an external master. If READY is not asserted within a programmable window (between 1 and 255 clocks), then the V96SSC will assert READY to end the cycle and generate an interrupt. For burst accesses, the BWT reloads its time-out count on each READY and returns to idle on BLAST.

2.9 Interrupt Control Unit

The Interrupt Control Unit manages inter rupts for all off the V96SSC’s on-chip inter rupts, as we ll as providing interrupt control for up to 8 external requests. Each pending request is latched in the Interrupt Status Register. The Interrupt Mask Register allows independent masking of all interrupt sources.

External interrupts may be routed to the Interrupt Control Unit via the I/O Multiplexer through the I/O port unit.

2.10 I/O Port Unit

The I/O Port Unit provides 8 independent single bit input or output ports. Each bit may be configured as an input port or an output port. As input ports, the unlatched inverted state of the associated pin is read from the Inp ut Port Register. In addition, th e i n pu t p or t bits are connect ed to the Interrupt C o ntr ol Unit to provide ex ter nal int erru pt re qu ests (IO[ 7:0 ] pins). When c onf igur ed as an o utput p ort, the s tate of the associated pin is set by writing to the Output Port Register.

The mapping of I/O Port bits to IOx pins is controlled via the I/O Multiplexer.

2.11 I/O Multiplexer

To allow the V96SSC to fit into a compa ct and economical 10 0-pin PQFP package , some nonessential I/O signals are multiplexed onto the IO[15:0] pins. Many internal signals have several options as to which IO pins they connect to. The multiplexing op ti on s for each IO pin are described in Table 4. Programming of the I /O Multiplexer is described in the

V96SSC User’s Manual.

2.12 Boot ROM Support

The V96SSC provi des s pecia l su ppor t for boot RO M de vices . Whe n an a ccess withi n the proc ess or’s boot range is detected on the A31, A[26:24] pins, the V96SSC outputs a latched low order address on the MA[11:0] pins (normally the muxed address li nes for DRAM) and asserts IOC0. T he V96SSC automatically detects boot ranges specific to each processor: 0x0000.0000 for the i960Sx, 0xFEFF.0000 for the i960Jx and 0xFFFF.0000 for PPC401Gx.

For i960Sx systems using 8-bit boot ROMs, the V96SSC will automatically steer the byte data to the proper half of the AD bus (i960Jx processors handle byte assembly internally).

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V96SSC

3.0 Pin Description and Pinout

Table 3 below lists the pin types found on the V96S SC. Table 4 describes the functi on of eac h pin on the V96SSC. Table 5 lists the pins by pin number. Figure 2 shows the pinout for the 100-pin EIAJ PQFP package an d Figure 3 shows the mechanical dime nsions of the package.

Table 3: Pin Types

Pin T ype Description

I Input pin

Schmidt trigger input pin

O Output pin with 4mA drive

Output pin with 12mA drive I/O I/O pin with 4mA output drive I

Schmidt trigger input with internal pull-up resistor

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V96SSC

Table 4: Signal Descriptions

Processor Inter face Signals

Signal T y pe R

Description

A31,A[26:16] I

High-order address lines from i960 processor. These signals are latched internally by t he V96SSC on the falling edge of ALE. Processor signals A[30:27] are optional and may be routed to the V96SSC through the I/O port pins (see belo w).

AD[15:0] I/O Z

Multiplexed address/data bus. For i960Jx based systems, the V96SSC only uses the lower 16-bits of the AD[31:0] bus.

ALE I

Address latch enable is connected to the i960 processor’s ALE pin. This signal is connected to the internal address latches.

ADS

Address status is connected to the AS pin on the i960Sx and to ADS on the i960Jx processors.

BE[1:0] I/O Z

Low order byte enables. The BE[1:0] pins are inputs for accesses from external masters; they become outputs when the V96SSC is the bus master. BE[3:2] are available through the I/O port pins for i960Jx systems (see below ).

BLAST I End of burst indic ation from i960 proces sor.

W/R I/O Z

Write/Read indication from the i960 processor. W/R is driven during V96SSC DMA operations to indicate the direction of the transfer.

HOLD O L Hold request from the V96SSC DMA Controller to the i960 processor.

HLDA I

Hold acknowledge from the i960 processor. This signal informs the V96SSC that it is now the local bus master.

INT O H Interrupt request output from the V96SSC interrupt controller.

READY I/O H

Data READY indication. The V96SSC returns READY to the i960 processor when data is read/w ritten to memory addresses under the V96SSC’s control. The V96SSC also monitors the READY signal for all bus accesses when the bus watch timer is enabled.

BTYPE[1:0] I

Bus transaction type. These signals are examined during the assert ion of AS, ADS or ALE to determine the type of external master initiating the bus cycle.

BTYPE[1:0] Master 00 i960SA/SB 01 PPC401Gx 10 i960JA/JD/JF (32-bit bus) 11 i960JA/JD/JF (16-bit bus)

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V96SSC

DMA and DRAM Controller Signals

Signal Type R Description

DREQ[1:0]

I DMA request inputs.

DACK[1:0] OHbDMA acknowledge outputs.

MA[11:0] O

XbDRAM multiplexed memory address lines.

RAS[1:0] O

HbDRAM row address strobes.

CAS[3:0] or

CAL[3:0]

Column address strobes. In EDRAM mode, the CAS[3:0] signals become CAL[3:0].

WE O

HbMemory write enable.

LE O

HbLatch enable.

OE[1:0] O

HbMemory output enables.

Multimode I/O Signals

Each of these pins has two or more alternate functions. Pin function is controlled via the I/O

multiplexer

Signal T y pe R Desc ription

IO0 I/O Z Functions: Input port 0, Output port 0, I/O strobe 0.

IO1 I/O Z

Functions: Input port 1, Output port 1, I/O strobe 1, serial clock for serial communications unit in SP I mode.

IO2 I/O Z

Functions: Input port 2, Output port 2, I/O strobe 2, serial data output (TxD in UART mode, SDO in SPI mode).

IO3 I/O Z

Functions: Input port 3, Output port 3, I/O strobe 3, serial data input (RxD in UART mode, SDI in SPI mode).

IO4 I/O Z

Functions: Input port 4, Output port 4, I/O strobe 4, refresh cycle indication from DRAM c ontroller.

IO5 I/O Z Functions: Input port 5, Output port 5, I/O strobe 5, PREADY

IO6 I/O Z

Functions: Input port 6, Output port 6, I/O strobe 6, general purpose timer 0 input.

IO7 I/O Z

Functions: Input port 7, Output port 7, I/O strobe 7, general purpose

timer 1 input. IO8 I/O Z Functions: Input port 0, Output port 0, general purpose timer 0 output. IO9 I/O Z Functions: Input port 1, Output port 1, general purpose timer 1 output.

Table 4: Signal Descriptions (cont’d)

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V96SSC

a. R indicates state during reset. b. Reset state is ’Z’ when 3.3V memory interface is selected via EN5V driven low. This feature can be used to

float the DRAM signals for board testing.

c. This signal was a no-connect prior to revision B1

Signal T ype R Description

BE2

/IO10 I/O Z

Functions: Input port 2, Output port 2, byte enable 2 input/output (for use

w/32-bit masters), end-of-process indication for DMA channel 0.

BE3/IO11 I/O Z

Functions: Input port 3, Output port 3, byte enable 3 input/output (for use

w/32-bit masters), end-of-process indication for DMA channel 1.

A27/IO12 I/O Z

Functions: Input port 4, Output port 4, A27 input pin, general purpose

timer 0 output.

A28/IO13 I/O Z

Functions: Input port 5, Output port 5, A28 input pin, general purpose

timer 1 output.

A29/IO14 I/O Z

Functions: Input port 6, Output port 6, A29 input pin, end-of-process

indication for DMA channel 0.

A30/IO15 I/O Z

Functions: Input port 7, Output port 7, A30 input pin, end-of-process

indication for DMA channel 1.

Clock, Reset and Configuration Signals

Signal Type R Description

CLK2 I

2X clock input (in i960Jx/PPC401Gx systems, this signal is 2X the

processor frequency).

RESET

RESET input.

RSTOUT O L RESET output from watchdog timer.

EN5V

Selects 5V (driven high) or 3.3V (driven low) DRAM memory interface .

An internal weak pul l - up is pr ovi de d for bac k w ar d com patibility.

Power and Ground Signals

Signal Type R Description

POWER leads for CPU I/O and internal core logic. Connect to a 5V

board plane.

VCC3-

POWER leads for DRAM interface signals. Connect to either a 5V or

3.3V board plane as determined by EN5V (5V only prior to revision B1).

GND - GROUND leads intended for exte rnal co nn ecti on to a G ND boa rd pl an e.

Table 4: Signal Descriptions (cont’d)

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V96SSC

Table 5: Pin Assignments

PIN # Signal PIN # Signal PIN # Signal PIN # Signal

READY 26 BE0 51 A27/I O12 76 MA6 2 ALE 27 BE1 52 BE3/IO11 77 MA7 3 A22 28 AD0 53 BE2/IO10 78 RAS1 4 A21 29 V

54 IO9 79 CAS1 5 ADS 30 GND 55 IO8 80 VCC3 6 RESET 31 AD 1 56 IO7 81 GND3 7 DREQ0 32 AD2 57 IO6 82 MA8 8 DREQ1 33 AD3 58 IO5 83 MA9 9 BTYPE0 34 AD4 59 IO4 84 MA10

10 BTYPE1 35 AD5 60 IO3 85 WE 11 BLAS T 36 AD6 61 IO2 86 OE0 12 V

37 AD7 62 IO1 87 CAS2 13 GND 38 AD8 63 IO0 88 LE 14 W/R 39 AD 9 64 VCC3 89 VCC3 15 HOLD 40 AD10 65 GND3 90 GND3 16 A20 41 AD11 66 MA0 91 MA11 17 A19 42 AD12 67 MA1 92 CAS3 18 HLDA 43 AD13 68 MA2 93 OE1 19 INT 44 AD14 69 MA3 94 DACK0 20 A18 45 AD15 70 RAS0 95 DACK 1 21 A17 46 V

71 CAS0 96 A23 22 A16 47 GND 72 VCC3 97 A24 23 RSTOUT 48 A30/IO15 73 GND3 98 A25 24 CLK2 49 A29/IO14 74 MA4 99 A26 25 EN5V 50 A28/I O13 75 MA5 100 A3 1

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V96SSC

Figure 2: Pinout for 100-pin EIAJ PQFP (top view)

ALE

READY

RESET

ADS

A21

DREQ1

DREQ0

Vcc

BTYPE1

BTYPE0

W/R

GND

A19

A20

HOLD

INT

HLDA

A16

A17

A18

CLK2

RSTOUT

BE1

BE0

EN5V

Vcc

AD0

GND

MA10

MA9

MA8

OE0

Vcc3LECAS2

MA11

GND

DACK0

OE1

CAS3

A23

DACK1

A26

A25

A24

A31

CAS1

Vcc3

MA6

MA7

RAS1

MA4

MA5

CAS0

Vcc3

GND

MA3

RAS0

MA0

MA1

MA2

Vcc3

GND

IO2

IO1

IO0

IO4

IO3

IO7

IO6

IO5

IO9

IO8

A27/IO12

BE3/IO11

BE2/IO10

A28/IO13

GND

A30/IO15

A29/IO14

AD15

Vcc

AD12

AD13

AD14

AD10

AD11

AD7

AD8

AD9

AD5

AD6

AD2

AD3

AD4

AD1

100

A22

BLAST

V96SSC

(TOP VIEW)

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V96SSC

Figure 3: 100-pin EIAJ PQFP mechanical details

Unit of Measurement = millimeters

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V96SSC

4.0 DC Specifications

The following DC specificat ions are based on B1 stepping silicon.

Table 6: Absolute Maximum Ratings

Symbol Parameter Value Units

Supply voltage -0.3 to +7.0 V

DC input voltage -0.3 to VCC+0.3 V

DC source or sink current -50 to +50 mA

STG

Storage temperature range -65 to 150 °C

Table 7: Guaranteed Operating Conditions

Symbol Parameter Value Units

Supply voltage 4.5 to 5.5 V

Ambient temperature range -40 to 85 °C

Table 8: DC Operating Specifications

Symbol Description Conditions Min Max Units

Low level input voltage VCC = 4.75V 0.8 V

High level input voltage VCC = 5.25V 2.0 V

Low level input cur r ent VIN=GND, VIN=5.25V -10

High level input current VIN=VIN=5.25V 10

OL4

Low level output voltage for 4mA outputs and I/O pins

= 4mA 0.4 V

OH4

High level output voltage for 4mA outputs and I/O pins

= -4mA 3.7 V

OL12

Low level output voltage for 12mA outputs and I/O pins

= 12mA 0.4 V

OH12

High level output voltage for 12mA outputs and I/O pins

= -12mA 3 .7 V

OZL

Low level float input leakage V

= GND -10

OZH

High level float input leakage V

= V

ICC (max) Maximum supply current

VCC = 5.5V

Frequency = 20MHz

71 mA

(typ) Typical supply current

VCC = 5.0V

Frequency = 20MHz

65 mA

Input and output capac i tance 20 pF

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V96SSC

5.0 AC Specifications

The following AC specifications are based on A-0 stepping silicon.

Figure 4: Clock and Synchronous Signals

Figure 5: ALE Signal

Table 9: AC Test Conditions

Symbol Parameter Limits Units

Supply voltage 4.75 to 5.25 V

Input low and high voltages 0.8 and 2.4 V

OUT

Capacitive load on output and I/O pins 50 pF

Table 10: Capacitive Derating for Output and I/O Pins

Output Drive Limit Derating

4mA 0.11ns/pF for loads > 50pF

12mA 0.04ns/pF for loads > 50pF

CLK2

CLK

W/R#, HLDA, DREQ[1:0]#

A31,A[26:16], BE[1:0]#, AS#

BLAST#, BTYPE[1:0]

RSTOUT#, INT#

HOLD, DACK[1:0]#

ALE

AD[15:0]

ADDRESS

ALE

ASU

Page 17

V96SSC

Notes:

1. t

is for signals RSTOUT, HOLD, DACKx, and INT.

Figure 6: Internal Register Read/Write Waveforms

Table 11: Clock, ALE, Synchronous Inputs and Outputs

33 MHz

# Symbol Description Notes Min Max Units

CLK2 period 15 ns 2tCHCLK2 high time 6 ns 3tCLCLK2 low time 6 ns 4tSUSynchronous input setup 10 ns 5t

Synchronous input hold 3 ns 6tCOCLK2 to synchronous output delay 1 12 ns 7t

ALE

ALE pulse width tC-7 ns 8t

ASU

Address setup to ALE falling 3 ns 9tAHAddress hold from ALE falling 1 ns

CLK2

CLK

AD[15:0]

W/R

READY

ADS

A31,A[26:23]

BLAST

ADDR DATA IN ADDR DATA OUT

IOC

OPORT

ADH

AD0

ADV

RZL

RLH

RHZ

OCHL

ADDRESS VALID ADDRESS VALID

Page 18

V96SSC

Notes:

1. For V96SSC internal register read.

2. Delays are measured from address valid and ALE asserted.

3. In IOC mode, delays are measured from CLK2 when CLK is high and ADS

is asserted. In OPORT mode, de-

lays are measured from CLK2 when CLK is high during Td cycle.

Figure 7: Memory Timing Waveforms

Table 12: Timing Relationships for Internal Register Read/Write

33 MHz

Sym-

bol

Descriptio n Notes Min Max Units

ADO

CLK2 to Data Output driving delay 1 4 12 ns

ADV

CLK2+ADS to internal register data valid, read access time 1 49 ns

ADH

Data hold after CLK2 1 3 ns 4tPDIO asynchronous chip-select output delay 2 19 ns 5tOCIO synchronous strobe output delay from CLK2 3 18 ns 6t

RZL

READY float to driving low from CLK2 3 12 ns 7t

RLH

READY low to high delay from CLK2 11 ns 8t

RHZ

READY high to float delay from CLK2 12 ns 9t

RFV

REFRESH (synchronous) output delay 14 ns

ROW ADDR

CLK2

CLK

AD[15:0]

RAS

MA[11:0]

A31,A[26:23]

CAS

ROW ADDR COLCOL

ADDR D In ADDR DATA OUT

ARA

DRAH

RAH

DCAH

LELH1

LELH2

CAH

CAV

ADDRESS VALID ADDRESS VALID

LEHL1

Page 19

V96SSC

Table 13: Memory Interface Signals

33 MHz

Sym-

bol

Description Notes Min Max Units

ARA

Address inpu t valid to row address valid on MA[11:0] 1 13 ns

RAH

Row address hold after CLK2 3 ns

CAV

CLK2 to column address valid 1 12 ns

CAH

Column address hold after CLK2 or CLK2 1,2 4 ns

BCAH

Column address hold after CLK2 or CLK2 during burst operation

1,2 4 ns

BCAV

CLK2 or CLK2 to column address valid during burst operation

1,2 14 ns

DRAH

DRAM row address hold 3 tM+1 ns

DCAH

DRAM column address hold 4 tN+1 ns

RSHL

CLK2 to RAS asserted delay 1 9 ns

10 t

RSLH

CLK2 to RAS de-asserted delay 1 9 ns

11 t

CHL1

CLK2 to CAS asserted delay 1 1 1 ns

12 t

CLH1

CLK2 to CAS de-asserted delay 1 10 ns

13 t

CHL2

CLK2 to CAS asserted delay 1,5 10 ns

14 t

CLH2

CLK2 to CAS de-asserted delay 1,6 10 ns

15 t

OEHL

CLK2 to OE asserted delay 1 10 ns

16 t

OELH

CLK2 to OE de-asserted delay 1 9 ns

17 t

WEHL

CLK2 to WE asserted delay 1 10 ns

18 t

WELH

CLK2 to WE de-asserted delay 1 10 ns

19 t

LEHL1

CAS asserted to LE asserted delay (read) 1 1 ns

20 t

LELH1

CAS de-asserted to LE de-asserted (read) 1 1 ns

21 t

LEHL2

CAS asserted to LE de-asserted delay (write) 1,7 1 ns

22 t

LELH2

CAS de-asserted to LE asserted (write) 1,7 1 ns

Page 20

V96SSC

Note:

1. The delay is from CPU Address valid or ALE if it comes first. Derate given delays by 0.058 ns per pF of load in excess of 50pF.

2. Relative to CLK2

only when T_CACA_RD or T_CACA_WR equals 0.

3. tM = (1 CLK2 period) * (T_RACA+1).

4. tN = (1/2 CLK2 period) * (T_CACA_RD + 1) for Read or (1/2 CLK2 period)*(T_CACA_WR+1) for 0-wait states write.

5. For Read Mode 2 and Write Mode 1 only.

6. For Write Mode 1 only.

7. For CAS Write Mode 0 and 1.

6.0 Revision History

USA:

2348G Walsh Ave.

Santa Clara CA 95051

Phone: (408)988-1050 Fax: (408)988-2601

Toll Free: (800)488-8410 (Canada and U.S. only)

World Wide Web: htt

://www.vcubed.com

Table 14: Revision History

Revision

Number

Date Comments and Changes

2.3 11/97 First release of RevB1 data sheet.

2.2 10/96 Data Book revision.

2.1 08/96 Updated timing specification.

2.01 11/95

Fixed incorrect polarity on some ALE and RESOUT

signals. Fixed W/R

description.

2.0 11/95

Final Data Sheet. All sp ecifications guarantee d f rom actual silicon. DC input levels changed to TTL compatible. Removed 16MHz and 20MHz timing specification.

1.2 03/95

First released version of the data sheet. Some changes to AC and DC specifications and to waveforms. All future changes to the data sheet will be documented in detail in this section.

1.0 01/95

First pre-silicon revision of preliminary data sheet. Sent only to a limited number of customers.

Datasheet V96SSC-33LP Datasheet (V3 Semiconductor)

Specifications and Main Features

Frequently Asked Questions

User Manual