Datasheet V827332U04SXTG-B1, V827332U04SXTG-B0, V827332U04SXTG-A1 Datasheet (Mosel Vitelic)

MOSEL VITELIC

1

V827332U04S

2.5 VOLT 32M x 72 HIGH PERFORMANCE
REGISTERED ECC DDR SDRAM MODULE

PRELIMINARY

V827332U04S Rev. 1.2 March 2002

Features

■ 184 Pin Registered 33,554,432 x 72 bit
Organization DDR SDRAM Modules

■ Utilizes High Performance 16M x 8 DDR
SDRAM in TSOPII-66 Packages

■ Single +2.5V (± 0.2V) Power Supply

■ Programmable CAS

Latency, Burst Length, and

Wrap Sequence (Sequential & Interleave)

■ Auto Refresh (CBR) and Self Refresh

■ All Inputs, Outputs are SSTL-2 Compatible

■ 4096 Refresh Cycles every 64 ms

■ Serial Presence Detect (SPD)

■ DDR SDRAM Performance

Description

The V827332U04S memory module is organized
33,554,432 x 72 bits in a 184 pin memory module.
The 32M x 72 memory module uses 18 Mosel­Vitelic 16M x 8 DDR SDRAM. The x72 modules are
ideal for use in high performance computer systems
where increased memory den sity and fast access
times are required.

Component Used -7 -75 -8 Units

tCKClock Frequency

(max.)

143

(PC266A)

133

(PC266B)

125

(PC200)

MHz

t

AC

Cloc k Access Time
CAS

Latenc y = 2.5

77.58ns

Module Speed

A1 PC1600 (100MHz @ CL2 )
B0 PC2100 B (133MHz @ CL2.5)
B1 PC2100 A (133MHz @ CL2)

16Mx8

16Mx8

16Mx8

16Mx8

16Mx8

16Mx8

16Mx8

16Mx8

16Mx8

Reg

Reg

PLL

2

MOSEL VITELIC

V827332U04S

V827332U04S Rev. 1.2 March 2002

Part Number Information

V 8 2 73 32 U 0 4 S X T G - XX

DDRSDRAM

2.5V
WIDTH

DEPTH

184 PIN Registered
DIMM X8 COMPONENT

REFRESH

RATE 4K

4 BANKS

STTL

COMPONENT

REV LEVEL

COMPONENT

PACKAGE, T = TSOP

LEAD FINISH

G = GOLD

SPEED

A1 (100MHZ@CL2)

MOSEL VITELIC

MANUFACTURED

B0 (133MHZ@CL2.5)
B1 (133MHZ@CL2)

MOSEL VITELIC

V827332U04S

3

V827332U04S Rev. 1.2 March 2002

Block Diagram

DQ4
DQ5
DQ6
DQ7

DQ0
DQ1
DQ2
DQ3

DM
I/O 7
I/O 6
I/O 1
I/O 0

D0

DM0/DQS9

DM

D9

I/O 5
I/O 4
I/O 3
I/O 2

I/O 0
I/O 1
I/O 6

I/O 7
I/O 2
I/O 3
I/O 4
I/O 5

DQ12
DQ13
DQ14

DQ8
DQ9
DQ10
DQ11

DM
I/O 7
I/O 6
I/O 1
I/O 0

D1

DM

D10

I/O 5
I/O 4
I/O 3

I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4

DM1/DQS10

DQ20
DQ21
DQ22
DQ23

DQ16
DQ17
DQ18
DQ19

DM
I/O 7
I/O 6
I/O 1
I/O 0

D2

DM

D11

I/O 5
I/O 4
I/O 3
I/O 2

I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5

DM2/DQS11

DQ28
DQ29
DQ30
DQ31

DQ24
DQ25
DQ26
DQ27

DM
I/O 7
I/O 6
I/O 1
I/O 0

D3

DM

D12

I/O 5
I/O 4
I/O 3
I/O 2

I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5

DM3/DQS12

DQ36
DQ37
DQ38
DQ39

DQ32
DQ33
DQ34
DQ35

DM
I/O 7
I/O 6
I/O 1
I/O 0

D4

DM4/DQS13

DM

D13

I/O 5
I/O 4
I/O 3
I/O 2

I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5

DQ44
DQ45
DQ46
DQ47

DQ40
DQ41
DQ42
DQ43

DM
I/O 7
I/O 6
I/O 1
I/O 0

D5

DM

D14

I/O 5
I/O 4
I/O 3
I/O 2

I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5

DM5/DQS14

DQ52
DQ53
DQ54
DQ55

DQ48
DQ49
DQ50
DQ51

DM
I/O 7
I/O 6
I/O 1
I/O 0

D6

DM

D15

I/O 5
I/O 4
I/O 3
I/O 2

I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5

DQ60
DQ61
DQ62
DQ63

DQ56
DQ57
DQ58
DQ59

DM
I/O 7
I/O 6
I/O 1
I/O 0

D7

DM

D16

I/O 5
I/O 4
I/O 3
I/O 2

I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5

DM7/DQS16

PCK

RS0

RS

1

CS CS

CS CS

CS

CS

CS CS

CS CS

CS CS

CS CS

CS CS

DQS0

DQS

DQS4

DQS1

DQS5

DQS

DQS

DQS2

DQS

DQS

DQS3

DQS

DQS

DM6/DQS15

DQS6

DQS7

DQ15 I/O 2

I/O 5

CB4
CB5
CB6
CB7

CB0
CB1
CB2
CB3

DM
I/O 7
I/O 6
I/O 1
I/O 0

D8

DM

D17

I/O 5
I/O 4
I/O 3
I/O 2

I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5

CS

CS

DQS8
DM8

DQS

DQS

DQS

DQS

DQSDQS

DQS

DQS

DQS

DQS

DQS

Notes:

1. DQ-to-I/O wiring is shown as recom-
mended but may be changed.

2. DQ/DQS/DM/CKE/S relationships must
be maintained as shown.

3. DQ, DQS, DM resistors: 22 Ohms.

4. VDDID strap connections
(for memory device VDD, VDDQ):
STRAP OUT (OPEN): VDD = VDDQ
STRAP IN (VSS): VDD ≠VDDQ.

RAS
CAS
CKE0
CKE1

CS1
BA0-BAN
A0-A11

CS0

WE

PCK

RESET

RCS1

RCS0

RBA0 - RBAn
RA0 - RA11
RRAS
RCAS
RCKE0

RWE

RCKE1

BA0 -BAn : SDRAMs DQ0 - D17

A0 -An : SDRAMs D0 - D17

RAS

: SDRAMs D0 - D17

CAS

: SDRAMs DQ0 - D17

CKE : SDRAMs D0 - D8

CKE : SDRAMs D9 - D17

WE

: SDRAMs D0 - D17

R

E

G

I
S
T
E

R

PLL*

CK0,CK0
* Wire per Clock Loading table/wiring Diagrams

A0

Serial PD

A1

A2

SA0 SA1

SA2

SCL

SDA

WP

V

SS

D0 - D17

D0 - D17

V

DD/VDDQ

D0 - D17

D0 - D17

VREF

V

DDID

Strap: see Note 4

V

DDSPD

SPD

4

MOSEL VITELIC

V827332U04S

V827332U04S Rev. 1.2 March 2002

Pin Configurations (Front Side/Back Side)

Pin Front Pin Front Pin Front Pin Back Pin Back Pin Back

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31

VREF

DQ0
VSS
DQ1

DQS0

DQ2
VDD
DQ3

NC

NC
VSS
DQ8
DQ9

DQS1

VDDQ

CK1
CK1
VSS

DQ10
DQ11
CKE0

VDDQ

DQ16
DQ17
DQS2

VSS

A9

DQ18

A7

VDDQ

DQ19

32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52

53
54
55
56
57
58
59
60
61

A5

DQ24

VSS
DQ25
DQS3

A4

VDD
DQ26
DQ27

A2

Vss

A1
CB0*
CB1*

VDD

DQS8*

A0
CB2*

VSS

CB3*

BA1

Key

DQ32

VDDQ

DQ33

DQS4

DQ34

VSS

BA0
DQ35
DQ40

62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92

VDDQ

WE

DQ41

CAS
VSS

DQS5

DQ42
DQ43

VDD

NC
DQ48
DQ49

VSS
CK2

CK2
VDDQ
DQS6

DQ50
DQ51

VSS

VDDID

DQ56
DQ57

VDD
DQS7

DQ58
DQ59

VSS

NC
SDA
SCL

93
94
95
96
97
98

99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123

VSS
DQ4
DQ5

VDDQ

DM0
DQ6
DQ7
VSS

NC
NC

A13*

VDDQ

DQ12
DQ13

DM1

VDD
DQ14
DQ15
CKE1

VDDQ

BA2*

DQ20

A12*

VSS

DQ21

A11
DM2
VDD

DQ22

A8

DQ23

124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144

145
146
147
148
149
150
151
152
153

VSS

A6
DQ28
DQ29

VDDQ

DM3

A3
DQ30

VSS

DQ31

CB4*
CB5*

VDDQ

CK0*
CK0

*

VSS

DM8*

A10

CB6*

VDDQ

CB7*

key

VSS
DQ36
DQ37

VDD

DM4
DQ38
DQ39

VSS
DQ44

154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184

RAS

DQ45

VDDQ

CS0
CS1
DM5

VSS
DQ46
DQ47

NC

VDDQ

DQ52
DQ53

NC
VDD
DM6

DQ54
DQ55

VDDQ

NC

DQ60
DQ61

VSS
DM7

DQ62
DQ63

VDDQ

SA0
SA1
SA2

VDDSPD

Notes:

* These pins ar e not used in this module.

Pin Names

Pin Pin Description

CK1, CK1, CK2, CK2 Differential Clock Inputs
CS0

Chip Select Input
CKE0 Clock Enable Input
RAS

, CAS, WE Commend Sets Inputs
A0 ~ A11 Address
BA0, BA1 Bank Address
DQ0~DQ63 Data Inputs/Outputs
DQS0~DQS7 Data Strobe Inputs/Outputs
DM0~DM7 Data-in Mask

Key Key

VDD Power Supply
VDDQ DQs Power Supply
VSS Ground
VREF Reference Power Supply
VDDSPD Power Supply for SPD
SA0~SA2 E

2

PROM Address Inputs

SCL E

2

PROM Clock

SDA E

2

PROM Data I/O
VDDID VDD Identification Flag
DU Do not Use
NC No Connection

Pin Pin Description

MOSEL VITELIC

V827332U04S

5

V827332U04S Rev. 1.2 March 2002

Serial Pr esence Detect Inf o rm ation

Bin Sort:
A1 (PC1600 @ CL2)
B0 (PC2100B @ CL2.5)
B1 (PC2100A @ CL2)

Byte # Function described

Function Supported Hex value

A1 B0 B1 A1 B0 B1

0 Defines # of Bytes written into serial memory at module manufacturer 128bytes 80h
1 Total # of Bytes of SPD memory device 256bytes 08h
2 Fundamental memory type SDRAM DDR 07h
3 # of row address o n this assembly 12 0Ch
4 # of colu mn address on this assembly 10 0Ah
5 # of module Rows on this assembly 2 Bank 02h
6 Data width of this assembly 72 bits 48h

7 .........Data width of this assembly - 00h

8 VDD Q and interfac e standa rd of t hi s as s em bl y SSTL 2.5 V 04h

9 DDR SDRAM cycle time at CAS Latency =2.5 8ns 7.5ns 7ns 80h 75h 70h
10 DDR SDRAM Access time from clock at CL=2.5 ±0.8ns ±0.75ns ±0.70ns 80h 75h 70h
11 DIMM configuration type(Non-parity, Parity, ECC) Non-parity, ECC 02h
12 Refresh rate & type 15.6us & Self refresh 80h
13 Primary DDR SDRAM width x8 08h
14 Error checking DDR SDRAM data width x8 08h
15 Minimum clock delay for back-to-back random column

address

t

CCD

=1CLK 01h

16 DDR SDRAM device attributes : Burst lengths supported 2,4,8 0Eh
17 DDR SDRAM device attributes : # of banks on each DDR SDRAM 4 banks 04h
18 DDR SDRAM device attributes : CAS Latency supported 2,2.5 0Ch
19 DDR SDRAM device attributes : CS Latency 0CLK 01h
20 DDR SDRAM device attributes : WE Latency 1CLK 02h
21 DDR SDRAM module attributes Registered address&

control inputs and On-card

DLL

26h

22 DDR SDRAM device attributes : General +/-0.2V voltage tolerance 00h
23 DDR SDRAM cycle time at CL =2 10ns 10ns 7.5ns A0h A0h 75h
24 DDR SDRAM Access time from clock at CL =2 ±0.8ns ±0.75ns ±0.75ns 80h 75h 75h
25 DDR SDRAM cycle time at CL =1.5 - - - 00h
26 DDR SDRAM Access time from clock at CL =1.5 - - - 00h
27 Minimum row precharge time (=t

RP

) 20ns 20ns 18ns 50h 50h 48h

28 Minim u m row ac tiv a te to row ac tiv e dela y (=t

RRD

) 15ns 15ns 14ns 3Ch 3Ch 38h

6

MOSEL VITELIC

V827332U04S

V827332U04S Rev. 1.2 March 2002

29 Minimum RAS to CAS delay(=t

RCD

) 20ns 20ns 18ns 50h 50h 48h

30 Minimum active to precharge time(=t

RAS

) 50ns 45ns 45ns 32h 2Dh 2Dh
31 Module ROW density 128MB 20h
32 Command and addr ess signal input setup time 1.1ns 0.9ns 0.9ns B0h 90h 90h
33 Command and addr ess signal input hold time 1.1ns 0.9ns 0.9ns B0h 90h 90h
34 Data signal input setup time 0.6ns 0.5ns 0.5ns 60h 50h 50h
35 Data signal input hold time 0.6ns 0.5ns 0.5ns 60h 50h 50h

36-40 Superset information (may be used in future) - 00h

41 SDRAM device minimum active to active/auto-refresh time

(=t

RC

)

70ns 65ns 60ns 46h 41h 3Ch

42 SDRAM device minimum active to autorefresh to active/auto-refresh

time (=t

RFC

)

80ns 75ns 67ns 50h 4Bh 43h

43 SDRAM device maximum device cycle time (=t

CK MAX

) 12ns 12ns 12ns 30h 30h 30h

44 SDRAM device maximum skew between DQS and DQ signals

(=t

DQSQ

)

0.6ns 0.5ns 0.5ns 3Ch 32h 32h

45 SDRAM device maximum read datahold skew factor (=t

QHS

) 1ns 0.75ns 0.75ns A0h 75h 75h

46-61 Superset information (may be used in future) - 00h

62 SPD data revision code Initial release 00h
63 Checksum for Bytes 0 ~ 62 - DDh 23h C2h
64 Manufacturer J EDEC ID code Mosel Vitelic 40h

65 -71 ....... Manufacturer JEDEC ID code Mosel Vitelic 00h

72 Manufacturing location 01h

73-90 Module part number (ASCII) V827332U04S

91 Manufacturer revison code (For PCB) 0 00
92 Manufacturer revison code (For component) 0 00
93 Ma nu fac turing da te ( We ek ) - ­94 Ma nu fac turing da te ( Ye ar ) - -

95~98 Assembly serial # - -

99~127 Manufacturer specific data (may be used in future) Undefined 00h

128~255 Open for customer use Undefined 00h

Byte # Function described

Function Supported Hex value

A1 B0 B1 A1 B0 B1

Serial Pr esence Detect Inf o rm ation (con t. )

MOSEL VITELIC

V827332U04S

7

V827332U04S Rev. 1.2 March 2002

DC Operating Conditions

(TA = 0 to 70°C, Voltage referenced to VSS = 0V)

Notes: 1. V

DDQ

must not exceed the level of VDD.

2. V

IL

(min) is acceptable -1.5V AC pulse width with ð 5ns of dura tion.

3. The value of V

REF

is approximately equal to 0.5V

DDQ

.

AC Operating Conditions

(TA = 0 to 70 °C, Voltage referenced to VSS = 0V)

Notes: 1. VID is the magnitude of the difference between the input level on CK and the input on CK.

2. The value of VIX is expected to equal 0.5*V

DDQ

of the tr ansmitting device and must track variations in the DC level of the

same.

Parameter Symbol Min Typ. Max Unit Note

Power Supply Voltage V

DD

2.3 2.5 2.7 V

Power Supply Voltage V

DDQ

2.3 2.5 2.7 V 1

Input High Voltage V

IH

V

REF

+ 0.15 - V

DDQ

+ 0.3 V

Input Low Voltage V

IL

-0.3 - V

REF

- 0.15 V 2

I/O Termination Voltage V

TT

V

REF

- 0.04 V

REF

V

REF

+ 0.04 V

Refere nce Voltage V

REF

1.15 1.25 1.35 V 3

Input Le ak ag e C urr e nt I

I

-2 - 2 µA

Output Le ak ag e C urr e nt IO

z

-5 - 5 µA

Output High Current (V

OUT

= 1.95V) IO

H

-16.8 - - mA

Output Low Current (V

OUT

= 0.35V) IO

L

16.8 - - mA

Parameter Symbol Min Max Unit Note

Input H ig h (Logic 1) Voltage, DQ , DQS an d D M si gn al s V

IH(AC)

V

REF

+ 0.31 V

Input Low (Logic 0) Voltage, DQ, DQS and DM signals V

IL(AC)

V

REF

- 0.31 V

Input Differential Voltage, CK and CK

inputs V

ID(AC)

0.7 V

DDQ

+ 0.6 V 1

Input Cr os s in g P oin t Voltage, CK an d C K

inputs V

IX(AC)

0.5*V

DDQ-0.2

0.5*V

DDQ+0.2

V2

8

MOSEL VITELIC

V827332U04S

V827332U04S Rev. 1.2 March 2002

AC Operating Test Conditions (T

A

= 0 to 70°C, Voltage referenced to VSS = 0V)

Input/Output Capacitance

(V

DD

= 2.5V, V

DDQ

= 2.5V, TA = 25°C, f = 1MHz)

Parameter Value Unit

Refere nce Voltage V

DDQ

x 0.5 V

Termination Voltage V

DDQ

x 0.5 V

AC Input High Level Voltage (V

IH

, min) V

REF

+ 0.31 V

AC Input Low Level Voltage (V

IL

, max) V

REF

- 0.31 V

Input Timing Measurement Reference Level Voltage V

REF

V

Outpu t Tim in g Measur em e nt R ef er e nc e Le vel Voltag e V

TT

V
Input Signal maximum peak swing 1.5 V
Input minimum Signal Slew Rate 1 V/ns
Termination Resistor (R

T

) 50 ¾

Series Resistor (R

S

) 25 ¾

Output Load Capacitance for Access Time Measurement (C

L

) 30 pF

Parameter Symbol Min Max Unit

Input ca pacita nc e (A0 ~ A11, BA0 ~ BA1, RAS, CAS, WE) CIN1 60 75 pF
Input ca pacita nc e (C K E

0

) CIN

2

40 48 pF

Input ca pacita nc e (C S

0

) CIN

3

40 48 pF

Input ca pacita nc e (C LK

1

, CLK2) CIN

4

30 32 pF

Data & DQS input/output capacitance (DQ

0

~DQ63) C

OUT

10 12 pF

Input capaci ta nc e ( DM0~DM8 ) CIN

5

10 12 pF

Output Load Circuit (SSTL_2)

O

utput

Z0=50Ω

C

LOAD=30pF

V

REF

=0.5*VDD

Q

RT=50Ω

Vtt=0.5*VDDQ

MOSEL VITELIC

V827332U04S

9

V827332U04S Rev. 1.2 March 2002

DDR SDRAM IDD SPEC TABLE

* Module IDD was calcul at e d on th e ba si s of compo ne nt IDD and can be differentl y me as ured acc ording to DQ load ing cap.

Detailed test conditions for DDR SDRAM IDD1 & IDD

IDD1 : Operating current: One bank operation

1. Typical Case : Vdd = 2.5V, T=25’ C

2. Worst Case : Vdd = 2.7V, T= 10’ C

3. Only one bank is accessed with tRC(min), Burst Mode, Address and Control inputs on NOP edge are changing once
per clock cycle. lout = 0mA

4. Timing patterns

- DDR200(100Mhz, CL=2) : tCK = 10ns, CL2, BL=4, tRCD = 2*tCK, tRA S = 5*tCK
Read : A0 N R0 N N P0 N A0 N - repeat the same timing with random addres s changing
*50% of data changing at ever y burst

- DDR266B(133Mhz, CL=2.5) : tCK = 7.5ns, CL=2.5, BL=4, t RCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address chang ing
*50% of data changing at ever y burst

- DDR266A (133Mhz, CL=2) : tCK = 7.5ns, CL=2, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address chang ing
*50% of data changing at ever y burst

Legend : A=Activate, R=Read, W=Write, P=Precharge, N=NOP

Symbol

A1(PC1600@CL=2) B0(PC2100B@CL=2.5) B1(PC2100A@CL=2)

Unit

Typical Worst Typical Worst Typical Worst

IDD0 1450 1440 1350 1440 1080 1170 mA

IDD1 1650 1710 1575 1710 1280 1395 mA
IDD2P 750 720 675 720 540 585 mA
IDD2F 895 945 655 945 720 765 mA

IDD2Q 830 810 765 810 630 675 mA
IDD3P 980 765 720 765 585 630 mA
IDD3N 900 990 900 990 720 810 mA
IDD4R 1980 2250 1980 2250 1620 1845 mA

IDD4W 2115 2385 2115 2385 1710 1890 mA

IDD5 2115 2385 2115 2385 1710 1890 mA

IDD6 Normal 36 36 36 36 36 36 mA

Low power 18 18 18 18 18 18 mA

IDD7 3375 3825 3375 3825 2745 3150 mA

10

MOSEL VITELIC

V827332U04S

V827332U04S Rev. 1.2 March 2002

AC Characteristics (AC operating conditions unless otherwise noted)

Parameter Symbol

(PC1600) (PC2100B) (PC2100A)

Unit NoteMin Max Min Max Min Max

Row Cycle Time tRC 60 - 65 - 70 - ns
Auto Refresh Row Cycle Time t

RFC

67 - 75 - 80 - ns

Row Active Time t

RAS

45 120K 48 120K 50 120K ns

Row Address to Column Address Delay t

RCD

18 - 20 - 20 - ns

Row Active to Row Active Delay t

RRD

14 - 15 - 15 - ns

Column Address to Column Address Delay t

CCD

1 - 1 - 1 - CLK

Row Precharge Time t

RP

18 - 20 - 20 - ns

Write Recovery Time t

WR

15 - 15 - 15 - ns

Last Dat a-In to Read Command t

DRL

1 - 1 - 1 - CLK

Auto Precharge Write Recovery + Precharge Time t

DAL

35 - 35 - 35 - ns

System Clock Cycle Time CAS

Latency = 2.5 t

CK

7 12 7.5 12 8 12 ns

CAS

Latency = 2 7.5 12 10 12 10 12 ns

Clock High Level Width t

CH

0.45 0.55 0.45 0.55 0.45 0.55 CLK

Clock Low Level Width t

CL

0.45 0.55 0.45 0.55 0.45 0.55 CLK

Data-Out edge to Clock edge Skew t

AC

-0.75 0.75 -0.75 0.75 -0.8 0.8 ns

DQS-Out edge to Clock edge Skew t

DQSCK

-0.75 0.75 -0.75 0.75 -0.8 0.8 ns

DQS-Out edge to Data-Out edge Skew t

DQSQ

- 0.5 - 0.5 - 0.6 ns

Data-Out hold time from DQS t

QH

t

HPmin

-0.75ns

- t

HPmin

-0.75ns

- t

HPmin

-0.75ns

- ns 1

Clock Half Period t

HP

t

CH/L

min

- t

CH/L

min

- t

CH/L

min

- ns 1

Input Setup Time (fast slew rate) t

IS

0.9 - 0.9 - 1.1 - ns 2,3,5,6

Input Hold Time (fast slew rate) t

IH

0.9 - 0.9 - 1.1 - ns 2,3,5,6

Input Setup Time (slow sl ew rate) t

IS

1.0 - 1.0 - 1.1 - ns 2,4,5,6

Input Hold Time (slow slew rate) t

IH

1.0 - 1.0 - 1.1 - ns 2,4,5,6

Input Pulse Width t

IPW

2.2 - 2.2 - - - ns 6

Write DQS High Level Width t

DQSH

0.4 0.6 0.4 0.6 0.4 0.6 CLK

Write DQS Low Level Width t

DQSL

0.4 0.6 0.4 0.6 0.4 0.6 CLK

CLK to First Rising edge of DQS-In t

DQSS

0.75 1.25 0.75 1.25 0.75 1.25 CLK

Data-In Setup Time to DQS-In (DQ & DM) t

DS

0.5 - 0.5 - 0.6 - ns 7

Data-in Hold Time to DQS-In (DQ & DM) t

DH

0.5 - 0.5 - 0.6 - ns 7

DQ & DM Input Pulse Width t

DIPW

1.75 - 1.75 - 2 - ns

Read DQS Preamble Time t

RPRE

0.9 1.1 0.9 1.1 0.9 1.1 CLK

Read DQS Postamble Time t

RPST

0.4 0.6 0.4 0.6 0.4 0.6 CLK

MOSEL VITELIC

V827332U04S

11

V827332U04S Rev. 1.2 March 2002

AC Characteristics (cont.)

Notes: 1. This calculation accounts for tDQSQ(max), the pulse width distortion of on-chip circuit and jitter.

2. Data sampled at the rising edges of the clock : A0~A11, BA0~BA1, CKE, CS

, RAS, CAS, WE.

3. For command/address input slew rate >=1.0V/ns

4. For command/address input slew rate >=0 .5V/ns an d <1.0V/ ns

5. CK, CK

slew rate s are >=1 .0V/ns

6. These par amet er s gua r ante e de vi ce ti mi ng , but they ar e no t nec ess ar ily te sted on e ach de vice, an d the y ma y be gua ran te ed
by design or tester correlation.

7. Data latc he d at bo t h ris in g and fallin g ed ge s of Data Strobes(DQS) : DQ, DM

8. Minimum of 20 0 cycl es of stabl e inp ut clo cks af ter S elf R efresh Exit c omman d, whe re CK E is he ld hi gh, is req uired to co mplete
Self Refresh Exit and lock the internal DLL circuit of DDR SDRAM.

Absolute Maximum Ratings

Note: Operation at above absolute maximum rating can adversely affect devi ce reliability

Write DQS Preamble Setup Time t

WPRES

0 - 0 - 0 - CLK

Write DQS Preamble Hold Time t

WPREH

0.25 - 0.25 - 0.25 - CLK

Write DQS Postamble Time t

WPST

0.4 0.6 0.4 0.6 0.4 0.6 CLK

Mode Register Set Delay t

MRD

2 - 2 - 2 - CLK

Power Down Exit Time t

PDEX

10 - 10 - 10 - ns

Exit Self Refresh to Non-Read Command t

XSNR

75 - 75 - 80 - ns

Exit Self Refresh to Read Command t

XSRD

200 - 200 - 200 - CLK 8

Average Perio dic Refr esh Interval t

REFI

- 15.6 - 15.6 - 15.6 us

Parameter Symbol Rating Unit

Ambient Temperature TA 0 ~ 70 °C
Storag e Temperature T

STG

-55 ~ 125 °C

Voltage on Any Pin relative to V

SS

VIN, V

OUT

-0.5 ~ 3.6 V

Voltag e on V

DD

rela tive to V

SS

V

DD

-0.5 ~ 3.6 V

Voltag e on V

DDQ

relative to V

SS

V

DDQ

-0.5 ~ 3.6 V

Output Short Circuit Current I

OS

50 mA

Power Dissipation P

D

8 W

Solderi ng Temperature • Time T

SOLDER

260 • 10 °C • Sec

Parameter Symbol

(PC1600) (PC2100B) (PC2100A)

Unit NoteMin Max Min Max Min Max

12

MOSEL VITELIC

V827332U04S

V827332U04S Rev. 1.2 March 2002

Package Dimensions

A B

Tolerances : ± 0.005(.13) unless otherwise specified

REG PLL REG

A B

5.25 ± 0.006

5.171

(131.350)

(133.350 ± 0.15)

(43.33)

1.7

5.077

(128.950)

0.393
(10.00)

0.100 Min

(2.30 Min)

(19.80)

0.78

(17.80)

0.7

2.500

0.10 M C B A

0.050

0.0078 ±0.006

(0.20 ±0.15)

(1.270)

0.100

(2.50 )

Det ail B

0.250

(6.350)

Det ail A

0.157
(4.00)

0.071
(1.80)

0.039 ± 0.002

(1.000 ± 0.050)

(3.80)

2.175

(6.62)

0.26

0.10

M

CBA

M

0.1496

(3.00)

0.118

R (2.00)

0.0787

(4.00)

0.1575

0.157 Max

0.050 ± 0.0039
(1.270 ± 0.10)

(3.99 Max)

(4.24)

(0.167)

R (2.00)

0.0787

(3.00)

0.118

MOSEL VITELIC

V827332U04S

13

V827332U04S Rev. 1.2 March 2002

Label Information

CL = 2.5 (CLK)

t

RCD

= 3 (CLK)

t

RP

= 3 (CLK)

2533U

UNBUFFERED DIMM

PC2100 08

SPD Revision 0

0

V827332U04SXXX-XX 256MB CLXX
PC2100U-2533-080-A
XXXX-XXXXXXX
Assembly in Taiwan

A

Gerber file JEDEC

-- -

MOSEL VITELIC

Part Number

Module Density

D

IMM manufacture date code

Criteria of PC2100 or PC1600

CAS Latenc

y

14

MOSEL VITELIC

V827332U04S

V827332U04S Rev. 1.2 March 2002

WORLDWIDE OFFICES

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Printedin U.S.A.

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MOSEL VITELIC makes no commitment to update or keep cur­rent the information contained in t his document. No part of this
document may be copied or reproduced in any form or by any
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MOSEL VITELIC subjects its products to normal quality contr

ol

samplingtechniqueswhich are intendedto providean assuranc

e

of high quality products suitable for usual commercial applica

-

tions.MOSELVITELICdoesnot do testingappropriateto provid

e

100% product quality assurance and does not assume any liab

il-

ity for consequential or incidental arising from any use of its prod

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ucts. If such products are to be used in applications in whic

h

personal injury might occur from failure, purchaser must do i

ts

own quality assurance testing appropriate to such applications.

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