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V826664G24SXSG-B1
Datasheet (Mosel Vitelic)
14 pgs149.95 Kb0

Datasheet V826664G24SXSG-C0, V826664G24SXSG-B1, V826664G24SXSG-B0, V826664G24SXSG-A1 Datasheet (Mosel Vitelic)

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Page 1
MOSEL VITELIC
1
V826664G24S 512 MB 200-PIN DDR UNBUFFERED SODIMM
2.5 VOLT 64M x 64
PRELIMINARY
V826664G24S Rev. 1.0 August 2002
Features
■ Utilizes High Performance 32M x 8 DDR SDRAM in SOC Packages
■ Single +2.5V (± 0.2V) Power Supply
■ Programmable CAS
Latency, Burst Length, and
Wrap Sequence (Sequential & Interleave)
■ Auto Refresh (CBR) and Self Refresh
■ All Inputs, Outputs are SSTL-2 Compatible
■ 8192 Refresh Cycles every 64 ms
■ Serial Presence Detect (SPD)
■ DDR SDRAM Performance
Description
The V826664G24S memory module is organized 67,108,864 x 64 bits in a 200 pin memory module. The 64M x 64 memory module uses 16 Mosel­Vitelic 32M x 8 DDR SDRAM. The x64 modules are ideal for use in high performance computer systems where increased memory den sity and fast access times are required.
Component Used -6 -7 -75 -8 Units
tCKClock Frequency
(max.)
166
(PC333)
143
(PC266A)
133
(PC266B)
125
(PC200)
MHz
t
AC
Clock Access Ti me CAS
Latency = 2.5
6 7 7.5 8 ns
Module Speed
A1 PC1600 (100MHz @ CL2) B0 PC2100B (1 33MHz @ CL2.5) B1 PC2100A (1 33MHz @ CL2) C0 PC2700 (166MHz @ CL2.5)
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MOSEL VITELIC
V826664G24S
V826664G24S Rev. 1.0 August 2002
Part Number Information
V 8 2 66 64 G 2 4 S X S G - XX
DDR SDRAM
2.5V WIDTH
DEPTH
200 PIN Unbuffered SODIMM X8 COMPONENT
REFRESH
RATE 8K
4 BANKS
STTL
COMPONENT
REV LEVEL
COMPONENT
PACKAGE, S = SOC
LEAD FINISH
G = GOLD
SPEED
A1 (100MHz@CL2)
MOSEL VITELIC
MANUFACTURED
B0 (133MHz@CL2.5) B1 (133MHz@CL2)
C0 (166MHz@CL2.5)
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MOSEL VITELIC
V826664G24S
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V826664G24S Rev. 1.0 August 2002
Block Diagram
A0
SA0
SERIAL PD
U20
SDA
A1
SA1A2SA2
BA0, BA1
A0-A12
RAS#
BA0, BA1: DDR SDRAMs U1-U8 A0-A12: DDR SDRAMs U1-U8 RAS#: DDR SDRAMs U1-U8 CAS#: DDR SDRAMs U1-U8 CKE0: DDR SDRAMs U1
0
-U8
0
CKE1: DDR SDRAMs U11-U8
1
WE#: DDR SDRAMs U1-U8
CAS# CKE0 CKE1
WE#
V
REF
V
SS
DDR SDRAMs DDR SDRAMs
DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
U8
0
DQ DQ DQ DQ DQ DQ DQ DQ
DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55
U6
0
DQ DQ DQ DQ DQ DQ DQ DQ
DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47
U5
0
DQ DQ DQ DQ DQ DQ DQ DQ
DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39
DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
U4
0
DQ DQ DQ DQ DQ DQ DQ DQ
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23
U2
0
DQ DQ DQ DQ DQ DQ DQ DQ
DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
DM CS# DQS
U1
0
DQ DQ DQ DQ DQ DQ DQ DQ
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
DM0
CS0#
U3
0
DQ DQ DQ DQ DQ DQ DQ DQ
WP
SCL
U1
1
DQ DQ DQ DQ DQ DQ DQ DQ
U2
1
DQ DQ DQ DQ DQ DQ DQ DQ
U3
1
DQ DQ DQ DQ DQ DQ DQ DQ
U5
1
DQ DQ DQ DQ DQ DQ DQ DQ
CS1#
DM CS# DQS
DM CS# DQS DM CS# DQS
DM CS# DQS DM CS# DQS
DM CS# DQS
DQS0
DM7
DQS7
DM2
DQS2
DM5
DQS5
U6
1
DQ DQ DQ DQ DQ DQ DQ DQ
DM CS# DQS
DM4
DQS4
DM3
DQS3
DM CS# DQS
DM CS# DQS
U7
0
DQ DQ DQ DQ DQ DQ DQ DQ
U7
1
DQ DQ DQ DQ DQ DQ DQ DQ
DM CS# DQS
DM CS# DQS
DM CS# DQS DM CS# DQS
DM6
DQS6
DM1
DQS1
U4
1
DQ DQ DQ DQ DQ DQ DQ DQ
DM CS# DQS
U8
1
DQ DQ DQ DQ DQ DQ DQ DQ
DM CS# DQS
V
DDQ
V
DD
DDR SDRAMs
DDR SDRAMs
DDR SDRAM X 8
CK0 CK0#
120
DDR SDRAM X 8
CK1 CK1#
120
120
CK2 CK2#
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MOSEL VITELIC
V826664G24S
V826664G24S Rev. 1.0 August 2002
Pin Configurations (Front Side/Back Side)
Notes:
* These pins ar e not used in this module.
Pin Front Pin Front Pin Front Pin Back Pin Back Pin Back
1 3 5 7
9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39
41 43 45 47 49 51 53 55 57 59 61 63 65
VREF
VSS DQ0 DQ1 VDD
DQS0
DQ2 VSS DQ3 DQ8 VDD DQ9
DQS1
VSS DQ10 DQ11
VDD
CK0
CK0
VSS
DQ16 DQ17
VDD DQS2 DQ18
VSS DQ19 DQ24
VDD DQ25 DQS3
VSS DQ26
67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97
99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133
DQ27
VDD CB0 CB1 VSS
DQS8
CB2 VDD CB3
DU VSS CK2 CK2 VDD
CKE1
DU(A13)
A12
A9
VSS
A7 A5 A3 A1
VDD
A10/AP
BA0
WE
S0
DU VSS
DQ32 DQ33
VDD
DQS4
135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199
DQ34
VSS DQ35 DQ40
VDD DQ41 DQS5
VSS DQ42 DQ43
VDD
VDD
VSS
VSS DQ48 DQ49
VDD DQS6 DQ50
VSS DQ51 DQ56
VDD DQ57 DQS7 DQ58 DQ58 DQ59
VDD
SDA
SCL
VDDSPD
VDDID
2 4 6
8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40
42 44 46 48 50 52 54 56 58 60 62 64 66
VREF
VSS DQ4 DQ5 VDD DM0 DQ6 VSS DQ7
DQ12
VDD
DQ13
DM1
VSS DQ14 DQ15
VDD
VDD
VSS
VSS
DQ20 DQ21
VDD
DM2 DQ22
VSS DQ23 DQ28
VDD DQ29
DM3
VSS DQ30
68 70 72 74 76 78 80 82 84 86 88 90 92 94 96
98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134
DQ31
VDD
CB4
CB5 VSS DM8
CB6 VDD
CB7
DU/(RESET)
VSS VSS VDD VDD
CKE0
DU(BA2)
A11
A8
VSS
A6 A4 A2 A0
VDD
BA1 RAS CAS
S1
DU
VSS
DQ36 DQ37
VDD DM4
136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200
DQ38
VSS DQ39 DQ44
VDD DQ45
DM5
VSS DQ46 DQ47
VDD
CK1
CK1
VSS DQ52 DQ53
VDD
DM6 DQ54
VSS DQ55 DQ60
VDD DQ61
DM7
VSS DQ62 DQ63
VDD
SA0
SA1
SA2
DU
Pin Names
Pin Pin Description
A0~A12 Address Input (Multiplexed) BA0~BA1 Bank Select Address DQ0~DQ63 Data Input/Output DQS0~D Q S7 Data S trobe Input/Output CK0~CK2, CK0
~CK2, Clock Input CKE0, CKE1 Clock Enable Input CS0
, CS1 Chip Selec t Input RAS Row Address Strobe CAS
Column Address Strobe
WE
Write Enable
DM0~DM7 Data - In Mask
VDD Power Supply (2.5V) VDDQ Power Supply for DQS(2.5V) VSS Ground VREF Power Supply for Reference VDDSPD Serial EEPOM Power Supply (2.3V
to 3.6V) SDA Serial Data I/O SCL Serial Clock SA0~2 Address in EEPROM VDDID VDD Identification Flag NC No Connection
Pin Pin Description
Key
Key
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MOSEL VITELIC
V826664G24S
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V826664G24S Rev. 1.0 August 2002
Serial Pr esence Detect Info rm ation
Bin Sort: A1 (PC1600 @ CL2) B0 (PC2100B @ CL2.5) B1 (PC2100A @ CL2)
C0 (PC2700 @ CL2.5)
Byte # Function described
Function Supporte d Hex value
A1 B0 B1 C0 A1 B0 B1 C0
0 Defin es # of B yte s w ri tte n i nt o s eri al memor y at modu le ma nufa ct ur -
er
128bytes 80h
1 Total # of Bytes of SPD memory device 256bytes 08h 2 Fundamental memory type SDRAM DDR 07h 3 # of row address on this assembly 13 0Dh 4 # of column address on this assembly 10 0Ah 5 # of module Rows on this assembly 2 Bank 02h 6 Data width of this assembly 64 bits 40h
7 .........D a ta wid th of this as sem bl y - 00h
8 VDDQ and interface standar d of this assembly SSTL 2.5V 04h
9 DDR SDRAM cycle time at CAS Latency =2.5 8ns 7.5ns 7ns 6ns 80h 75h 70h 60h 10 DDR SDRAM Access time from clock at CL=2.5 ±0.8ns ±0.75ns ±0.75ns ±0.70ns 80h 75h 75h 70h 11 DIMM conf iguratio n ty pe ( Non-parity, Parity , EC C) Non-p ar it y , EC C 00h 12 Refresh rate & type 7.8us & Self refresh 82h 13 Primary DDR SDRAM width x8 08h 14 Error checking DDR SDRAM data width N/A 00h 15 Minimum clock delay for back-to-back random col umn
address
t
CCD
=1CLK 01h
16 DDR SDRAM device attributes : Burst lengths supported 2,4,8 0Eh 17 DDR SDRAM device attributes : # of banks on each DDR SDRAM 4 banks 04h 18 DDR SDRAM device attributes : CAS Latency supported 2,2.5 0Ch 19 DDR SDRAM device attributes : CS Latency 0CLK 01h 20 DDR SDRAM device attributes : WE Latency 1CLK 02h 21 DDR SDRAM module attributes Differential clock /
non Registered
20h
22 DDR SDRAM device attributes : General +/-0.2V voltage tolerance 00h 23 DDR SDRAM cycle time at CL =2 10ns 10ns 7.5ns 7.5ns A0h A0h 75h 75h 24 DDR SDRAM Access time from clock at CL =2 ±0.8ns ±0.75ns ±0.75ns ±0.70ns 80h 75h 75h 70h 25 DDR SDRAM cycle time at CL =1.5 - - - - 00h 26 DDR SDRAM Access time from clock at CL =1.5 - - - - 00h 27 Minimum row precharge time (=t
RP
) 20ns 20ns 20ns 18ns 50h 50h 50h 48h
28 Minimum row activate to row active delay(=t
RRD
) 15ns 15ns 15ns 12ns 3Ch 3Ch 3Ch 30h
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MOSEL VITELIC
V826664G24S
V826664G24S Rev. 1.0 August 2002
29 Minimum RAS to CAS delay(=t
RCD
) 20ns 20ns 20ns 18ns 50h 50h 50h 48h
30 Minimum active to precharge time(=t
RAS
) 50ns 45ns 45ns 42ns 32h 2Dh 2Dh 2Ah 31 Module ROW density 256MB 40h 32 Command and address signal input setup time 1.1ns 0.9ns 0.9ns 0.75ns B0h 90h 90h 75h 33 Command and address signal input hold time 1.1ns 0.9ns 0.9ns 0.75ns B0h 90h 90h 75h 34 Data signal input setup time 0.6ns 0.5ns 0.5ns 0.45ns 60h 50h 50h 45h 35 Data signal input hold time 0.6ns 0.5ns 0.5ns 0.45ns 60h 50h 50h 45h
36-40 Superset information (may be used in future) 00h
41 SD RAM device minimum active to active/auto-refresh time
(=t
RC
)
70ns 65ns 65ns 60ns 46h 41h 41h 3Ch
42 SDRAM device minimum active to autorefresh to active/auto-refresh
time (=t
RFC
)
80ns 75ns 75ns 72ns 50h 4Bh 4Bh 48h
43 SD RAM device maximum device cycle time (=t
CK MAX
) 12ns 12ns 12ns 12ns 30h 30h 30h 30h
44 SD RAM device maximum skew bet ween DQS and DQ signals
(=t
DQSQ
)
0.6ns 0.5ns 0.5ns 0.45ns 3Ch 32h 32h 2Dh
45 SD RAM device maximum read da tahold skew factor (=t
QHS
) 1ns 0.75ns 0.75ns 0.60ns A0h 75h 75h 60h
46-61 Superset information (may be used in future) - 00h
62 SPD data revision code Initial release 00h 63 Checksum for Bytes 0 ~ 62 - E8h 23h F3h 4Ch 64 Manufacturer JEDEC ID code Mosel Vitelic 40h
65 -71 ....... Man ufa ct ure r JEDE C ID cod e 00h
72 Manufacturing location 02=Taiwan 05=China 0A=S-CH
73-90 Module part number (ASCII) V826664G24S
91 Manufacturer revison code (For PCB) 0 00 92 Manufacturer revison code (For component) 0 00 93 Manufacturing date (Week) - ­94 Manufacturing date (Year) - -
95~98 Assembly serial # - ­99~127 Manuf acturer specific data (may be used in future) Un defined 00h 128~255 Open for cu stomer us e Undef i ne d 00h
Byte # Function described
Function Supporte d Hex value
A1 B0 B1 C0 A1 B0 B1 C0
Serial Pr esence Detect Info rm ation (cont . )
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MOSEL VITELIC
V826664G24S
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V826664G24S Rev. 1.0 August 2002
DC Operating Conditions
(TA = 0 to 70°C, Voltage referenced to VSS = 0V)
Notes: 1. V
DDQ
must not exceed the level of VDD.
2. V
IL
(min) is acceptable -1.5V AC pulse width with <=5ns of duration.
3. The value of V
REF
is approximately equal to 0.5V
DDQ
.
AC Operating Conditions
(TA = 0 to 70 °C, Voltage referenced to VSS = 0V)
Notes: 1. VID is the magnitude of the difference between the input level on CK and the input on CK.
2. The value of VIX is expected to equal 0.5* V
DDQ
of the tr ansmitting device a nd must track variations in the DC level of th e
same.
Parameter Symbol Min Typ. Max Unit Note
Power Supply Voltage V
DD
2.3 2.5 2.7 V
Power Supply Voltage V
DDQ
2.3 2.5 2.7 V 1
Input High Voltage V
IH
V
REF
+ 0.15 - V
DDQ
+ 0.3 V
Input Low Voltage V
IL
-0.3 - V
REF
- 0.15 V 2
I/O Termination Voltage V
TT
V
REF
- 0.04 V
REF
V
REF
+ 0.04 V
Refere nce Voltage V
REF
1.15 1.25 1.35 V 3
Input Le ak ag e C urr e nt I
I
-2 - 2 µA
Output Le ak ag e C urr e nt IO
z
-5 - 5 µA
Output High Current (V
OUT
= 1.95V) IO
H
-16.8 - - mA
Output Low Current (V
OUT
= 0.35V) IO
L
16.8 - - mA
Parameter Symbol Min Max Unit Note
Input H ig h (Logic 1) Volt ag e, DQ , DQ S an d D M si gn al s V
IH(AC)
V
REF
+ 0.31 V
Input Low (Logic 0) Voltage, DQ, DQS and DM signals V
IL(AC)
V
REF
- 0.31 V
Input Differential Voltage, CK and CK
inputs V
ID(AC)
0.7 V
DDQ
+ 0.6 V 1
Input Cr os s in g P oin t Voltage, CK an d CK
inputs V
IX(AC)
0.5*V
DDQ-0.2
0.5*V
DDQ+0.2
V2
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MOSEL VITELIC
V826664G24S
V826664G24S Rev. 1.0 August 2002
AC Operating Test Conditions (T
A
= 0 to 70°C, Voltage referenced to VSS = 0V)
Input/Output Capacitance
(V
DD
= 2.5V, V
DDQ
= 2.5V, TA = 25°C, f = 1MHz)
Parameter Value Unit
Refere nce Voltage V
DDQ
x 0.5 V
Termination Voltage V
DDQ
x 0.5 V
AC Input High Level Voltage (V
IH
, min) V
REF
+ 0.31 V
AC Input Low Level Voltage (V
IL
, max) V
REF
- 0.31 V
Input Timing Measurement Reference Level Voltage V
REF
V
Outpu t Tim in g Measurement Ref er e nc e Le vel Voltag e V
TT
V Input Signal maximum peak swing 1.5 V Input minimum Signal Slew Rate 1 V/ns Termination Resistor (R
T
) 50 Ohm
Series Resistor (R
S
) 25 Ohm
Output Load Capacitance for Access Time Measurement (C
L
) 30 pF
Parameter Symbol Min Max Unit
Input ca pacitance (A0 ~ A11, BA0 ~ BA1, RAS, CAS, WE) CIN1 36 45 pF Input ca pacitance (CKE
0
) CIN
2
36 45 pF
Input ca pacitance (CS
0
) CIN
3
34 42 pF
Input ca pacitanc e ( C LK
1
, CLK2) CIN
4
34 38 pF
Data & DQS input/output capacitance (DQ
0
~DQ63) C
OUT
89pF
Input capacitance (DM 0~DM8) CIN
5
89pF
Output Load Circuit (SSTL_2)
O
utput
Z0=50Ω
C
LOAD=30pF
V
REF
=0.5*VDD
Q
RT=50Ω
Vtt=0.5*VDDQ
Page 9
MOSEL VITELIC
V826664G24S
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V826664G24S Rev. 1.0 August 2002
DDR SDRAM IDD SPEC TABLE
* Module IDD was calcul at e d on th e ba si s of component IDD and can be differentl y me as u r ed acc ording to DQ load in g cap.
Detailed test conditions for DDR SDRAM IDD1 & IDD
IDD1 : Operating current: One bank operation
1. Typical Case : Vdd = 2.5V, T=25’ C
2. Worst Case : Vdd = 2.7V, T= 10’ C
3. Only one bank is accessed with tRC(min), Burst Mode, Address and Control inputs on NOP edge are changing once per clock cycle. lout = 0mA
4. Timing patterns
- DDR200(100Mhz, CL=2) : tCK = 10ns, CL2, BL=4, tRCD = 2*tCK, tRA S = 5*tCK Read : A0 N R0 N N P0 N A0 N - repeat the same timing with random addres s changing *50% of data changing at ever y burst
- DDR266B(133Mhz, CL=2.5) : tCK = 7.5ns, CL=2.5, BL=4, t RCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing *50% of data changing at ever y burst
- DDR266A (133Mhz, CL=2) : tCK = 7.5ns, CL=2, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing *50% of data changing at ever y burst
Legend : A=Activate, R=Read, W=Write, P=Precharge, N=NOP
Symbol
C0
DDR333@CL=2.5B1DDR266@CL=2B0DDR266@CL=2.5A1DDR200@CL=2
Unit Not es
Typical Typical Typical Typical
IDD0 880 800 800 640 mA
IDD1 1120 1000 1000 800 mA IDD2P 450 380 380 260 mA IDD2F 365 360 360 320 mA
IDD2Q 340 280 280 240 mA
IDD3P 450 380 380 260 mA IDD3N 460 400 400 320 mA IDD4R 1360 1360 1360 1120 mA
IDD4W 1680 1480 1480 1200 mA
IDD5 1600 1480 1480 1200 mA
IDD6 Normal 54 54 54 54 mA
Low powe r 30 30 30 30 mA Optional
IDD7A 2800 2600 2600 2120 mA
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MOSEL VITELIC
V826664G24S
V826664G24S Rev. 1.0 August 2002
AC Characteristics (AC operating conditions unless otherwise noted)
Parameter Symbol
(PC333) (PC266A) (PC266B) (PC200)
Unit NoteMin Max Min Max Min Max Min Max
Row Cycle Time tRC 60 - 65 - 65 - 70 - ns Auto Refresh Row Cycle Time t
RFC
72 - 75 - 75 - 80 - ns
Row Active Time t
RAS
42 120K 45 120K 45 120K 50 120K ns
Row Address to Column Address Delay t
RCD
18 - 20 - 20 - 20 - ns
Row Active to Row Active Delay t
RRD
12 - 15 - 15 - 15 - ns
Column Address to Column Address Delay t
CCD
1 - 1 - 1 - 1 - CLK
Row Precharge Time t
RP
18 - 20 - 20 - 20 - ns
Write Recovery Time t
WR
12 - 15 - 15 - 15 - ns
Last Dat a-In to Read Command t
DRL
1 - 1 - 1 - 1 - CLK
Auto Precharge Write Recovery + Precharge Time
t
DAL
35 - 35 - 35 - 35 - ns
System Clock Cycle Time
CAS
Latency = 2.5 t
CK
6 12 7 12 7.5 12 8 12 ns
CAS
Latency = 2 7.5 12 7.5 12 10 12 10 12 ns
Clock High Level Width t
CH
0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 CLK
Clock Low Level Width t
CL
0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 CLK
Data-Out edge to Clock edge Skew t
AC
-0.75 0.75 -0.75 0.75 -0.75 0.75 -0.8 0.8 ns
DQS-Out edge to Clock edge Skew t
DQSCK
-0.75 0.75 -0.75 0.75 -0.75 0.75 -0.8 0.8 ns
DQS-Out edge to Data-Out edge Skew t
DQSQ
- 0.45 - 0.5 - 0.5 - 0.6 ns
Data-Out hold time from DQS t
QH tHPmin
-0.75ns
- t
HPmin
-0.75ns
- t
HPmin
-0.75ns
- t
HPmin
-0.75ns
- ns 1
Clock Half Period t
HP
t
CH/L
min
- t
CH/L
min
- t
CH/L
min
- t
CH/L
min
- ns 1
Input Setup Time (fast slew rate) t
IS
0.75 - 0.9 - 0.9 - 1.1 - ns 2,3,5,6
Input Hold Time (fast slew rate) t
IH
0.75 - 0.9 - 0.9 - 1.1 - ns 2,3,5,6
Input Setup Time (slow slew rate) t
IS
0.8 - 1.0 - 1.0 - 1.1 - ns 2,4,5,6
Input Hold Time (slow slew rate) t
IH
0.8 - 1.0 - 1.0 - 1.1 - ns 2,4,5,6
Write DQS High Level Width t
DQSH
0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 CLK
Write DQS Low Level Width t
DQSL
0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 CLK
CLK to First Rising edge of DQS-In t
DQSS
0.75 1.25 0.75 1.25 0.75 1.25 0.75 1.25 CLK
Data-In Setup Time to DQS-In (DQ & DM) t
DS
0.45 - 0.5 - 0.5 - 0.6 - ns 7
Data-in Hold Time to DQS-In (DQ & DM) t
DH
0.45 - 0.5 - 0.5 - 0.6 - ns 7
DQ & DM Input Pulse Width t
DIPW
1.75 - 1.75 - 1.75 - 2 - ns
Read DQS Preamble Time t
RPRE
0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1 CLK
Read DQS Postamble Time t
RPST
0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 CLK
Write DQS Preamble Setup Time t
WPRES
0 - 0 - 0 - 0 - CLK
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MOSEL VITELIC
V826664G24S
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V826664G24S Rev. 1.0 August 2002
AC Characteristics (cont.)
Notes: 1. This calculation accounts for tDQSQ(max), the pulse width distortion of on-chip circuit and jitter.
2. Data sampled at the rising edg es of the clock : A0~A11, B A0~BA1, CKE , C S
, RAS, CAS, WE.
3. For command/addr ess input slew rate >=1.0V/ns
4. For command/addr ess input slew rate >=0.5V/ns and <1.0V/ns
5. CK, CK
slew rate s are >=1 .0V/ns
6. These par amet er s gua r ante e de vi ce ti mi ng , but they ar e no t nec ess ar ily te sted on e ach de vice, an d the y ma y be gua ran te ed by design or tester correlation.
7. Data latc he d at bo t h ris in g and fallin g ed ge s of D at a S trobes(DQ S) : DQ, DM
8. Minimum of 20 0 cycl es of stabl e inp ut clo cks af ter S elf R efresh Exit c omman d, whe re CK E is he ld hi gh, is req uired to co mplete Self Refresh Exit and lock the internal DLL circuit of DDR SDRAM.
Absolute Maximum Ratings
Note: Operation at above absolute maximum rating c an adversely affect device reli ability
Write DQS Preamble Hold Time t
WPREH
0.25 - 0.25 - 0.25 - 0.25 - CLK
Write DQS Postamble Time t
WPST
0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 CLK
Mode Register Set Delay t
MRD
2 - 2 - 2 - 2 - CLK
Power Down Exit Time t
PDEX
10 - 10 - 10 - 10 - ns
Exit Self Refresh to Non-Read Command t
XSNR
75 - 75 - 75 - 80 - ns
Exit Self Refresh to Read Command t
XSRD
200 - 200 - 200 - 200 - CLK 8
Average Periodic Refresh Interval t
REFI
- 7.8 - 7.8 - 7.8 - 7.8 us
Parameter Symbol Rating Unit
Ambient Temperature TA 0 ~ 70 °C Storag e Temperature T
STG
-55 ~ 125 °C
Voltage on Any Pin relative to V
SS
VIN, V
OUT
-0.5 ~ 3.6 V
Voltag e on V
DD
rela tive to V
SS
V
DD
-0.5 ~ 3.6 V
Voltag e on V
DDQ
relative to V
SS
V
DDQ
-0.5 ~ 3.6 V
Output Short Circuit Current I
OS
50 mA
Power Dissipation P
D
16 W
Solderi ng Temperature • Time T
SOLDER
260 • 10 °C • Sec
Parameter Symbol
(PC333) (PC266A) (PC266B) (PC200)
Unit NoteMin Max Min Max Min Max Min Max
Page 12
12
MOSEL VITELIC
V826664G24S
V826664G24S Rev. 1.0 August 2002
Package Dimensions
Tolerances : ±.006(.15) unless otherwise specified
2.70
2.50
Units : Inches (Millimeters)
Full R 2x
0.17
(4.20)
0.456
11.40
1.896
(47.40)
0.24
(6.0)
0.086
0.79 (20.00)
2.15
(63.60)
(67.60)
Detail Z
0.16 ± 0.0039
(4.00
± 0.10)
0.04
± 0.0039
(1.00
± 0.1)
2-
0.07
(1.80)
1.25 (31.75)
0
.16 ± 0.039
(
4.00
± 0.10)
0.096
(2.40)
0.07
(1.8)
0.150 Max
0.04
± 0.0039
(1.00
± 0.10)
0.157 Min
(4.00 Min)
(3.80 Max)
0.157 Min
(4.00 Min)
1
0.024 TYP
0.018
± 0.001
0.01 (0.25)
(0.45 ± 0.03)
(0.60 TYP)
0.102 Min
(2.55 Min)
Detail Y
2
0.098
2.45
40 42
39
41
Z Y
199
200
Page 13
MOSEL VITELIC
V826664G24S
13
V826664G24S Rev. 1.0 August 2002
Label Information
CL = 2.5 (CLK)
t
RCD
= 3 (CLK)
t
RP
= 3 (CLK)
2533U
UNBUFFERED DIMM
PC2700 X
SPD Revision
V826664G24SXXX-XX 512MB CLXX PC2700U-2533-X-XX XXXX-XXXXXXX Assembly in Taiwan
X
--
MOSEL VITELIC
Part Number
Module Density
DIMM manufacture date code
Criteria of PC2700
CAS Latency
X
-
Gerberfileusedforthisdesign
"A":ReferencedesignforrawcardAisusedforthisassembly
"B":ReferencedesignforrawcardBisusedforthisassembly
"C":ReferencedesignforrawcardCisusedforthisassembly
"Z":Noneofthereferencedesignwereusedforthisassembly
Revisionnumberofthereferencedesignused "1":1stRevision "2":2ndRevision blank:notapplicable
CL = 2.5 (CLK)
t
RCD
= 3 (CLK)
t
RP
= 3 (CLK)
2533U
UNBUFFERED SODIMM
PC2100 XX
SPD Revision
X
V826664G24SXXX-XX 512MB CLXX PC2100U-2533-XXX-X XXXX-XXXXXXX Assembly in Taiwan
X
Gerber file
-- -
MOSEL VITELIC
Part Number
Module Density
DIMM manufacture date code
Criteria of PC2100 or PC1600
CAS Latenc
y
CYCLE TIME
Page 14
14
MOSEL VITELIC
V826664G24S
V826664G24S Rev. 1.0 August 2002
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sampling techniques which areintended to provideanassuranc
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100% product quality assurance and does not assume any liab
il-
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ucts. If such products are to be used in applications in whic
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personal injury might occur from failure, purchaser must do i
ts
own quality assurance testing appropriate to such applications.
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