Datasheet V826632K24SXTG-B1, V826632K24SXTG-B0, V826632K24SXTG-A1 Datasheet (Mosel Vitelic)
Page 1
MOSEL VITELIC
1
V826632K24S
2.5 VOLT 32M x 64 HIGH PERFORMANCE
UNBUFFERED DDR SDRAM MODULE
PRELIMINARY
V826632K24S Rev. 1.0 April 2002
Features
■ 184 Pin Unbuffered 33,554,432 x 64 bit
Organization DDR SDRAM Modules
■ Utilizes High Performance 32M x 8 DDR
SDRAM in TSOPII-66 Packages
■ Single +2.5V (± 0.2V) Power Supply
■ Programmable CAS
Latency, Burst Length, and
Wrap Sequence (Sequential & Interleave)
■ Auto Refresh (CBR) and Self Refresh
■ All Inputs, Outputs are SSTL-2 Compatible
■ 8192 Refresh Cycles every 64 ms
■ Serial Presence Detect (SPD)
■ DDR SDRAM Performance
Description
The V826632K24S memory module is organized
33,554,432 x 64 bits in a 184 pin memory module.
The 16M x 64 memory module uses 8 Mosel-Vitelic
32M x 8 DDR SDRAM. Th e x64 modu les are ideal
for use in high performance computer systems
where increased memory den sity and fast access
times are required.
Component Used B1 B0 A1 Units
tCKClock Frequency
(max.)
143
(PC266A)
133
(PC266B)
125
(PC200)
MHz
t
AC
Clock Cycle Time
CAS
Latenc y = 2.5
77.58ns
Page 2
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V826632K24S Rev. 1.0 April 2002
MOSEL VITELIC
V826632K24S
Part Number Information
V 8 2 66 32 K 2 4 S X T G - XX
DDRSDRAM
2.5V
WIDTH
DEPTH
184 PIN Unbuffered
DIMM X8 COMPONENT
REFRESH
RATE 8K
4 BANKS
STTL
COMPONENT
REV LEVEL
COMPONENT
PACKAGE, T = TSOP
LEAD FINISH
G = GOLD
SPEED
A1 (100MHZ@CL2)
MOSEL VITELIC
MANUFACTURED
B0 (133MHZ@CL2.5)
B1 (133MHZ@CL2)
Page 3
MOSEL VITELIC
V826632K24S
3
V826632K24S Rev.1.0 April 2002
CS0
Serial PD
A0 A1 A2
SA0 SA1 SA2
SCL
BA0-BA1 BA0-BA1 : SDRAMs D0 - D7
A0 - A12 A0 - A12 : SDRAMs D0 - D7
RAS RAS : SDRAMs D0 - D7
CAS CAS : SDRAMs D0 - D7
CKE0 CKE : SDRAMs D0 - D7
WE WE : SDRAMs D0 - D7
Notes:
1. DQ-to-I/O wiring is shown as recommended
but may be changed.
2. DQ/DQS/DM/CKE/CS relationships must be
maintained as shown.
3. DQ,DQS, DM/DQS resistors : 22 Ohms.
4. VDDID strap connections
(for memory device VDD, VDDQ) :
STRAP OUT (OPEN): VDD=VDDQ
STRAP IN (
V
SS
): VDD VDDQ
Strap: see Note 4
D0
CS
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQS0
DM0
SDA
V
DD/VDDQ
V
REF
0.1uF
0.1uF
0.1uF
V
SS
D0 - D7
D0 - D7
D0 - D7
D0 - D7
V
DDID
DM DQS
D4
CS
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ32
DQ33
DQS4
DM4
DM DQS
D1
CS
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ8
DQ9
DQS1
DM1
DM DQS
D5
CS
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ40
DQ41
DQS5
DM5
DM DQS
D2
CS
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ16
DQ17
DQS2
DM2
DM DQS
D6
CS
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ48
DQ49
DQS6
DM6
DM DQS
D3
CS
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ24
DQ25
DQS3
DM3
DM DQS
D7
CS
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQ56
DQ57
DQS7
DM7
DM DQS
Clock Wiring
Clock Input SDRAMs
CK0/CK0
CK1/CK1
CK2/CK2
3 SDRAMs
2 SDRAMs
3 SDRAMs
Block D i ag r am
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V826632K24S Rev. 1.0 April 2002
MOSEL VITELIC
V826632K24S
Pin Configurations (Front Side/Back Side)
Notes:
* These pins ar e not used in this module.
Pin Front Pin Front Pin Front Pin Back Pin Back Pin Back
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
VREF
DQ0
VSS
DQ1
DQS0
DQ2
VDD
DQ3
NC
NC
VSS
DQ8
DQ9
DQS1
VDDQ
CK1
CK1
VSS
DQ10
DQ11
CKE0
VDDQ
DQ16
DQ17
DQS2
VSS
A9
DQ18
A7
VDDQ
DQ19
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
A5
DQ24
VSS
DQ25
DQS3
A4
VDD
DQ26
DQ27
A2
Vss
A1
CB0*
CB1*
VDD
DQS8*
A0
CB2*
VSS
CB3*
BA1
Key
DQ32
VDDQ
DQ33
DQS4
DQ34
VSS
BA0
DQ35
DQ40
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
VDDQ
WE
DQ41
CAS
VSS
DQS5
DQ42
DQ43
VDD
NC
DQ48
DQ49
VSS
CK2
CK2
VDDQ
DQS6
DQ50
DQ51
VSS
VDDID
DQ56
DQ57
VDD
DQS7
DQ58
DQ59
VSS
NC
SDA
SCL
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
VSS
DQ4
DQ5
VDDQ
DM0
DQ6
DQ7
VSS
NC
NC
A13*
VDDQ
DQ12
DQ13
DM1
VDD
DQ14
DQ15
CKE1
VDDQ
BA2*
DQ20
A12
VSS
DQ21
A11
DM2
VDD
DQ22
A8
DQ23
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
VSS
A6
DQ28
DQ29
VDDQ
DM3
A3
DQ30
VSS
DQ31
CB4*
CB5*
VDDQ
CK0*
CK0
*
VSS
DM8*
A10
CB6*
VDDQ
CB7*
key
VSS
DQ36
DQ37
VDD
DM4
DQ38
DQ39
VSS
DQ44
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
RAS
DQ45
VDDQ
CS0
CS1
DM5
VSS
DQ46
DQ47
NC
VDDQ
DQ52
DQ53
NC
VDD
DM6
DQ54
DQ55
VDDQ
NC
DQ60
DQ61
VSS
DM7
DQ62
DQ63
VDDQ
SA0
SA1
SA2
VDDSPD
Pin Names
Pin Pin Description
CK1, CK1, CK2, CK2 Differential Clock Inputs
CS0
Chip Select Input
CKE0 Clock Enable Input
RAS
, CAS, WE Commend Sets Inputs
A0 ~ A12 Address
BA0, BA1 Bank Address
DQ0~DQ63 Data Inputs/Outputs
DQS0~DQS7 Data Strobe Inputs/Outputs
DM0~DM7 Data-in Mask
VDD Power Supply
Key Key
VDDQ DQs Power Supply
VSS Ground
VREF Reference Power Supply
VDDSPD Power Supply for SPD
SA0~SA2 E
2
PROM Address Inputs
SCL E2 PROM Clock
SDA E
2
PROM Data I/O
VDDID VDD Identification Flag
DU Do not Use
NC No Connection
Pin Pin Description
Page 5
MOSEL VITELIC
V826632K24S
5
V826632K24S Rev.1.0 April 2002
Serial Pr esence Detect Info rm ation
Bin Sort:
B1 (PC266A @ CL = 2)
B0 (PC266B @ CL = 2.5)
A1 (PC200 @ CL = 2)
Byte # Function described
Function Supported Hex value
A1 B0 B1 A1 B0 B1
0 Defines # of Bytes written into serial memory at module manufacturer 128bytes 80h
1 Total # of Bytes of SPD memory device 256by tes 08h
2 Fundamental memory type SDRAM DDR 07h
3 # of row ad dre ss on this ass em bly 13 0Dh
4 # of column address on this assembly 10 0Ah
5 # of module Rows on this assembly 1 Bank 01h
6 Data w id th of t hi s as s em bl y 64 bits 40h
7 .........Data width of this assembly - 00h
8 VDDQ and interface standard of this assembly SSTL 2.5V 04h
9 DDR SDRAM cycle time at CAS Latency =2.5 8ns 7.5ns 7ns 80h 75h 70h
10 DDR SDRAM Access time from clock at CL=2.5 ± 0.8ns ±0.75ns ±0.75ns 80h 75h 75h
11 DIMM configuration type(Non-parity, Parity, ECC) Non-parity, ECC 00h
12 Refresh rate & type 7.8us & Self refresh 82h
13 Primary DDR SDRAM width x8 08h
14 Error checking DDR SDRAM data width N/A 00h
15 Minimum clock de lay for back-to-back random column
address
t
CCD
=1CLK 01h
16 DDR SDRAM device attributes : Burst lengths supported 2,4,8 0Eh
17 DDR SDRAM device attributes : # of banks on each DDR SDRAM 4 banks 04h
18 DDR SDRAM device attributes : CAS Latency supported 2,2.5 0Ch
19 DDR SDRAM device attributes : CS Latency 0CLK 01h
20 DDR SDRAM device attributes : WE Latency 1CLK 02h
21 DDR SDRAM module attributes Differential clock /
non Registered
20h
22 DDR SDRAM device attributes : General +/-0.2V voltage tolerance 00h
23 DDR SDRAM cycle time at CL =2 10ns 10ns 7.5ns A0h A0h 75h
24 DDR SDRAM Access time from clock at CL =2 ±0.8ns ±0.75ns ±0.75ns 80h 75h 75h
25 DDR SDRAM cycle time at CL =1.5 - - - 00h
26 DDR SDRAM Access time from clock at CL =1.5 - - - 00h
27 Minimum row precharge time (=t
RP
) 20ns 20ns 20ns 50h 50h 50h
28 Minimum r o w activate to row active delay(=t
RRD
) 15ns 15ns 15ns 3Ch 3Ch 3Ch
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V826632K24S Rev. 1.0 April 2002
MOSEL VITELIC
V826632K24S
29 Minimum RAS to CAS delay(=t
RCD
) 20ns 20ns 20ns 50h 50h 50h
30 Minimum active to precharge time(=t
RAS
) 50ns 45ns 45ns 32h 2Dh 2Dh
31 Module ROW density 256MB 40h
32 Command and address signal input setup time 1.1ns 0.9ns 0.9ns B0h 90h 90h
33 Command and address signal input hold time 1.1ns 0.9ns 0.9ns B0h 90h 90h
34 Data signal input setup time 0.6ns 0.5ns 0.5ns 60h 50h 50h
35 Data signal input hold time 0.6ns 0.5ns 0.5ns 60h 50h 50h
36-40 Superset information (may be used in future) 00h
41 SDRAM device minimum active to active/auto-refresh time
(=t
RC
)
70ns 65ns 65ns 46h 41h 41h
42 SDRAM de vice minim um activ e to au to refr es h to activ e /au to -ref res h
time (=t
RFC
)
80ns 75ns 75ns 50h 4Bh 4Bh
43 SDRAM device maximum device cycle time (=t
CK MAX
) 12ns 12ns 12ns 30h 30h 30h
44 SDRAM device maximum skew between DQS and DQ signals
(=t
DQSQ
)
0.6ns 0.5ns 0.5ns 3Ch 32h 32h
45 SDRAM device maximum read datahold skew fac tor (=t
QHS
) 1ns 0.75ns 0.75ns A0h 75h 75h
46-61 Superset information (may be used in future) - 00h
62 SPD data revision code Initial release 00h
63 Checksum for Bytes 0 ~ 62 - E7h 22h F2h
64 Manufacturer JEDEC ID code Mosel Vitelic 40h
65 -71 ....... Manufacturer JEDEC ID code Mosel Vitelic 40h
72 Manufacturin g location 01h
73-90 Module part number (ASC II) V826632K24S
91 Manufacturer re vison code (For PCB ) 0 00
92 Manufacturer re vison code (For comp onent) 0 00
93 Manufacturing date (Week) - 94 Manufacturin g date (Year) - -
95~98 Assembly serial # - -
99~127 Manufacturer specific data (may be used in future) Undefined 00h
128~255 Open for customer use Undefined 00h
Byte # Function described
Function Supported Hex value
A1 B0 B1 A1 B0 B1
Serial Pr esence Detect Info rm ation (con t.)
Page 7
MOSEL VITELIC
V826632K24S
7
V826632K24S Rev.1.0 April 2002
DC Operating Conditions
(TA = 0 to 70°C, Voltage referenced to VSS = 0V)
Notes: 1. V
DDQ
must not exceed the level of VDD.
2. V
IL
(min) is acceptable -1.5V AC pulse width with ð 5ns of duration.
3. The value of V
REF
is approximately equal to 0.5V
DDQ
.
AC Operating Conditions
(TA = 0 to 70 °C, Voltage referenced to VSS = 0V)
Notes: 1. VID is the magnitude of the difference between the input level on CK and the input on CK.
2. The value of VIX is expected to equal 0.5*V
DDQ
of the tr ansmitting device and must track variations in the DC level of the
same.
Parameter Symbol Min Typ. Max Unit Note
Power Supply Voltage V
DD
2.3 2.5 2.7 V
Power Supply Voltage V
DDQ
2.3 2.5 2.7 V 1
Input High V oltage V
IH
V
REF
+ 0.15 - V
DDQ
+ 0.3 V
Input Low Voltage V
IL
-0.3 - V
REF
- 0.15 V 2
I/O Termination Voltage V
TT
V
REF
- 0.04 V
REF
V
REF
+ 0.04 V
Refere nce Voltage V
REF
1.15 1.25 1.35 V 3
Input Le ak ag e C urr e nt I
I
-2 - 2 µA
Output Le ak ag e C urr e nt IO
z
-5 - 5 µA
Output High Current (V
OUT
= 1.95V) IO
H
-16.8 - - mA
Output Low Current (V
OUT
= 0.35V) IO
L
16.8 - - mA
Parameter Symbol Min Max Unit Note
Input H ig h (Logic 1) Volt age, DQ, DQS an d DM signals V
IH(AC)
V
REF
+ 0.31 V
Input Low (Logic 0) Voltage, DQ, DQS and DM signals V
IL(AC)
V
REF
- 0.31 V
Input Differential Voltage, CK and CK
inputs V
ID(AC)
0.7 V
DDQ
+ 0.6 V 1
Input Cr os s in g P oin t Voltage, CK an d CK
inputs V
IX(AC)
0.5*V
DDQ-0.2
0.5*V
DDQ+0.2
V2
Page 8
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V826632K24S Rev. 1.0 April 2002
MOSEL VITELIC
V826632K24S
AC Operating Test Conditions (T
A
= 0 to 70°C, Voltage referenced to VSS = 0V)
Input/Output Capacitance
(V
DD
= 2.5V, V
DDQ
= 2.5V, TA = 25°C, f = 1MHz)
Parameter Value Unit
Refere nce Voltage V
DDQ
x 0.5 V
Termination Voltage V
DDQ
x 0.5 V
AC Input High Level Voltage (V
IH
, min) V
REF
+ 0.31 V
AC Input Low Level Voltage (V
IL
, max) V
REF
- 0.31 V
Input Timing Measurement Reference Level Voltage V
REF
V
Outpu t Tim in g Measur em e nt R ef er e nc e Le vel Voltag e V
TT
V
Input Signal maximum peak swing 1.5 V
Input minimum Signal Slew Rate 1 V/ns
Termination Resistor (R
T
) 50 ohm
Series Resistor (R
S
) 25 ohm
Output Load Capacitance for Access Time Measurement (C
L
) 30 pF
Parameter Symbol Min Max Unit
Input ca pacita nc e (A0 ~ A11, BA0 ~ BA1, RAS, CAS, WE) CIN1 29 34 pF
Input ca pacita nc e (C KE
0
) CIN
2
29 34 pF
Input ca pacita nc e (C S
0
) CIN
3
26 30 pF
Input ca pacita nc e (C LK
1
, CLK2) CIN
4
30 32 pF
Data & DQS input/output capacitance (DQ
0
~DQ63) C
OUT
8 9 pF
Input capacit a nc e ( DM 0~DM8) CIN
5
8 9 pF
Output Load Circuit (SSTL_2)
O
utput
Z0=50Ω
C
LOAD
=30pF
V
REF
=0.5*V
DD
Q
RT=50Ω
Vtt=0.5*V
DDQ
Page 9
MOSEL VITELIC
V826632K24S
9
V826632K24S Rev.1.0 April 2002
DDR SDRAM Module IDD Spec Table
AC Characteristics
(AC operating conditions unless otherwise noted)
Symbol
B1(DDR266@CL=2) B0(DDR266@CL=2.5) A1(DDR200@CL=2)
Unittypical worst typical worst typical worst
IDD0 720 760 720 760 640 680 mA
IDD1 1120 1200 1120 1200 1000 1080 mA
IDD2P 168 200 168 200 152 184 mA
IDD2F 320 360 320 360 280 320 mA
IDD2Q 240 280 240 280 216 256 mA
IDD3P 200 240 200 240 160 200 mA
IDD3N 320 360 320 360 240 280 mA
IDD4R 1200 1320 1200 1320 1000 1120 mA
IDD4W 1080 1200 1080 1200 840 960 mA
IDD5 1560 1640 1560 1640 1140 1520 mA
IDD6 Normal 16 16 16 16 16 16 mA
Low power 888888mA
IDD7 2080 2240 2080 2240 2000 2200 mA
Parameter Symbol
(PC266A) (PC266B) (PC200)
Unit NoteMin Max Min Max Min Max
Row Cycle Time tRC 65 - 65 - 70 - ns
Auto Refresh Row Cycle Time t
RFC
75 - 75 - 80 - ns
Row Active Time t
RAS
45 120K 45 120K 50 120K ns
Row Address to Column Address Delay t
RCD
20 - 20 - 20 - ns
Row Active to Row Active Delay t
RRD
15 - 15 - 15 - ns
Column Address to Column Address Delay t
CCD
1 - 1 - 1 - CLK
Row Precharge Time t
RP
20 - 20 - 20 - ns
Write Recovery Time t
WR
15 - 15 - 15 - ns
Last Dat a-In to Read Comman d t
DRL
1 - 1 - 1 - CLK
Auto Precharge Write Rec overy + Precharge
Time
t
DAL
35 - 35 - 35 - ns
System Clock Cycle Time CAS
Latency = 2.5 t
CK
7 12 7.5 12 8 12 ns
CAS
Latency = 2 7.5 12 10 12 10 12 ns
Clock High Level Width t
CH
0.45 0.55 0.45 0.55 0.45 0.55 CLK
Clock Low Level Width t
CL
0.45 0.55 0.45 0.55 0.45 0.55 CLK
Data-Out edge to Clock edge Skew t
AC
-0.75 0.75 -0.75 0.75 -0.8 0.8 ns
Page 10
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V826632K24S Rev. 1.0 April 2002
MOSEL VITELIC
V826632K24S
AC Characteristics (cont.)
Notes: 1. This calculation accounts for tDQSQ(max), the pulse width distortion of on-chip circuit and jitter.
2. Data sampled at the rising edges of the clock : A0~A11, BA0~BA1, CKE, CS
, RAS, CAS, WE.
3. For command/address input slew rate >=1.0V/ns
4. For command/address input slew rate >=0.5V/ns and <1.0V/ns
5. CK, CK
slew rate s are >=1 .0V/ns
6. These par amet er s gua r ante e de vi ce ti mi ng , but they ar e no t nec ess ar ily te sted on e ach de vice, an d the y ma y be gua ran te ed
by design or tester correlation.
7. Data latc he d at bo t h ris in g and fallin g ed ge s of D at a S tr ob e s(D Q S) : DQ, DM
8. Minimum of 20 0 cycl es of stabl e inp ut clo cks af ter S elf R efresh Exit c omman d, whe re CK E is he ld hi gh, is req uired to co mplete
Self Refresh Exit and lock the internal DLL circuit of DDR SDRAM.
DQS-Out edge to Clock edge Skew t
DQSCK
-0.75 0.75 -0.75 0.75 -0.8 0.8 ns
DQS-Out edge to Data-Out edge Skew t
DQSQ
- 0.5 - 0.5 - 0.6 ns
Data-Out hold time from DQS t
QH
t
HPmin
-0.75ns
- t
HPmin
-0.75ns
- t
HPmin
-0.75ns
- ns 1
Clock Half Period t
HP
t
CH/L
min
- t
CH/L
min
- t
CH/L
min
- ns 1
Input Setup Time (fast slew rate) t
IS
0.9 - 0.9 - 1.1 - ns 2,3,5,6
Input Hold Time (fast slew rate) t
IH
0.9 - 0.9 - 1.1 - ns 2,3,5,6
Input Setup Time (slow slew rate) t
IS
1.0 - 1.0 - 1.1 - ns 2,4,5,6
Input Hold Time (slow slew rate) t
IH
1.0 - 1.0 - 1.1 - ns 2,4,5,6
Write DQS High Level Width t
DQSH
0.4 0.6 0.4 0.6 0.4 0.6 CLK
Write DQS Low Level Width t
DQSL
0.4 0.6 0.4 0.6 0.4 0.6 CLK
CLK to First Rising edge of DQS-In t
DQSS
0.75 1.25 0.75 1.25 0.75 1.25 CLK
Data-In Setup Time to DQS-In (DQ & DM) t
DS
0.5 - 0.5 - 0.6 - ns 7
Data-in Hold Time to DQS-In (DQ & DM) t
DH
0.5 - 0.5 - 0.6 - ns 7
DQ & DM Input Pulse Width t
DIPW
1.75 - 1.75 - 2 - ns
Read DQS Preamble Time t
RPRE
0.9 1.1 0.9 1.1 0.9 1.1 CLK
Read DQS Postamble Time t
RPST
0.4 0.6 0.4 0.6 0.4 0.6 CLK
Write DQS Preamble Setup Time t
WPRES
0 - 0 - 0 - CLK
Write DQS Preamble Hold Time t
WPREH
0.25 - 0.25 - 0.25 - CLK
Write DQS Postamble Time t
WPST
0.4 0.6 0.4 0.6 0.4 0.6 CLK
Mode Register Set Delay t
MRD
2 - 2 - 2 - CLK
Power Down Exit Time t
PDEX
10 - 10 - 10 - ns
Exit Self Refresh to Non-Read Command t
XSNR
75 - 75 - 80 - ns
Exit Self Refresh to Read Command t
XSRD
200 - 200 - 200 - CLK 8
Average Periodic Refresh Interval t
REFI
- 7.8 - 7.8 - 7.8 us
Parameter Symbol
(PC266A) (PC266B) (PC200)
Unit NoteMin Max Min Max Min Max
Page 11
MOSEL VITELIC
V826632K24S
11
V826632K24S Rev.1.0 April 2002
Absolute Maximum Ratings
Note: Operation at above absolute maximum rating can adversely affect device reliability
Parameter Symbol Rating Unit
Ambient Temperature TA 0 ~ 70 °C
Storag e Temperature T
STG
-55 ~ 125 °C
Voltage on Any Pin relative to V
SS
VIN, V
OUT
-0.5 ~ 3.6 V
Voltag e on V
DD
rela tive to V
SS
V
DD
-0.5 ~ 3.6 V
Voltag e on V
DDQ
relative to V
SS
V
DDQ
-0.5 ~ 3.6 V
Output Short Circuit Current I
OS
50 mA
Power Dissipation P
D
6W
Solderi ng Temperature • Time T
SOLDER
260 • 10 °C • Sec
Page 12
12
V826632K24S Rev. 1.0 April 2002
MOSEL VITELIC
V826632K24S
Package Dimensions
Tolerances : ± 0.005(.13) unless otherwise specified.
The used device is 8Mx16 SDRAM, TSOP.
SDRAM Part NO : K4H281638B-TC
5.25 ± 0.006
5.077
i
0.050
0.0078 ±0.006
(0.20 ±0.15)
0.100 Min
(2.30 Min)
0.393
(10.00)
(1.270)
0.100
(2.50 )
Detail B
A B
0.089
(2.26)
(128.950)
(133.350 ± 0.15)
0.250
(6.350)
Detail A
0.157
(4.00)
0.071
(1.80)
0.039 ± 0.002
(1.000 ± 0.050)
(3.80)
2.175
(6.62)
(64.77) (49.53)
(17.80)
2.55
1.95
0.26
2.500
0.7
0.10
C
BA
0.10
MC BA
0.1496
(3.00)
0.118
(2.00)
0.0787
(4.00)
0.1575
1.25 ± 0.006
(31.75
±
0.15)
(4.00)
(2X)0.157
0.098 Max
0.050 ± 0.003
9
(1.270 ± 0.10
)
(2.47 Max)
M
M
Units: Inches (Millimeters)
Page 13
MOSEL VITELIC
V826632K24S
13
V826632K24S Rev.1.0 April 2002
CL = 2.5 (CLK)
t
RCD
= 3 (CLK)
t
RP
= 3 (CLK)
2533U
UNBUFFERED DIMM
PC2100 08
SPD Revision 0
0
V826632K04SXXX-XX 256MB CLXX
PC2100U-2533-080-A
XXXX-XXXXXXX
Assembly in Taiwan
A
Gerber file JEDEC
-- -
MOSEL VITELIC
Part Number
Module Density
D
IMM manufacture date code
Criteria of PC2100 or PC1600
CAS Latenc
y
Page 14
14
V826632K24S Rev. 1.0 April 2002
MOSEL VITELIC
V826632K24S
WORLDWIDE OFFICES
© Copyright, MOSEL VITELIC Corp.
Printedin U.S.A.
The information in this document is subject to change without
notice.
MOSEL VITELIC makes no commitment to update or keep current the information contained in this document. No part of this
document may be copied or reproduced in any form or by any
means without the prior written consent of MOSEL-VITELIC.
MOSEL VITELIC subjects its products to normal quality contr
ol
samplingtechniqueswhich are intendedtoprovide an assuranc
e
of high quality products suitable for usual commercial applica
-
tions.MOSELVITELICdoes not dotestingappropriate toprovid
e
100% product quality assurance and does not assume any liab
il-
ity for consequential or incidental arising from any use of its prod
-
ucts. If such products are to be used in applications in whic
h
personal injury might occur from failure, purchaser must do i
ts
own quality assurance testing appropriate to such applications.
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