Datasheet V62C3801024LL-70V, V62C3801024LL-70T, V62C3801024LL-70B, V62C3801024LL-55V, V62C3801024LL-55T Datasheet (Mosel Vitelic)
...Page 1
1
2
3
4
5
6
7
8
9
16
15
14
13
12
11
10
A
8
A
9
A
11
A
13
WE
CE
2
A
15
Vcc
NC
A
16
A
14
A
12
A
7
A
6
A
5
A
4
32
31
30
29
28
27
26
25
24
17
18
19
20
21
22
23
CE1
A
10
OE
I/O
8
I/O
7
I/O
6
I/O
5
I/O
4
GND
I/O
3
I/O
2
I/O
1
A
0
A
1
A
2
A
3
1024
X
1024
ROW DECODER
SENSE AMP
INPUT BUFFER
COLUMN DECODER
CONTROL
CIRCUIT
I/O
7
I/O
0
OE
WE
CE1
CE2
A9A10A11A12A13A14A15A
16
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
V62C3801024L(L)
Ultra Low Power
128K x 8 CMOS SRAM
Features
• Ultra Low-power consumption
- Active: 30mA at 55ns
- Stand-by: 5
µA (CMOS input/output)
1 µA CMOS input/output, L version
• Single +2.7V to 3.3V Power Supply
• Equal access and cycle time
• 55/70/85/100 ns access time
• Easy memory expansion with CE1
, CE2
and OE
inputs
• 2.0V data retention mode
• TTL compatible, Tri-state input/output
• Automatic power-down when deselected
Functional Description
The V62C3801024L is a low power CMOS Static RAM organized as 131,072 words by 8 bits. Easy memory expansion is
provided by an active LOW CE1
, an active HIGH CE2, an a-
ctive LOW OE
, and Tri-state I/O’s. This device has an au-
tomatic power-down mode feature when deselected.
Writing to the device is accomplished by taking Chip E-
nable 1 (CE1
) with Write Enable (WE) LOW, and Chip Enable 2 (CE2) HIGH. Reading from the device is performed
by taking Chip Enable 1 (CE1
) with Output Enable
(OE) LOW while Write Enable (WE) and Chip Enable 2
(CE2) is HIGH. The I/O pins are placed in a high-impedance state when the device is deselected: the outputs are disabled during a write cycle.
The V62C3801024LL comes with a 2V data retention feature
and Lower Standby Power. TheV62C3801024L is available in
a 32-pin 8 x 20 mm TSOP1 / STSOP / 48-fpBGA packages.
32-Pin TSOP1 / STSOP (See next page)
Logic Block Diagram
1024
X
1024
ROW DECODER
SENSE AMP
INPUT BUFFER
COLUMN DECODER
CONTROL
CIRCUIT
I/O
8
I/O
1
OE
WE
CE1
CE2
A10A11A12A13A14A15A
16
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
A9
REV. 1.1 April 2001 V62C3801024L(L)
1
Page 2
V62C3801024L(L)
2
Top View
48-CSP Ball-Grid Array package (shading indicates no ball)
1 2 3 4 5 6
A
A0A1CE2
A3A6A
8
B
I/O4A2WE
A4A7I/O
0
C
I/O5NCNCA5NC
I/O
1
D
VSSNCNCNCNCV
DD
E
VDDNCNCNCNCV
SS
F
I/O6NCNCNCNCI/O
2
G
I/O7OE
CE1A16A15I/O
3
H
A9A10A11A12A13A
14
MOSEL VITELIC V62C3801024L(L)B
TOP VIEW
6
5
4
3
2
1
A B C D E F G H
REV. 1.1 April 2001 V62C3801024L(L)
Page 3
V62C3801024L(L)
Absolute Maximum Ratings *
* Note: Stresses greater than those listed above Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions outside those indicated in the operational sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect reliability.
Parameter Symbol Minimum Maximum Unit
Voltage on Any Pin Relative to Gnd Vt -0.5 4.6 V
Power Dissipation P
T
− 1.0 W
Storage Temperature (Plastic) Tstg -55 +150
0
C
Temperature Under Bias Tbias -40 +85
0
C
Truth Table
* Key: X = Don’t Care, L = Low, H = High
CE1 CE2 WE OE Data Mode
H X X X High-Z Standby
X L X X High-Z Standby
L H H L Data Out Active, Read
L H H H High-Z Active, Output Disable
L H L X Data In Active, Write
3
Recommended Operating Conditions (T
A
= 00C to +700C / -400C to 850C**)
* VIL min = -1.0V for pulse width less than tRC/2.
** For Industrial Temperature
Parameter Symbol Min Typ Max Unit
V
CC
2.7 3.0 3.3 V
Gnd 0.0 0.0 0.0 V
V
IH
2.2 - VCC + 0.5 V
V
IL
-0.5* - 0.6 V
Supply Voltage
Input Voltage
REV. 1.1 April 2001 V62C3801024L(L)
Page 4
AC Test Conditions
Input Pulse Level 0.6V to 2.2V
Input Rise and Fall Time 5ns
Input and Output Timing
Reference Level 1.4V
Output Load Condition
70ns/85 ns C
L
= 30pf + 1TTL Load
Load 100ns/120 ns C
L
= 100pf + 1TTL Load
C
L
*
Figure A. * Including Scope and Jig Capacitance
TTL
V62C3801024L(L)
DC Operating Characteristics (V
cc
= 3V+10%, Gnd = 0V, TA = 00C to +700C / -400C to 850C)
Input Leakage Current
II
LI
Vcc = Max,
V
in
= Gnd to V
cc
- 1 - 1 - 1 - 1 µA
Output Leakage
Current
II
LO
CE1 = VIH or CE2 = V
IL
Vcc= Max, V
OUT
= Gnd to V
cc
- 1 - 1 - 1 - 1 µA
Operating Power
Supply Current
I
CC
CE1 = VIL , CE2 = V
IH
VIN = V
IH
or V
IL
, I
OUT
= 0 mA
- 3 - 3 - 3 - 3
mA
Average Operating
Current
I
CC1
CE1 = VIL , CE2 = V
IH
I
OUT
= 0mA,
Min Cycle, 100% Duty
- 30 - 25 - 20 - 15
mA
I
CC2
CE1 = 0.2V,
CE2 = V
cc
- 0.2V
I
OUT
= 0mA,
Cycle Time=1µs, 100% Duty
- 3 - 3 - 3 - 3 mA
Standby Power Supply
Current (TTL Level)
I
SB
CE1 = VIH or CE2 = VIL - 0.5 - 0.5 - 0.5 - 0.5 mA
Standby Power Supply
Current (CMOS Level)
I
SB1
CE1 > Vcc - 0.2V or L
CE2 <
0.2V, f = 0
V
IN
< 0.2V or
V
IN
> Vcc- 0.2V LL
-
-
5
1
-
-
5
1
-
-
5
1
-
-
5
1
µA
µA
Output Low Voltage V
OL
IOL = 2 mA - 0.4 - 0.4 - 0.4 - 0.4 V
Output High Voltage V
OH
IOH = -2 mA 2.4 - 2.4 - 2.4 - 2.4 - V
-55 -85 -100
Unit
Parameter Sym Test Conditions
Min Max Min Max Min Max Min Max
-70
4
Capacitance (f = 1MHz, T
A
= 250C)
Parameter* Symbol Test Condition Max Unit
Input Capacitance
C
in
Vin = 0V 7 pF
I/O Capacitance
C
I/O
V
in
= V
out
= 0V 8 pF
* This parameter is guaranteed by device characterization and is not production tested.
REV. 1.1 April 2001 V62C3801024L(L)
Page 5
V62C3801024L(L)
Parameter Symbol
Unit
Note
Read Cycle Time
t
RC
55 - 70 - 85 - 100 - ns
Address Access Time
tAA - 55 - 70 - 85 - 100 ns
Chip Enable Access Time
t
ACE
- 55 - 70 - 85 - 100 ns
Output Enable Access Time
t
OE
- 35 - 40 - 40 - 50 ns
Output Hold from Address Change
t
OH
10 - 10 - 10 - 10 - ns
Chip Enable to Output in Low-Z
t
CLZ
10 - 10 - 10 - 10 - ns 4,5
Chip Disable to Output in High-Z
t
CHZ
- 25 - 30 - 35 - 40 ns 4,5
Output Enable to Output in Low-Z
t
OLZ
5 - 5 - 5 - 5 - ns 4,5
Output Disable to Output in High-Z
t
OHZ
- 25 - 25 - 30 - 35 ns 4,5
Power-Up Time
t
PU
0 - 0 - 0 - 0 - ns 5
Power-Down Time
t
PD
- 55 - 70 - 85 - 100 ns 5
Read Cycle
(3,9)
(V
cc
= 3.0V+0.3V, Gnd = 0V, TA = 00C to +700C / -400C to +850C)
Write Cycle
(3,11)
(V
cc
= 3.0V+0.3V, Gnd = 0V, TA = 00C to +700C / -400C to +850C)
Parameter Symbol
Unit
Note
Write Cycle Time
t
WC
55 - 70 - 85 - 100 - ns
Chip Enable to Write End
tCW 45 - 60 - 70 - 80 - ns
Address Setup to Write End
t
AW
45 - 60 - 70 - 80 - ns
Address Setup Time
t
AS
0 - 0 - 0 - 0 - ns
Write Pulse Width
t
WP
45 - 50 - 60 - 70 - ns
Write Recovering Time
t
WR
0 - 0 - 0 - 0 - ns
Data Valid to Write End
t
DW
25 - 30 - 35 - 40 - ns
Data Hold Time
t
DH
0 - 0 - 0 - 0 - ns
Write Enable to Output in High-Z
t
WZ
- 25 - 30 - 35 - 40 ns 4,5
Output Active from Write End
t
OW
5 - 5 - 5 - 5 - ns 4,5
Min Max Min Max Min Max Min Max
-55 -70 -85 -100
5
Min Max Min Max Min Max Min Max
-55 -70 -85 -100
REV. 1.1 April 2001 V62C3801024L(L)
Page 6
Timing Waveform of Read Cycle 1
(3,6,7,9)
(Address Controlled)
t
RC
t
AA
t
OH
Data Valid
Address
D
OUT
Timing Waveform of Read Cycle 2
(5,6,8,9)
(CE1 Controlled)
50% 50%
I
CC
I
SB
t
PD
t
CHZ
t
OHZ
t
RC
t
OE
t
OLZ
t
ACE
t
CLZ
t
PU
CE1
OE
D
OUT
Supply Current
Data Valid
Timing Waveform of Read Cycle 3
(3,6,8,9)
(CE2 Controlled)
50% 50%
I
CC
I
SB
t
PD
t
CHZ
t
OHZ
t
RC
t
OE
t
OLZ
t
ACE
t
CLZ
t
PU
CE2
OE
D
OUT
Supply Current
Data Valid
V62C3801024L(L)
6
REV. 1.1 April 2001 V62C3801024L(L)
Page 7
V62C3801024L(L)
Timing Waveform of Write Cycle 1
(10,11)
(WE Controlled)
Data Valid
Address
D
OUT
Timing Waveform of Write Cycle 2
(10,11)
(CE1 Controlled)
Timing Waveform of Write Cycle 3
(10,11)
(CE2 Controlled)
D
IN
WE
t
DW
t
DH
t
OW
t
WZ
t
AS
t
WP
t
WR
t
WC
t
AW
D
OUT
D
IN
WE
Address
CE1
Data Valid
t
WZ
t
DW
t
DH
t
WP
t
WC
t
CW
t
AW
t
WR
t
AS
D
OUT
D
IN
WE
Address
CE2
Data Valid
t
WZ
t
DW
t
DH
t
WP
t
WC
t
CW
t
AW
t
WR
t
AS
7
REV. 1.1 April 2001 V62C3801024L(L)
Page 8
V62C3801024L(L)
Data Retention Characteristics (L Version Only)
(1)
Parameter Symbol Test Condition Min Max Unit
VCC for Data Retention
V
DR
CE1 > VCC - 0.2V or 1.0
-
V
Data Retention Current
I
CCDR
CE
2
< + 0.2V
- 5 µA
Chip Deselect to Data Retention Time
t
CDR
VIN > VCC - 0.2V or 0 - ns
Operation Recovery Time
(2)
t
R
VIN < 0.2V
t
RC
- ns
Data Retention Mode
V
DR
> 1.0V
2.7V 2.7V
V
IH
V
IH
V
DR
V
CC
CE
t
R
t
CDR
Data Retention Waveform
(L Version Only) (TA = 00C to +700C / -400C to +850C)
8
Notes
1. L-version includes this feature.
2. This Parameter is sampled and not 100% tested.
3. For test conditions, see AC Test Condition, Figure A.
4. This parameter is tested with CL = 5
pF as shown in Figure B. Transition is measured +
500mV from steady-state voltage.
5. This parameter is guaranteed, but is not tested.
6. WE
is HIGH for read cycle.
7. CE1
and OE are LOW and CE2 is HIGH for read cycle.
8. Address valid prior to or coincident with CE1
transition LOW or CE2 transition HIGH.
9. All read cycle timings are referenced from the last valid address to the first transtion address.
10. CE1
or WE must be HIGH or CE2 must be LOW during address transition.
11. All write cycle timings are referenced from the last valid address to the first transition address.
REV. 1.1 April 2001 V62C3801024L(L)
Page 9
V62C3801024L(L)
Ordering Information
Device Type* Speed Package
V62C3801024L-55T 55 ns 8 x 20 mm 32-pin Plastic TSOP1
V62C3801024L-70T 70 ns
V62C3801024L-85T 85 ns
V62C3801024L-100T 100 ns
V62C3801024LL-55T 55 ns
V62C3801024LL-70T 70 ns
V62C3801024LL-85T 85 ns
V62C3801024LL-100T 100 ns
V62C3801024L-55V 55 ns 8 x 13.4 mm 32-pin Plastic STSOP
V62C3801024L-70V 70 ns
V62C3801024L-85V 85 ns
V62C3801024L-100V 100 ns
V62C3801024LL-55V 55 ns
V62C3801024LL-70V 70 ns
V62C3801024LL-85V 85 ns
V62C3801024LL-100V 100 ns
V62C3801024L(L)-55B 55 ns 48-fpBGA
V62C3801024L(L)-70B 70 ns
V62C3801024L(L)-85B 85 ns
V62C3801024L(L)-100B 100 ns
9
* For Industrial Temperature tested devices, an “I” designator will be added to the end of the device number.
REV. 1.1 April 2001 V62C3801024L(L)
Page 10
MOSEL VITELIC
WORLDWIDE OFFICES
© Copyright 2001, MOSEL VITELIC Inc.
4/01
Printed in U.S.A.
MOSEL VITELIC
3910 N. First Street, San Jose, CA 95134-1501 Ph: (408) 433-6000 Fax: (408) 433-0952 Tlx: 371-9461
The information in this document is subject to change without
notice.
MOSEL VITELIC makes no commitment to update or keep current the information contained in this document. No part of this
document may be copied or reproduced in any form or by any
means without the prior written consent of MOSEL-VITELIC.
MOSEL VITELIC subjects its products to normal quality control
sampling techniques which are intended to provide an assurance
of high quality products suitable for usual commercial applications. MOSEL VITELIC does not do testing appropriate to provide
100% product quality assurance and does not assume any liability for consequential or incidental arising from any use of its products. If such products are to be used in applications in which
personal injury might occur from failure, purchaser must do its
own quality assurance testing appropriate to such applications.
U.S. SALES OFFICES
U.S.A.
3910 NORTH FIRST STREET
SAN JOSE, CA 95134
PHONE: 408-433-6000
FAX: 408-433-0952
TAIWAN
7F, NO. 102
MIN-CHUAN E. ROAD, SEC. 3
TAIPEI
PHONE: 886-2-2545-1213
FAX: 886-2-2545-1209
NO 19 LI HSIN ROAD
SCIENCE BASED IND. PARK
HSIN CHU, TAIWAN, R.O.C.
PHONE: 886-3-579-5888
FAX: 886-3-566-5888
SINGAPORE
10 ANSON ROAD #23-13
INTERNATIONAL PLAZA
SINGAPORE 079903
PHONE: 65-3231801
FAX: 65-3237013
JAPAN
ONZE 1852 BUILDING 6F
2-14-6 SHINTOMI, CHUO-KU
TOKYO 104-0041
PHONE: 03-3537-1400
FAX: 03-3537-1402
UK & IRELAND
SUITE 50, GROVEWOOD
BUSINESS CENTRE
STRATHCLYDE BUSINESS
PARK
BELLSHILL, LANARKSHIRE,
SCOTLAND, ML4 3NQ
PHONE: 44-1698-748515
FAX: 44-1698-748516
GERMANY
(CONTINENTAL
EUROPE & ISRAEL)
BENZSTRASSE 32
71083 HERRENBERG
GERMANY
PHONE: +49 7032 2796-0
FAX: +49 7032 2796 22
NORTHWESTERN
3910 NORTH FIRST STREET
SAN JOSE, CA 95134
PHONE: 408-433-6000
FAX: 408-433-0952
SOUTHWESTERN
302 N. EL CAMINO REAL #200
SAN CLEMENTE, CA 92672
PHONE: 949-361-7873
FAX: 949-361-7807
CENTRAL,
NORTHEASTERN &
SOUTHEASTERN
604 FIELDWOOD CIRCLE
RICHARDSON, TX 75081
PHONE: 214-826-6176
FAX: 214-828-9754
V62C3801024L(L)
Loading...