Page 1
Copyright © 1998, V3 Semiconductor Corp. V360EPC DataSheet Rev 1.2 1
V360EPC Rev. A0 / A1
LOCAL BUS TO PCI BRIDGE
FOR DE-MULTIPLEXED A/D PROCESSORS
V3 Semiconductor reserves the right to change the specifications of this product without notice.
V360EPC and V96BMC are trademarks of V3 Semiconductor. All other trademarks are the property of their respective owners.
• Glueless interface to i960Cx/Hx and
AMD29030/40 processors
• Configurable for primary master, bus master or
target operation.
• Type 0 and type 1 configuration cycles.
•Upto1KbyteburstaccessonPCIorlocal.
• Large, 640-byteFIFOs using V3’s unique
D
YNAMIC BANDWIDTH ALLOCATION™ architecture
• 64-byte read FIFO per aperture.
• Enhanced support for 8/16-bit local bus devices
with programmable region sizes.
• 3.3 volt support
• Dual bi-directional address space remapping
• Fully compliant with PCI 2.1 specification
• On-the-fly byte order(endian) conversion
•I
2
O ATU and messaging unit including
hardware controlled circularqueues
• 2 channel DMA controller plus multiprocessor
DMA chaining and demand mode DMA
• Hot swapping capability
• 16 8-bit bi-directionalmailboxregisters with
doorbell interrupts
• Flexible PCI and local interrupt management
• Optional power-on serial EEPROM initialization
• 33MHz and 50MHz local bus versions
• Industrials Temperature Grade -40 to +85’C
• Low cost 160-pin EIAJPQFP package
V360EPC provides the highest performance,
most fle xible, an d mos t economic al method to
directly connect i960Cx/Hx or AMD2930/40
processors to the PCI bus. As a generic solution
for 32-bit de-multiplexed local bus applications,
V360EP C is also a suita ble ca ndid ate f or a
variety of high -perfor mance applications based
on Motorola, IBM, DEC and Hitachi embedded
processors - where a minimal amount of glue
logicis needed.
V360EPC is the second generation of V3’s I
2
O
ready PCI bridges - fully backw ar d com patible
with V962P BC and V292PBC Rev B2 devices and is su pporti ng pow erful fea tures l ike Ho t
Swap and DMA ch aining. Th e PC I bu s can be
run at full 33MHz, independent of local bus clock
rate. The overall throughput of the system is
dram at ically i m pr oved b y inc r e asing the FIF O
depths and utilizing the unique D
YNAMIC
BANDWIDTH ALLOCATION™ architecture.
Access to the PCI bus can be performed through
two programmable address apertures. Two more
aper tur es a re provided for PCI -to- loc al b us
accesses. There are 64-bytes of read FIFOs in
each direction, 3 2-b ytes d edi cate d for each
aperture.
Two high-performance DMA channels with
chaining and demand mode capabilities provide
a powerful data transfer engine for bulk data
transfers. Ma ilbox regis ters and flex ible PCI
interrupt controllers are also included to provide
a simple mechanism to emulate PCI device
control ports. The part is available in 160-pin low
cost PQFP packages.
i960Cx/Hx
CPU
V96BMC
MEMORY
CONTROL
D
R
A
M
ROM
V360EPC
LOCAL TO
PCI BRIDGE
TYPICALAPPLICATION
PERIPHERAL
PCI
PCI SLOT or EDGE CONNECTOR
Page 2
V360EPC
2 V360EPC Data Sheet Rev 1.2 Copyright© 1998, V3 SemiconductorInc.
This document contains the product codes, pinouts, package mechanical information, DC
characteristics, and AC characteristics for the V360EPC. Detailed functional information is contained
in the User’s Manual.
V3 Semiconductor retains the rights to change documentation, specifications, or device
functi ona li ty at any tim e wit h out no t ic e. Ple ase ve rif y tha t you ha ve th e late s t copy of all
documents before finalizing a design.
1.0 Product Codes
2.0 Pin Description and Pinout
Table 2 below lists the pin types found on the V360EPC. Table 3 describes the function of each pin on
the V360EPC. Table 5 lists the pins by pin number. Figure 1 shows the pinout for the 160-pin EIAJ
PQFP packageand Figure 2 shows the mechanical dimensions of thepackage.
Table 1: Product Codes
Product Code Processors Bus Type Package Frequency
V360EPC-33
REV A0 / A1
i960Cx/Hx,
AMD29030/40
32-bit de-multiplexed 160-pin EIAJ PQFP 33MHz
V360EPC-50
REV A0 / A1
i960Cx/Hx,
AMD29030/40
32-bit de-multiplexed 160-pin EIAJ PQFP 50MHz
Table 2: Pin Types
Pin Type Description
PCI I PCI input only pin.
PCI O PCI output only pin.
PCI I/O PCI tri-state I/O pin.
PCI I/OD PCI input with open drain output.
I/O
4
TTL I/O pin with 4mA output drive.
I TTL input only pin.
O
4
TTL output pinwith 4mA outputdrive.
Page 3
V360EPC
Copyright © 1998, V3 Semiconductor Corp. V360EPC DataSheet Rev 1.2 3
Table 3: S i gnal Descriptions
PCI Bus Interface
Signal Type R
a
Description
AD[31:0] PCI I/O Z Address and data, multiplexed on the same pins.
C/BE[3:0]
PCI I/O Z Bus Command and Byte Enables, multiplexed on the same pins.
PAR PCI I/O Z Parity represents even parity across AD[31:0] and C/BE[3:0]
.
FRAME
PCI I/O Z
Cycle Frame indicates the beginning and burst length of an
access.
IRDY
PCI I/O Z
Initiator Readyindicates theinitiating agent’s (busmaster’s)ability
to complete the current data phase of the transaction.
TRDY
PCI I/O Z
Target Readyindicates thetarget agent’s(selecteddevice’s) ability to complete the current data phase of the transaction.
STOP
PCI I/O Z
Stop indicates the current target is requesting the master to stop
the current transaction (retry or disconnect).
DEVSEL
PCI I/O Z
DeviceSelect, when actively driven by a target,indicates the driving device has decoded its address as the target of the current
access. As an inputto the initiator, DEVSEL
indicates whether
any device on the bus has been selected.
IDSEL PCI I
Initialization Device Selectis used as a chip selectduringconfiguration read and write transactions. It must be driven high in order
to access the chip’s internal configuration space.
REQ
PCI O Z
Request indicates to the arbiter that this agent requests use of the
bus.
GNT
PCI I
Grant indicates to the agent that access to the bus has been
granted.
PCLK PCI I PCLK provides timing for all transactionson thePCI bus.
PRST
PCI I/O Z/L
Acts as an input when RDIR is high, an output when RDIR is low.
As aninput it isasserted low to bringall internal EPC operation to
a reset state.
PERR
PCI I/O Z
Parity Error is used to report data parity errors during all PCI
transactions except a Special Cycle.
SERR PCI I/OD Z
System Error is u sed to report address parity errors, data parity
errors on the Special Cycle command, or any other system error
where t he result will be catastrophic.
INT[A:D]
PCI I/OD Z Level-sensitive interruptrequests may be received or generated.
Page 4
V360EPC
4 V360EPC Data Sheet Rev 1.2 Copyright© 1998, V3 SemiconductorInc.
Local Bus Interface
Signal Type R Description
LD[31:0]
ID[31:0]
b
I/O4 Z Local multiplexed addr ess and data bus.
LA[31:2] I/O4 Z Local address bus.
BE[3:0]
BWE[3:0]
b
I/O4 Z Local bus byte enables.
W/R
R/W
b
I/O4 Z Read-Write strobe.
ADS
LREQ
b
I/O4 Z Asserted low to indicate the beginning of a bus cycle.
READY
RDY
c
I/O4 Z Local Bus data ready
HOLD
LBREQ
b
O4 L
Local bus hold request: assertedby the chip to initiate a localbus
mastercycle.
HOLDA
LBGRT
b
I Local bus hold acknowledge.
LPAR[3:0] I/O4 Z Localbus parity.
BLAST
BURST
b
I/O4 Z Burst lastc. Burst requestb.
BTERM
ERR
b
I/O4 Z Bus Time-out. Burst terminatec.
LINT
O4 H Localinterrupt request.
LRST
I/O4 L/Z Local bus RESET signal.
LCLK
MEMCLK
b
I Local bus clock.
Serial EEPROM Interface
Signal Type R Description
SCL/LPERR
O4 X EEPROM clock. Local parity error.
SDA I/O4 X EEPROM data.
Table 3: Signal Descriptions (cont’d)
Page 5
V360EPC
Copyright © 1998, V3 Semiconductor Corp. V360EPC DataSheet Rev 1.2 5
2.1 Test Mode Pins
Several device pins are used during manufacturing test to put the V360EPC device into various test
modes.These pinsmust be maintained at proper levels during reset to insure proper operation.
Thisis typically handled through pull-up or pull-down resistors (typically 1K to 10K) on the signalpins if
they are not guaranteedto be at theproper level during reset. Table4 below shows the reset statesfor
test mode pins:
Configuration
Signal Type R Description
RDIR I
Resetdirection.TielowtodrivePRST
out and LRST in, high to
drive LRST
out and PRST in.
EN5V
I
Selects 5V (EN5V
driven low) or 3.3V (EN5V driven high) device
operationmodes.
Power and Ground Signals
Signal Type R Description
V
CC
-
POWER leads intended for external connection to a V
CC
board
plane.
GND -
GROUND leads intended for external connection to a GND board
plane.
a. R indicates state during reset.
b. Applies to AMD29030/40 mode.
c. Applies to i960Cx/Hx mode.
Ta ble 4: RESET State for Test M ode Pins
Mode Pin 134 Pin 135 Pin 153
i960Cx/Hx Pull-Up Pull-Up Pull-Up
AMD2930/40 Pull-Down Pull-Up Pull-Up
Table 3: Signal Descriptions (cont’d)
Page 6
V360EPC
6 V360EPC Data Sheet Rev 1.2 Copyright© 1998, V3 SemiconductorInc.
Table 5: Pin Assignments
PIN # Signal PIN # Signal PIN # Signal PIN # Signal
1V
CC
41 V
CC
81 V
CC
121 V
CC
2INTD42 AD14 82 LA23 122 LA6
3PRST
43 AD13 83 LD8/ID8 123 LD25/ID25
4 PCLK44AD1284LA22124LA5
5GNT
45 AD11 85 LD9/ID9 125 LD26/ID26
6REQ
46 AD10 86 LA21 126 LA4
7 AD31 47 AD9 87 LD10/ID10 127 LD27/ID27
8 AD30 48 AD8 88 LA20 128 LA3
9 AD29 49 C/BE0
89 LD11/ID11 129 LD28/ID28
10 AD28 50 V
CC
90 LA19 130 LA2
11 GND 51 GND 91 LD12/ID12 131 LD29/ID29
12 AD27 52 AD7 92 LA18 132 LD30/ID30
13 AD26 53 AD6 93 LD13/ID13 133 LD31/ID31
14 AD25 54 AD5 94 LA17 134
'1'
’0’
a
15 AD24 55 AD4 95 LD14/ID14 135
BTERM
ERR
a
16 C/BE3 56 AD3 96 LA16 136
READY
RDY
a
17 IDSEL 57 AD2 97 LD15/ID15 137
HOLD
LBREQ
a
18 AD23 58 AD1 98 LA15 138
HOLDA
LBGNT
a
19 AD22 59 AD0 99 LD16/ID16 139
ADS
LREQ
a
20 V
CC
60 V
CC
100 V
CC
140 V
CC
21 GND 61 GND 101 GND 141 GND
22 AD21 62 LD0/ID0 102 LA14 142
LCLK
MEMCLK
a
Page 7
V360EPC
Copyright © 1998, V3 Semiconductor Corp. V360EPC DataSheet Rev 1.2 7
a. Applies to AMD29030/40 mode.
23 AD20 63 LA31 103 LD17/ID17 143 EN5V
24 AD19 64 LD1/ID1 104 LA13 144 V
CC
25 AD18 65 LA30 105 LD18/ID18 145
BE3
BWE3
a
26 AD17 66 LD2/ID2 106 LA12 146
BE2
BWE2
a
27 AD16 67 LA29 107 LD19/ID19 147
BE1
BWE1
a
28 C/BE2 68 LD3/ID3 108 LA11 148
BE0
BWE0
a
29 FRAME 69 LA28 109 LD20/ID20 149
BLAST
BURST
a
30 GND 70 LD4/ID4 110 LA10 150
W/R
R/W
a
31 IRDY 71 LA27 111 LD21/ID21 151 RDIR
32 TRDY
72 LD5/ID5 112 LA9 152 LRST
33 DEVSEL 73 LA26 113 LD22/ID22 153 ’1’
34 STOP
74 LD6/ID6 114 LA8 154 LINT
35 PERR 75 LA25 115 LD23/ID23 155 SDA
36 SERR
76 LD7/ID7 116 LA7 156
SCL/
LPERR
37 PAR 77 LA24 1 17 LPAR2 157 INTA
38 C/BE1 78 LPAR0 118 LPAR3 158 INTB
39 AD15 79 LPAR1 119 LD24/ID24 159 INTC
40 GND 80 GND 120 GND 160 GND
Table 5: Pin Assignments (cont’d)
PIN # Signal PIN # Signal PIN # Signal PIN # Signal
Page 8
V360EPC
8 V360EPC Data Sheet Rev 1.2 Copyright© 1998, V3 SemiconductorInc.
Figure 1: Pinout for 160-pin EIAJ PQFP (top view)
Vcc
INTD#
PRST#
PCLK
GNT#
REQ#
AD31
AD30
AD29
AD28
GND
AD27
AD26
AD25
AD24
C/BE3#
IDSEL
AD23
AD22
Vcc
GND
AD21
AD20
AD19
AD18
AD17
AD16
C/BE2#
FRAME#
GND
IRDY#
TRDY#
DEVSEL#
STOP#
PERR#
SERR#
PAR
C/BE1#
AD15
GND
GND
LPAR1
LPAR0
LA24
LD7/ID7
LA25
LD6/ID6
LA26
LD5/ID5
LA27
LD4/ID4
LA28
LD3/ID3
LA29
LD2/ID2
LA30
LD1/ID1
LA31
LD0/ID0
GND
Vcc
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
GND
Vcc
C/BE0#
AD8
AD9
AD10
AD11
AD12
AD13
AD14
Vcc
GND
LD24/ID24
LPAR3
LPAR2
LA7
LD23/ID23
LA8
LD22/ID22
LA9
LD21/ID21
LA10
LD20/ID20
LA11
LD19/ID19
LA12
LD18/ID18
LA13
LD17/ID17
LA14
GND
Vcc
LD16/ID16
LA15
LD15/ID15
LA16
LD14/ID14
LA17
LD13/ID13
LA18
LD12/ID12
LA19
LD11/ID11
LA20
LD10/ID10
LA21
LD9/ID9
LA22
LD8/ID8
LA23
Vcc
80
120
41
1
81
40
121
160
V360EPC
Vcc
LA6
LD25/ID25
LA5
LD26/ID26
LA4
LD27/ID27
LA3
LD28/ID28
LA2
LD29/ID29
LD30/ID30
LD31/ID31
'1' / '0'
BTERM#/ERR#
READY#/RDY#
HOLD/LBREQ#
HOLDA/LBGNT#
ADS#/LREQ#
Vcc
GND
LCLK/MEMCLK
EN5V#
Vcc
BE3#/BWE3#
BE2#/BWE2#
BE1#/BWE1#
BE0#/BWE0#
BLAST#/BURST#
W/R# (R/W#)
RDIR
LRST#
'1'
LINT#
SDA
SCL/LPERR#
INTA#
INTB#
INTC#
GND
Page 9
V360EPC
Copyright © 1998, V3 Semiconductor Corp. V360EPC DataSheet Rev 1.2 9
Figure 2: 160-pin EIAJ PQFP mechanical details
Unit of Measurement = millimeters
Page 10
V360EPC
10 V360EPC DataSheet Rev 1.2 Copyright © 1998, V3 Semiconductor Inc.
3.0 DC Specifications
The DC specificat ions for the PCI bus signals match exactly those given in thePCI Specification, Rev.
2.1, Section 4.2.1.1. For more information on the PCI DC specifications, see the PCI Specification.
3.1 PCI Bus DC Specifications
Table 6: Absolute Maximum Ratings
Symbol Parameter Value Units
V
CC
Supply voltage -0.3 to +7 V
V
IN
DC input voltage -0.3 to VCC+0.3 V
I
IN
DC input current ± 10 mA
Tj Junction temperature 125 °C
T
STG
Storage temperature range -40 to +125 °C
Table 7: Guaranteed Operating Conditions
Symbol Parameter Value Units
V
CC
Supply voltage 5 volt 4.50 to 5.50 V
V
CC
Supply voltage 3.3 volt 3.0 to 3.6 V
Theta Ja Thermal resistance 50 °C/w
T
A
Ambient t emperature range -40 to 85 °C
Table 8: PCI Bus Signals DC Operating Specifications
Symbol Parameter Condition Min Max Units Notes
V
IH
Input high voltage 2.0 VCC+0.5 V
V
IL
Input lowvoltage -0.5 0.8 V
I
IH
Input high leakage current VIN=2.7V 70 µA1
I
IL
Input lowleakage current VIN=0.5V -70 µA1
V
OH
Output high voltage I
OUT
=-2mA 2.4 V
V
OL
Output low voltage I
OUT
= 3mA, 6mA 0.55 V 2
C
IN
Input pin capacitance 10 pF 3
Page 11
V360EPC
Copyright © 1998, V3 Semiconductor Corp. V360EPC DataSheet Rev 1.2 11
Notes:
1. Input leakage currents include high impedance output leakage for all bi-directional buffers with tri-state outputs.
2. Signals without pull-up resistors have greater than 3mA low output current. Signals requiring pull resistors
have greater than 6mA output current. The latter include FRAME
, TRDY, IRDY,STOP,SERR,PERR.
3. Absolute maximum pin capacitance for a PCI unit is 10pF (except for CLK).
4. Lower capacitance on this input-only pin allows for non-resistive coupling to AD[xx].
3.2 Local Bus DC Specifications
C
CLK
PCLK pin capacitance 5 12 pF
C
IDSEL
IDSEL pin capacitance 8 pF 4
L
PIN
Pin inductance 20 nH
Table 9: Local Bus Signals DC Operating Specifications for V cc = 5 volt
Symbol Description Conditions Min Max Units
V
IL
Low level input voltage VCC= 4.75V 0.8 V
V
IH
High level inputvoltage VCC=5.25V 2.0 V
I
IL
Low level input current VIN=GND, VCC=5.25V -10 µA
I
IH
High level inputcurrent VIN=VCC= 5.25V 10 µA
V
OL4
Low level output voltage for 4 mA
outputs and I/O pins
I
OL
=-4mA 0.4 V
V
OH4
High level output voltage for 4 mA
outputs and I/O pins
I
OH
=4mA 2.4 V
I
OZL
Low level float input leakage VIN=GND -10 µA
I
OZH
High level floatinput leakage VIN=V
CC
10 µA
I
CC
(max) Maximum supply current
V
CC
=5.25V
PCLK = LCLK = 33MHz
150 mA
I
CC
(typ) Typicalsupply current
V
CC
=5.0V
PCLK = LCLK = 33MHz
120 mA
C
IO
Input and output ca pacitance 10 pF
Table 8: PCI Bus Signals DC Operating Specifications
Symbol Parameter Condition Min Max Units Notes
Page 12
V360EPC
12 V360EPC DataSheet Rev 1.2 Copyright © 1998, V3 Semiconductor Inc.
Table 10: Local Bus Signals DC Operating Specification s for Vcc = 3.3 Volt
Symbol Description Conditions Min Max Units
V
IL
Low level input voltage VCC= 3.0V 0.8 V
V
IH
High level inputvoltage VCC=3.6V 2.1 V
I
IL
Low level input current VIN=GND, VCC=3.6V -10 µA
I
IH
High level inputcurrent VIN=VCC=3.6V 10 µA
V
OL4
Low level output voltage for 4 mA
outputs and I/O pins
I
OL
=-4mA 0.4 V
V
OH4
High level output voltage for 4 mA
outputs and I/O pins
I
OH
=4mA 2.4 V
I
OZL
Low level float input leakage VIN=GND -10 µA
I
OZH
High level floatinput leakage VIN=V
CC
10 µA
I
CC
(max) Maximum supply current
V
CC
=3.6V
PCLK = LCLK = 33MHz
95 mA
I
CC
(typ) Typicalsupply current
V
CC
=3.3V
PCLK = LCLK = 33MHz
80 mA
C
IO
Input and output ca pacitance 10 pF
Page 13
V360EPC
Copyright © 1998, V3 Semiconductor Corp. V360EPC DataSheet Rev 1.2 13
4.0 AC Specifications
The AC specifications for the PCI bus signals match exactly those given in the PCI Specification, Rev.
2.1,Section 4.2.1.2.For more information on thePCI AC specifications, including the V/Icurves for 5V
signalling, see section 4.2.1.2 of Rev 2.1 PCI Specification.
4.1 PCI Bus Timings
Notes:
1. Refer to the V/I curves in Section 4.2.1 of the PCI Specification. This specification does not apply to CLK and
RST
which are system outputs. “Switching Current High” specifications are not relevant to open drain outputs
such as SERR
and INTA-INTD.
2. Note that this segment of the minimum current curve is drawn from the AC drive point directly to the DC drive
point rather than toward the voltage rail (as it does in the pull-down curve). This difference is intended to allow
for an optional N-channel pull-up.
3.Maximum current requirements are met asdrivers pull beyond the first step voltage (AC drive point). Equations
defining these maximums (A and B) areprovidedwith the respective V/I curves given in the PCI Spec. The equation defined maxima is met by design.
4. Theminimum slew rate (slowest signal edge) is met bythe PCI drivers. The maximum slew rate (fastest signal
edge) is a guideline. Motherboard designers must bear in mind that rise and fall times faster than this maximum
guideline could occur, and should ensure that signal integrity modeling accounts for this.
Tab le 11: PCI Bus Signals AC Operating Specifications
Symbol Parameter Condition Min Max Units Notes
I
OH(AC)
Switching
current high
0V<V
OUT
≤1.4V -44 mA 1
1.4V<V
OUT
<2.4V -44+(V
OUT
-1.4)/0.024 Equation A mA 1, 2, 3
(Test point) V
OUT
=3.1V -142 mA 3
I
OL(AC)
Switching
current low
V
OUT
≥2.2V 95 mA 1
2.2V>V
OUT
>0.55 V
OUT
/0.023 Equation B mA 1, 3
(Test point) V
OUT
=0.71 206 mA 3
I
CL
Low clamp
current
-5<V
IN
≤-1 -25+(VIN+1)/0.015 mA
t
R
Unloaded
outputrise
time
0.4Vto 2.4V 1 5 V/ns 4
t
F
Unloaded
output fall
time
2.4Vto 0.4V 1 5 V/ns 4
Equation A: IOH= 11.9·(V
OUT
- 5.25V)·(V
OUT
+ 2.45V) for VCC>V
OUT
>3.1V
Equation B: I
OL
= 78.5·V
OUT
(4.4V - V
OUT
)for0V<V
OUT
<0.71V
Page 14
V360EPC
14 V360EPC DataSheet Rev 1.2 Copyright © 1998, V3 Semiconductor Inc.
4.2 Local Bus Timings
Figure 3: Clock and Synchronous Signals
Notes:
Table 12: Local Bus AC Test Conditions
Symbol Parameter Limits Units
V
CC
Supply voltage 5 volt operation 4.50 to 5.50 V
V
CC
Supply voltage 3.3 volt operation 3.0 to 3.60 V
V
IN
Input lowand high voltages 0.4 and 2.0 V
C
OUT
Capacitive load onoutput and I/O pins 50 pF
Table 13: Capacitive Derating for Output and I/O Pins
Output Drive Limit Supply voltage Derating
4mA 5 volt 0.058 ns/pF for loads> 50pF
4mA 3.3 volt 0.099 ns/pF for loads > 50pF
LOCAL CLOCK
INPUT SETUP/HOLD
OUTPUT VALID
OUTPUT DRIVE
OUTPUT FLOAT
T
H
T
SU
T
CL
T
C
T
CH
T
COZ
VALID
VALID
Tczo
T
COV
VALID
Page 15
V360EPC
Copyright © 1998, V3 Semiconductor Corp. V360EPC DataSheet Rev 1.2 15
1. Measured at 1.5V.
2. All local bus signals except those in 4a, 4b, 4c, 4d and 4e.
3. All local bus signals except those in 6a.
4. READY
, BLAST,ADSare driven to high impedance at the falling edge of LCLK.
Table 14: Local Bus Timing Parameters for Vcc = 5 Volts +/- 5%
33MHz 50MHz
# Symbol Description Notes Min Max Min Max Units
1T
C
LCLK/MEMCLK period 30 20 ns
2T
CH
LCLK/MEMCLK high time 1 12 9 ns
3T
CL
LCLK/MEMCLK low time 1 12 9 ns
4T
SU
Synchronous input setup 2 7 6 ns
4a T
SU
Synchronousinput setup
(BLAST
,BTERM)/(BURST,ERR)
87ns
4b T
SU
Synchronousinput setup (ADS/LREQ)65ns
4c T
SU
Synchronous input setup (address, data,
byte enables)
86ns
4d T
SU
Synchronous input setup f or read data
when in localbus master mode
55ns
4e T
SU
Synchronous input setup for (READY,W/
R
, HOLDA)/(RDY,R/W,LBGRT)
54
5T
H
Synchronous input hold 2 2 ns
6T
COV
LCLK/MEMCLK to output valid delay 3 3 14 3 10 ns
6a T
COV
LCLK/MEMCLK to output valid delay
(address, data, byte enable, parity)
315312ns
7T
CZO
LCLK to output driving delay 3 15 3 12 ns
8T
COZ
LCLK/MEMCLK to high impedancedelay 4 3 15 3 12 ns
9T
RST
Reset period when LRST used as input 16·T
C
16·T
C
ns
Page 16
V360EPC
16 V360EPC DataSheet Rev 1.2 Copyright © 1998, V3 Semiconductor Inc.
Tab le 15: Local Bu s Timing Parameters for Vcc = 3.3 Volts +/- 5%
33MHz
# Symbol Description Notes Min Max Units
1T
C
LCLK/MEMCLK period 30 ns
2T
CH
LCLK/MEMCLK high time 1 12 ns
3T
CL
LCLK/MEMCLK low time 1 12 ns
4T
SU
Synchronous input setup 2 8 ns
4a T
SU
Synchronous input setup
(BLAST
,BTERM)/(BURST,ERR)
9ns
4b T
SU
Synchronous input setup (ADS/LREQ)7ns
4c T
SU
Synchronous input setup (address, data,
byte enables)
8ns
4d T
SU
Synchronous input setup for read data
when in local bus master mode
7ns
4e T
SU
Synchronous input setup for (READY,W/
R
, HOLDA)/(RDY,R/W,LBGRT)
5
5T
H
Synchronous input hold 3 ns
6T
COV
LCLK/MEMCLK to output valid delay 3 4 14 ns
6a T
COV
LCLK/MEMCLK to output valid delay
(address, data, byte enable, parity)
416ns
7T
CZO
LCLKto output driving delay 4 16 ns
8T
COZ
LCLK/MEMCLK to high impedance delay 4 4 16 ns
9T
RST
ResetperiodwhenLRSTusedasinput 16·T
C
ns
Table 16: PCI Bus Timing Parameters for Vcc = 5 or 3.3 Volts +/- 10%
# Symbol Description Notes Min Max Units
1T
C
PCLK period 30 ns
2T
SU
Synchronous input setup to PCLK 1 7 ns
2a T
SU
Synchronous input setup to PCLK (GNT)10ns
3T
H
Synchronous input hold from PCLK 0 ns
4T
COV
PCLK to output valid delay 2 3 11 ns
Page 17
V360EPC
Copyright © 1998, V3 Semiconductor Corp. V360EPC DataSheet Rev 1.2 17
Notes:
1. All PCI bus signals except those in 2a.
2. All PCI bus signals except those in 4a.
4.3 Serial EEPROM Port TImings
The clock for the serial EEPROM interface is derived by dividing the PCI bus clock. T he waveforms
generatedareshowninFigure4.
Figure 4: Serial EEPROM Waveforms and Timings
4a T
COV
PCLK to output valid delay (REQ)412ns
5T
CZO
PCLK to output driving delay 4 11 ns
6T
COZ
PCLK to highimpedancedelay 5 18 ns
7T
RST
ResetperiodwhenPRSTusedasinput 16·T
C
Table 16: PCI Bus Timing Parameters for Vcc = 5 or 3.3 Volts +/- 10%
SCL
SDA
STARTCONDITION
STOP CONDITION
512 P CI BUS
CLOCKS
256 PCI BUS
CLOCKS
256 PCI BUS
CLOCKS
Page 18
V360EPC
18 V360EPC DataSheet Rev 1.2 Copyright © 1998, V3 Semiconductor Inc.
5.0 Revision History
USA:
2348G Walsh Ave.
Santa Clara CA 95051
Phone: (408)988-1050 Fax: (408)988-2601
Toll Free: (800)488-8410 (Canada and U.S. only)
World Wide Web: http://www.vcubed.com
Table 17: Revision History
Revision
Number
Date Comments and Changes
1.2 4/99 Updated for Rev. A1
1.1 5/98 Addition of 3.3 volt information.
1.0 8/97 First pre-silicon revision of preliminary data sheet.
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