Page 1
MOSEL VITELIC
1
V29LC51002
2 MEGABIT (262,144 x 8 BIT)
5 VOLT CMOS FLASH MEMORY
PRELIMINARY
V29LC51002 Rev. 0.5 October 2000
Features
■
256Kx8-bit Organization
■
Address Access Time: 90 ns
■
Single 5V ± 10% Power Supply
■
Sector Erase Mode Operation
■
512 bytes per Sector, 512 Sectors
– Sector-Erase Cycle Time: 10ms (Max)
– Byte-Write Cycle Time: 30 µ s (Max)
■
Minimum 1,000 Erase-Program Cycles
■
Low power dissipation
– Active Read Current: 20mA (Typ)
– Active Program Current: 30mA (Typ)
– Standby Current: 100 µ A (Max)
■
Low V
CC
Program Inhibit Below 3.5V
■
CMOS and TTL Interface
■
Packages:
– 32-pin Plastic DIP
– 32-pin PLCC
Description
The V29LC51002 is a high speed 262,144 x 8 bit
CMOS flash memory. Writing or erasing the device
is done with a single 5 Volt power supply. The
device has separate chip enable CE, write enable
WE, and output enable OE controls to eliminate
bus contention.
The V29LC51002 features a sector erase
operation which allows each sector to be erased
and reprogrammed without affecting data stored in
other sectors. The device also supports full chip
erase.
Device Usage Chart
Operating
Temperature
Range
Package Outline Access Time (ns)
Temperature
MarkPJ 90
0 °
C to 70 ° C • • • Blank
Page 2
2
V29LC51002 Rev. 0.5 October 2000
MOSEL VITELIC
V29LC51002
OPERATING VOLTAGE
51: 5V
DEVICE SPEED
C51002-01
V 29 LC 00251 –
90: 90ns
P = PDIP
J = PLCC
PKG.
Pin Configurations
N/C
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
1
2
3
4
5
6
8
9
10
11
12
13
14
15
16
30
31
32
29
28
27
26
25
7
24
23
22
21
20
32-Pin PDIP
Top View
V
CC
WE
A17
A14
A13
A8
A9
A11
OE
A10
CE
I/O3
I/O4
I/O5
I/O6
I/O7
19
18
17
51002-02
A
6
A
5
A
4
A
3
A
2
A
1
I/O
0
5
6
7
8
9
10
11
12
13
29
51002-03
28
27
26
25
24
23
22
21
A12A15A16NC
VCCWE
A
17
A
0
14
I/O
2
GND
I/O
3
I/O4I/O5I/O
6
A
7
A
13
A
8
A
9
A
11
OE
A
10
I/O
7
CE
A
14
I/O
1
32 Pin PLCC
Top View
15 16 17 18 19 20
4
321323130
Pin Names
A
0
–A
17
Address Inputs
I/O
0
–I/O
7
Data Input/Output
CE
Chip Enable
OE
Output Enable
WE Write Enable
V
CC
5V ± 10% Power Supply
GND Ground
NC No Connect
Page 3
MOSEL VITELIC
V29LC51002
3
V29LC51002 Rev. 0.5 October 2000
Functional Block Diagram
Capacitance
(1,2)
NOTE:
1. Capacitance is sampled and not 100% tested.
2. T
A
= 25 ° C, V
CC
= 5V ± 10%, f = 1 MHz.
Latch Up Characteristics
(1)
NOTE:
1. Includes all pins except V
CC
. Test conditions: V
CC
= 5V, one pin at a time.
AC Test Load
Symbol Parameter Test Setup Typ. Max. Units
C
IN
Input Capacitance V
IN
= 0 6 8 pF
C
OUT
Output Capacitance V
OUT
= 0 8 12 pF
C
IN2
Control Pin Capacitance V
IN
= 0 8 10 pF
Parameter Min. Max. Unit
Input Voltage with Respect to GND on A
9
, OE
-1 +13 V
Input Voltage with Respect to GND on I/O, address or control pins -1 V
CC
+ 1 V
V
CC
Current -100 +100 mA
Address buffer & latchesA0–A
17
51002-07
I/O Buffer & Data Latches
I/O
0
–I/O
7
Y-Decoder
2,097,152 Bit
Memory Cell Array
X-Decoder
Control Logic
CE
OE
WE
51002-08
IN3064 or Equivalent
IN3064
or Equivalent
2.7 kΩ
6.2 kΩ
+5.0 V
IN3064 or Equivalent
IN3064 or Equivalent
CL = 100 pF
Device Under
Test
Page 4
4
V29LC51002 Rev. 0.5 October 2000
MOSEL VITELIC
V29LC51002
Absolute Maximum Ratings
(1)
NOTE:
1. Stress greater than those listed unders “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. No more than one output maybe shorted at a time and not exceeding one second long.
DC Electrical Characteristics
(over the commercial operating range)
Symbol Parameter Commercial Unit
V
IN
Input Voltage (input or I/O pins) -2 to +7 V
V
IN
Input Voltage (A
9
pin, OE
) -2 to +13 V
V
CC
Power Supply Voltage -0.5 to +5.5 V
T
STG
Storage Temerpature (Plastic) -65 to +125
°
C
T
OPR
Operating Temperature 0 to +70
°
C
I
OUT
Short Circuit Current
(2)
200 (Max.) mA
Parameter
Name Parameter Test Conditions Min. Max. Unit
V
IL
Input LOW Voltage V
CC
= V
CC
Min. — 0.8 V
V
IH
Input HIGH Voltage V
CC
= V
CC
Max. 2 — V
I
IL
Input Leakage Current V
IN
= GND to V
CC
, V
CC
= V
CC
Max. —
± 1 µ
A
I
OL
Output Leakage Current V
OUT
= GND to V
CC
, V
CC
= V
CC
Max. —
± 10 µ
A
V
OL
Output LOW Voltage V
CC
= V
CC
Min., I
OL
= 2.1mA — 0.4 V
V
OH
Output HIGH Voltage V
CC
= V
CC
Min, I
OH
= -400 µ A 2.4 — V
I
CC1
Read Current CE
= OE = V
IL
, WE
= V
IH
, all I/Os open,
Address input = V
IL
/V
IH
, at f = 1/t
RC
Min.,
V
CC
= V
CC
Max.
— 40 mA
I
CC2
Write Current CE
= WE = VIL, OE = V
IH
, V
CC
= V
CC
Max. — 50 mA
I
SB
TTL Standby Current CE
= OE = WE = V
IH
, V
CC
= V
CC
Max. — 2mA
I
SB1
CMOS Standby Current CE
= OE = WE = V
CC
– 0.3V, V
CC
= V
CC
Max. — 100
µ
A
V
H
Device ID Voltage for A
9
CE
= OE = V
IL
, WE
= V
IH
11.5 12.5 V
I
H
Device ID Current for A
9
CE = OE = V
IL
, WE = V
IH
, A9 = V
H
Max. — 50
µ
A
Page 5
MOSEL VITELIC
V29LC51002
5
V29LC51002 Rev. 0.5 October 2000
AC Electrical Characteristics
(over all temperature ranges)
Read Cycle
Program (Erase/Program) Cycle
Parameter
Name Parameter
-90
UnitMin. Max.
t
RC
Read Cycle Time 90 — ns
t
AA
Address Access Time — 90 ns
t
ACS
Chip Enable Access Time — 90 ns
t
OE
Output Enable Access Time — 45 ns
t
CLZ
CE Low to Output Active 0 — ns
t
OLZ
OE Low to Output Active 0 — ns
t
DF
OE or CE High to Output in High Z 0 40 ns
t
OH
Output Hold from Address Change 0 — ns
Parameter
Name Parameter
-90
UnitMin. Typ. Max.
t
WC
Write Cycle Time 90 ——ns
t
AS
Address Setup Time 0 ——ns
t
AH
Address Hold Time 45 ——ns
t
CS
CE Setup Time 0 ——ns
t
CH
CE Hold Time 0 ——ns
t
OES
OE Setup Time 0 ——ns
t
OEH
OE High Hold Time 0 ——ns
t
WP
WE Pulse Width 45 ——ns
t
WPH
WE Pulse Width High 30 ——ns
t
DS
Data Setup Time 30 ——ns
t
DH
Data Hold Time 0 ——ns
t
WHWH1
Programming Cycle ——30 µs
t
WHWH2
Sector Erase Cycle ——10 ms
t
WHWH3
Chip Erase Cycle — 3 — sec
Page 6
6
V29LC51002 Rev. 0.5 October 2000
MOSEL VITELIC V29LC51002
Waveforms of Read Cycle
Waveforms of WE
Controlled-Program Cycle
NOTES:
1. PA: The address of the memory location to be programmed.
2. PD: The data at the byte address to be programmed.
t
RC
t
AA
t
CE
t
OE
t
CLZ
t
OH
t
AA
t
OLZ
t
DF
ADDRESS
CE
OE
WE
I/O
VALID DATA OUT VALID DATA OUT
HIGH-Z
51002-09
HIGH-Z
t
WC
t
AS
PA5555H
t
WHWH1
t
WPH
t
CS
t
RC
t
AH
t
DS
t
DH
t
WP
t
OES
t
DF
t
OH
t
OE
PD
(3)
Valid
Data
A0H
C51002-10
ADDRESS
CE
OE
WE
I/O
3rd bus cycle
t
CH
Page 7
MOSEL VITELIC V29LC51002
7
V29LC51002 Rev. 0.5 October 2000
Waveforms of Erase Cycle
(1)
NOTES:
1. PA: The address of the memory location to be programmed.
2. PD: The data at the byte address to be programmed.
3. SA: The sector address for Sector Erase.
t
WC
t
AS
t
WPH
t
WHWH
2
3
ADDRESS
CE
OE
WE
I/O
5555H 5555H 5555H2AAAH 2AAAH SA
(5555H for Chip Erase)
AAH 55H 80H AAH 55H 30H
(10H for
Chip Erase)
51002-12
t
AH
t
WP
t
DS
t
DH
t
CS
Page 8
8
V29LC51002 Rev. 0.5 October 2000
MOSEL VITELIC V29LC51002
FUNCTIONAL DESCRIPTION
Read Cycle
A read cycle is performed by holding both CE
and OE signals LOW. Data Out becomes valid only
when these conditions are met. During a read cycle
WE must be HIGH prior to CE and OE going LOW.
WE must remain HIGH during the read operation
for the read to complete (see Table 1).
Output Disable
Returning OE or CE HIGH, whichever occurs first
will terminate the read operation and place the l/O
pins in the HIGH-Z state.
Standby
The device will enter standby mode when the CE
signal is HIGH. The l/O pins are placed in the
HIGH-Z, independent of the OE input state.
Command Sequence
The V29LC51002 does not provide the “reset”
feature to return the chip to its normal state when
an incomplete command sequence or an
interruption has happened. In this case, normal
operation (Read Mode) can be restored by issuing
a “non-existent” command sequence, for example
Address: 5555H, Data FFH.
Byte Write Cycle
The V29LC51002 is programmed on a byte-bybyte basis. The byte write operation is initiated by
using a specific four-bus-cycle sequence: two
unlock program cycles, a program setup command
and program data program cycles (see Table 2).
During the byte write cycle, addresses are
latched on the falling edge of either CE or WE,
whichever is last. Data is latched on the rising edge
of CE or WE, whichever is first. The byte write cycle
can be CE controlled or WE controlled.
Sector Erase Cycle
The V29LC51002 features a sector erase
operation which allows each sector to be erased
and reprogrammed without affecting data stored in
other sectors. Sector erase operation is initiated by
using a specific six-bus-cycle sequence: Two
unlock program cycles, a setup command, two
additional unlock program cycles, and the sector
erase command (see Table 2). A sector must be
first erased before it can be re-written. While in the
internal erase mode, the device ignores any
program attempt into the device. Sector erase is
completed in 10ms max. The V29LC51002 is
shipped fully erased (all bits = 1).
512
512
•
•
•
512
512
V29LC51002
00000H
C51002-15
Table 1. Operation Modes Decoding
NOTES:
1. X = Don’t Care, VIH = HIGH, VIL = LOW, VH = 12.5V Max.
2. PD: The data at the byte address to be programmed.
Decoding Mode CE OE WE A
0
A
1
A
9
I/O
Read V
IL
V
IL
V
IH
A
0
A
1
A
9
READ
Byte Write V
IL
V
IH
V
IL
A
0
A
1
A
9
PD
Standby V
IH
XXXXXHIGH-Z
Output Disable V
IL
V
IH
V
IH
X X X HIGH-Z
Page 9
MOSEL VITELIC V29LC51002
9
V29LC51002 Rev. 0.5 October 2000
Table 2. Command Codes
NOTES:
1. RA: Read Address
2. RD: Read Data
3. PA: The address of the memory location to be programmed.
4. PD: The data at the byte address to be programmed.
5. SA(5): Sector Address
6. 40H: Manufacturing ID
7. 82H: Device ID
Command
Sequence
First Bus
Program Cycle
Second Bus
Program Cycle
Third Bus
Program Cycle
Fourth Bus
Program Cycle
Fifth Bus
Program Cycle
Six Bus
Program Cycle
Address Data Address Data Address Data Address Data Address Data Address Data
Read XXXXH F0H
Read 5555H AAH 2AAAH 55H 5555H F0H RA(1) RD(2)
Autoselect 5555H AAH 2AAAH 55H 5555H 90H 00H 40H(6)
01H 82H(7)
Byte
Program
5555H AAH 2AAAH 55H 5555H A0H PA PD(4)
Chip Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 10H
Sector Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H SA(5) 30H
Chip Erase Cycle
The V29LC51002 features a chip-erase
operation. The chip erase operation is initiated by
using a specific six-bus-cycle sequence: two unlock
program cycles, a setup command, two additional
unlock program cycles, and the chip erase
command (see Table 2).
The automatic erase begins on the rising edge of
the last WE or CE pulse in the command sequence
and is completed in 3 sec max.
Page 10
10
V29LC51002 Rev. 0.5 October 2000
MOSEL VITELIC V29LC51002
Byte Program Algorithm Chip/Sector Erase Algorithm
Write Byte-Write
Command Sequence
Add/Data
5555H/AAH
2AAAH/55H
5555H/A0H
Four Bus
Cycle
Sequence
PA/PD
Write Erase
Command Sequence
Add/Data
5555H/AAH
2AAAH/55H
5555H/80H
Six Bus
Cycle
Sequence
5555H/AAH
2AAAH/55H
5555H/10H (Chip Erase)
SA/30H (Sector Erase)
C51002-16
Time Out 30µS
Writing
Complete
Time Out for Sector or
Chip Erase
Erase Complete
Page 11
MOSEL VITELIC V29LC51002
11
V29LC51002 Rev. 0.5 October 2000
Package Diagrams
32-pin Plastic DIP
32-pin PLCC
15° MAX
0.545/0.555
INDEX-1
.047
+.012
– 0
0.210 MAX
0.120 MIN
0.010 MIN
.600 TYP
1.660 MAX.
.050 MAX
.100
TYP
.032
+.012
– 0
.018
+.006
– .002
.010
+.004
– .0004
INDEX-2
EJECTOR MARK
.420 ± .003
3° - 6°
3° - 6°
3° - 6°
.017
30°
.136 ± .003
.110
.046 ± .003
.025
.050 TYP
.450 ± .003
.490 ± .005
.045X45°
.590 ± .005
.550 ± .003
20 19 18 17 16 15 14
21
22
23
24
25
26
27
28
29
30 31 32 1 2 3 4
13
12
11
10
9
8
7
6
5
Page 12
MOSEL VITELIC WORLDWIDE OFFICES V29LC51002
© Copyright 2000, MOSEL VITELIC Inc.
10/00
Printed in U.S.A.
MOSEL VITELIC 3910 N. First Street, San Jose, CA 95134-1501 Ph: (408) 433-6000 Fax: (408) 433-0952 Tlx: 371-9461
The information in this document is subject to change without
notice.
MOSEL VITELIC makes no commitment to update or keep current the information contained in this document. No part of this
document may be copied or reproduced in any form or by any
means without the prior written consent of MOSEL-VITELIC.
MOSEL VITELIC subjects its products to normal quality control
sampling techniques which are intended to provide an assurance
of high quality products suitable for usual commercial applications. MOSEL VITELIC does not do testing appropriate to provide
100% product quality assurance and does not assume any liability for consequential or incidental arising from any use of its products. If such products are to be used in applications in which
personal injury might occur from failure, purchaser must do its
own quality assurance testing appropriate to such applications.
U.S. SALES OFFICES
U.S.A.
3910 NORTH FIRST STREET
SAN JOSE, CA 95134
PHONE: 408-433-6000
FAX: 408-433-0952
HONG KONG
19 DAI FU STREET
TAIPO INDUSTRIAL ESTATE
TAIPO, NT, HONG KONG
PHONE: 852-2666-3307
FAX: 852-2770-8011
TAIWAN
7F, NO. 102
MIN-CHUAN E. ROAD, SEC. 3
TAIPEI
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NO 19 LI HSIN ROAD
SCIENCE BASED IND. PARK
HSIN CHU, TAIWAN, R.O.C.
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SUITE 50, GROVEWOOD
BUSINESS CENTRE
STRATHCLYDE BUSINESS
PARK
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SCOTLAND, ML4 3NQ
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(CONTINENTAL
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BENZSTRASSE 32
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FAX: +49 7032 2796 22
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PHONE: 408-433-6000
FAX: 408-433-0952
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