Datasheet V29C51002T-90T, V29C51002T-90P, V29C51002T-90J, V29C51002T-55T, V29C51002T-55P Datasheet (Mosel Vitelic)
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MOSEL VITELIC
V29C51002T/V29C51002B
2 MEGABIT (262,144 x 8 BIT)
5 VOLT CMOS FLASH MEMORY
Features
256Kx8-bit Organization
Address Access Time: 55, 90 ns
Single 5V ± 10% Power Supply
Sector Erase Mode Operation
16KB Boot Block (lockable)
512 bytes per Sector, 512 Sectors
– Sector-Erase Cycle Time: 10ms (Max)
– Byte-Write Cycle Time: 20 µ s (Max)
Minimum 10,000 Erase-Program Cycles
Low power dissipation
– Active Read Current: 20mA (Typ)
– Active Program Current: 30mA (Typ)
– Standby Current: 100 µ A (Max)
Hardware Data Protection
Low V
Self-timed write/erase operations with end-of-cycle detection
– DATA Polling
– Toggle Bit
CMOS and TTL Interface
Available in two versions
– V29C51002T (Top Boot Block)
– V29C51002B (Bottom Boot Block)
Packages:
– 32-pin Plastic DIP
– 32-pin TSOP-I
– 32-pin PLCC
Program Inhibit Below 3.5V
CC
PRELIMINARY
Description
The V29C51002T/V29C51002B is a high speed
262,144 x 8 bit CMOS flash memory. Writing or
erasing the device is done with a single 5 Volt
power supply. The device has separate chip enable
CE, write enable WE, and output enable OE
controls to eliminate bus contention.
The V29C51002T/V29C51002B offers a combination of: Boot Block with Sector Erase/Write
Mode. The end of write/erase cycle is detected by
Polling of I/O
DATA
The V29C51002T/V29C51002B features a
sector erase operation which allows each sector to
be erased and reprogrammed without affecting
data stored in other sectors. The device also
supports full chip erase.
Boot block architecture enables the device to
boot from a protected sector located either at the
top (V29C51002T) or the bottom (V29C51002B).
All inputs and outputs are CMOS and TTL
compatible.
The V29C51002T/V29C51002B is ideal for
applications that require updatable code and data
storage.
or by the Toggle Bit I/O
7
.
6
Device Usage Chart
Operating
Temperature
Range
C to 70 ° C ••••• Blank
V29C51002T/V29C51002B Rev. 2.1 October 2000
Package Outline Access Time (ns)
Temperature
MarkPTJ5590
1
Page 2
MOSEL VITELIC
V 29 C 00251
OPERATING VOLTAGE
BOOT BLOCK LOCATION
Pin Configurations
N/C
A16
A15
A12
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
A7
1
2
3
4
5
6
32-Pin PDIP
7
Top View
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
51002-02
V
WE
A17
A14
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
51: 5V
CC
T –
DEVICE SPEED
55: 55ns
90: 90ns
T: TOP
B: BOTTOM
A12A15A16NC
4
3 2 1 32 31 30
A
5
7
6
A
6
7
A
5
8
A
I/O
4
9
A
3
10
A
2
11
A
1
12
A
0
13
0
32 Pin PLCC
Top View
14
15 16 17 18 19 20
2
1
I/O
I/O
GND
VCCWE
3
I/O4I/O5I/O
I/O
P = PDIP
T = TSOP-I
J = PLCC
17
A
29
28
27
26
25
24
23
22
21
6
51002-03
A
A
A
A
A
OE
A
CE
I/O
V29C51002T/V29C51002B
TEMP.
PKG.
BLANK (0°C TO 70°C)
51002-01
Pin Names
A
–A
0
17
I/O
–I/O
0
14
13
8
9
11
10
7
CE
OE Output Enable
WE Write Enable
V
CC
GND Ground
NC No Connect
Address Inputs
Data Input/Output
7
Chip Enable
5V ± 10% Power Supply
V
A16
A15
A12
A11
A13
A14
A17
WE
CC
N/C
A7
A6
A5
A4
A9
A8
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32-Pin TSOP I
Standard Pinout
Top View
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
51002-04
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
A3
V29C51002T/V29C51002B Rev. 2.1 October 2000
2
Page 3
MOSEL VITELIC
V29C51002T/V29C51002B
Functional Block Diagram
X-Decoder
17
Address buffer & latchesA0–A
CE
OE
Control Logic
WE
Capacitance
(1,2)
Symbol Parameter Test Setup Typ. Max. Units
C
IN
C
OUT
C
IN2
NOTE:
1. Capacitance is sampled and not 100% tested.
2. T
= 25 ° C, V
A
Latch Up Characteristics
Input Capacitance V
Output Capacitance V
Control Pin Capacitance V
= 5V ± 10%, f = 1 MHz.
CC
(1)
= 0 6 8 pF
IN
= 0 8 12 pF
OUT
= 0 8 10 pF
IN
2,097,152 Bit
Memory Cell Array
Y-Decoder
I/O Buffer & Data Latches
–I/O
I/O
0
7
51002-07
Parameter Min. Max. Unit
Input Voltage with Respect to GND on A
Input Voltage with Respect to GND on I/O, address or control pins -1 V
V
Current -100 +100 mA
CC
NOTE:
1. Includes all pins except V
. Test conditions: V
CC
, OE
9
= 5V, one pin at a time.
CC
-1 +13 V
+ 1 V
CC
AC Test Load
+5.0 V
IN3064
Device Under
Test
CL = 100 pF
V29C51002T/V29C51002B Rev. 2.1 October 2000
or Equivalent
6.2 kΩ
3
2.7 kΩ
IN3064 or Equivalent
IN3064 or Equivalent
IN3064 or Equivalent
51002-08
Page 4
°
°
± 1 µ
± 10 µ
µ
MOSEL VITELIC
Absolute Maximum Ratings
(1)
V29C51002T/V29C51002B
Symbol Parameter Commercial Unit
V
IN
V
IN
V
CC
T
STG
T
OPR
I
OUT
NOTE:
1. Stress greater than those listed unders “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. No more than one output maybe shorted at a time and not exceeding one second long.
Input Voltage (input or I/O pins) -2 to +7 V
Input Voltage (A
pin, OE
9
) -2 to +13 V
Power Supply Voltage -0.5 to +5.5 V
Storage Temerpature (Plastic) -65 to +125
Operating Temperature 0 to +70
Short Circuit Current
(2)
200 (Max.) mA
C
C
DC Electrical Characteristics
(over the commercial operating range)
Parameter
Name Parameter Test Conditions Min. Max. Unit
V
V
I
IL
I
OL
V
V
I
CC1
I
CC2
I
SB
I
SB1
V
I
H
IL
IH
OL
OH
H
Input LOW Voltage V
Input HIGH Voltage V
Input Leakage Current V
Output Leakage Current V
Output LOW Voltage V
Output HIGH Voltage V
Read Current CE
Address input = V
V
Write Current CE
TTL Standby Current CE
CMOS Standby Current CE
Device ID Voltage for A
Device ID Current for A
CE
9
CE = OE = VIL, WE = VIH, A9 = VH Max. — 50 µA
9
= V
CC
CC
IN
OUT
CC
CC
CC
Min. — 0.8 V
CC
= V
Max. 2 — V
CC
= GND to V
= GND to V
= V
CC
= V
CC
= OE = V
= V
CC
Min., I
Min, I
, WE
IL
Max.
CC
, V
CC
OL
OH
IL
= WE = VIL, OE = V
= OE = WE = V
= OE = WE = V
= OE = V
, WE = V
IL
= V
CC
, V
Max. —
CC
= V
CC
Max. —
CC
= 2.1mA — 0.4 V
= -400 µ A 2.4 — V
, all I/Os open,
= V
IH
/V
, at f = 1/t
IH
IH
, V
IH
CC
– 0.3V, V
CC
IH
Min.,
RC
, V
= V
CC
= V
Max. — 50 mA
CC
Max. — 2mA
CC
= V
CC
Max. — 100
CC
— 40 mA
11.5 12.5 V
A
A
A
V29C51002T/V29C51002B Rev. 2.1 October 2000
4
Page 5
MOSEL VITELIC V29C51002T/V29C51002B
AC Electrical Characteristics
(over all temperature ranges)
Read Cycle
Parameter
Name Parameter
t
RC
t
AA
t
ACS
t
OE
t
CLZ
t
OLZ
t
DF
t
OH
Read Cycle Time 55 — 90 — ns
Address Access Time — 55 — 90 ns
Chip Enable Access Time — 55 — 90 ns
Output Enable Access Time — 25 — 45 ns
CE Low to Output Active 0 — 0 — ns
OE Low to Output Active 0 — 0 — ns
OE or CE High to Output in High Z 0 30 0 40 ns
Output Hold from Address Change 0 — 0 — ns
Program (Erase/Program) Cycle
Parameter
Name Parameter
t
WC
t
AS
t
AH
t
CS
t
CH
t
OES
t
OEH
t
WP
t
WPH
t
DS
t
DH
t
WHWH1
t
WHWH2
t
WHWH3
Write Cycle Time 55 ——90 ——ns
Address Setup Time 0 —— 0 ——ns
Address Hold Time 35 ——45 ——ns
CE Setup Time 0 —— 0 ——ns
CE Hold Time 0 —— 0 ——ns
OE Setup Time 0 —— 0 ——ns
OE High Hold Time 0 —— 0 ——ns
WE Pulse Width 30 ——45 ——ns
WE Pulse Width High 20 ——30 ——ns
Data Setup Time 25 ——30 ——ns
Data Hold Time 0 —— 0 ——ns
Programming Cycle ——20 ——20 µs
Sector Erase Cycle ——10 ——10 ms
Chip Erase Cycle — 2 —— 2 — sec
-55 -90
UnitMin. Max. Min. Max.
-55 -90
UnitMin. Typ. Max. Min. Typ. Max.
V29C51002T/V29C51002B Rev. 2.1 October 2000
5
Page 6
MOSEL VITELIC V29C51002T/V29C51002B
Waveforms of Read Cycle
t
RC
ADDRESS
t
AA
t
CE
CE
t
OE
OE
t
OLZ
WE
t
CLZ
I/O
Waveforms of WE
HIGH-Z
Controlled-Program Cycle
VALID DATA OUT VALID DATA OUT
3rd bus cycle
ADDRESS
t
t
WC
CH
t
AS
PA5555H
t
AH
CE
OE
t
t
OES
t
WP
WHWH1
WE
t
I/O
t
CS
A0H
WPH
t
DS
t
DH
(3)
PD
NOTES:
1. I/O7: The output is the complement of the data written to the device.
2. PA: The address of the memory location to be programmed.
3. PD: The data at the byte address to be programmed.
I/O
t
DF
t
OH
HIGH-Z
t
AA
(2)
PA
t
RC
t
OE
(1)
D
OUT
7
51002-09
t
t
OH
51002-10
DF
V29C51002T/V29C51002B Rev. 2.1 October 2000
6
Page 7
MOSEL VITELIC V29C51002T/V29C51002B
Waveforms of CE Controlled-Program Cycle
t
WC
ADDRESS
WE
OE
5555H PA PA
t
AS
t
AH
(1)
t
RC
t
WP
t
WHWH1
CE
t
A0H
WPH
t
DS
t
DH
(2)
PD
(1)
t
AS
t
AH
t
OES
I/O
Waveforms of Erase Cycle
t
WC
ADDRESS
5555H 5555H 5555H2AAAH 2AAAH SA
CE
OE
t
WP
WE
I/O
t
CS
t
DS
t
WPH
t
DH
AAH 55H 80H AAH 55H 30H
NOTES:
1. PA: The address of the memory location to be programmed.
2. PD: The data at the byte address to be programmed.
3. SA: The sector address for Sector Erase.
I/O7
t
DF
t
OE
D
OUT
t
OH
51002-11
(5555H for Chip Erase)
2
t
WHWH
3
(10H for
Chip Erase)
51002-12
V29C51002T/V29C51002B Rev. 2.1 October 2000
7
Page 8
MOSEL VITELIC V29C51002T/V29C51002B
Waveforms of DATA Polling Cycle
t
CH
CE
t
DF
OE
t
OEH
t
OE
WE
I/O
I/O0-I/O
7
6
I/O
7
I/O0-I/O
6
Waveforms of Toggle Bit Cycle
CE
t
OEH
WE
OE
t
CE
t
t
WHWH1 (2 or 3)
I/O
INVALID
7
OH
VALID DATA OUT
VALID DATA OUT
HIGH-Z
HIGH-Z
51002-13
I/O
6
V29C51002T/V29C51002B Rev. 2.1 October 2000
t
WHWH1 (2 or 3)
8
stop toggling
51002-14
Page 9
MOSEL VITELIC V29C51002T/V29C51002B
Functional Description
The V29C51002T/V29C51002B consists of 512
equally-sized sectors of 512 bytes each. The 16 KB
lockable Boot Block is intended for storage of the
system BIOS boot code. The boot code is the first
piece of code executed each time the system is
powered on or rebooted.
The V29C51002 is available in two versions: the
V29C51002T with the Boot Block address starting
from 3C000H to 3FFFFH, and the V29C51002B
with the Boot Block address starting from 00000H
to 3FFFFH.
Read Cycle
A read cycle is performed by holding both CE
and OE signals LOW. Data Out becomes valid only
when these conditions are met. During a read cycle
WE must be HIGH prior to CE and OE going LOW.
WE must remain HIGH during the read operation
for the read to complete (see Table 1).
Output Disable
Returning OE or CE HIGH, whichever occurs first
will terminate the read operation and place the l/O
pins in the HIGH-Z state.
Standby
The device will enter standby mode when the CE
signal is HIGH. The l/O pins are placed in the
HIGH-Z, independent of the OE input state.
Command Sequence
The V29C51002T/V29C51002B does not
provide the “reset” feature to return the chip to its
normal state when an incomplete command
sequence or an interruption has happened. In this
case, normal operation (Read Mode) can be
restored by issuing a “non-existent” command
sequence, for example Address: 5555H, Data FFH.
V29C51002T V29C51002B
16KB Boot Block 512 Byte
512 Byte
512 Byte
512 Byte
3FFFFH
3C000H
03FFFH
00000H
16KB Boot Block = 32 Sectors
00000H
16KB Boot Block
512 Byte
512 Byte
51002-15
Byte Write Cycle
The V29C51002T/V29C51002B is programmed
on a byte-by-byte basis. The byte write operation is
initiated by using a specific four-bus-cycle
sequence: two unlock program cycles, a program
setup command and program data program cycles
(see Table 2).
During the byte write cycle, addresses are
latched on the falling edge of either CE or WE,
whichever is last. Data is latched on the rising edge
of CE or WE, whichever is first. The byte write cycle
can be CE controlled or WE controlled.
Sector Erase Cycle
The V29C51002T/V29C51002B features a
sector erase operation which allows each sector to
be erased and reprogrammed without affecting
data stored in other sectors. Sector erase operation
is initiated by using a specific six-bus-cycle
sequence: Two unlock program cycles, a setup
command, two additional unlock program cycles,
Table 1. Operation Modes Decoding
Decoding Mode CE OE WE A
Read V
Byte Write V
Standby V
Autoselect Device ID V
Autoselect Manufacture ID V
Enabling Boot Block Protection Lock V
Disabling Boot Block Protection Lock V
Output Disable V
NOTES:
1. X = Don’t Care, VIH = HIGH, VIL = LOW, VH = 12.5V Max.
2. PD: The data at the byte address to be programmed.
V29C51002T/V29C51002B Rev. 2.1 October 2000
IL
IL
IH
IL
IL
IL
H
IL
V
IL
V
IH
XXXXXHIGH-Z
V
IL
V
IL
V
H
V
H
V
IH
V
IH
V
IL
V
IH
V
IH
V
IL
V
IL
V
IH
9
0
A
0
A
0
V
IH
V
IL
XXVHX
XXVHX
X X X HIGH-Z
A
1
A
1
A
1
V
IL
V
IL
A
9
A
9
A
9
V
H
V
H
I/O
READ
PD
CODE
CODE
Page 10
MOSEL VITELIC V29C51002T/V29C51002B
Table 2. Command Codes
First Bus
Command
Sequence
Read XXXXH F0H
Read 5555H AAH 2AAAH 55H 5555H F0H RA(1) RD(2)
Autoselect
Mode
Byte
Program
Chip Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 10H
Sector Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H SA(5) 30H
NOTES:
1. RA: Read Address
2. RD: Read Data
3. PA: The address of the memory location to be programmed.
4. PD: The data at the byte address to be programmed.
5. SA(5): Sector Address
Program Cycle
Address Data Address Data Address Data Address Data Address Data Address Data
5555H AAH 2AAAH 55H 5555H 90H
5555H AAH 2AAAH 55H 5555H A0H PA PD(4)
and the sector erase command (see Table 2). A
sector must be first erased before it can be re-
Second Bus
Program Cycle
Third Bus
Program Cycle
Fourth Bus
Program Cycle
See table 3 for detail.
Fifth Bus
Program Cycle
Six Bus
Program Cycle
data, and the device is then ready for the next
cycle.
written. While in the internal erase mode, the
device ignores any program attempt into the
device. The internal erase completion can be
determined via DATA polling or toggle bit status.
The V29C51002T/V29C51002B is shipped fully
erased (all bits = 1).
Toggle Bit (I/O6)
The V29C51002T/V29C51002B also features
another method for determining the end of a
program cycle. When the device is in the program
cycle, any attempt to read the device will result in
l/O6 toggling between 1 and 0. Once the program is
Chip Erase Cycle
The V29C51002T/V29C51002B features a chip-
erase operation. The chip erase operation is
completed, the toggling will stop. The device is then
ready for the next operation. Examining the toggle
bit may begin at any time during a program cycle.
initiated by using a specific six-bus-cycle
sequence: two unlock program cycles, a setup
command, two additional unlock program cycles,
and the chip erase command (see Table 2).
The automatic erase begins on the rising edge of
the last WE
or CE pulse in the command sequence
and terminates when the data on DQ7 is “1”.
Boot Block Protection Enabling/Disabling
The V29C51002T/V29C51002B features
hardware Boot Block Protection. The boot block
sector protection is enabled when high voltage
(12.5V) is applied to OE and A9 pins with CE pin
LOW and WE pin LOW. The sector protection is
disabled when high voltage is applied to OE, CE
Program Cycle Status Detection
There are two methods for determining the state
and A9 pins with WE pin LOW. Other pins can be
HIGH or LOW. This is shown in table 1.
of the V29C51002T/V29C51002B during a
program (erase/write) cycle: DATA Polling (I/O7)
and Toggle Bit (I/O6).
Autoselect Mode
The V29C51002T/V29C51002B features an
Autoselect mode to identify boot block locking
DATA Polling (I/O7)
The V29C51002T/V29C51002B features DATA
polling to indicate the end of a program cycle.
When the device is in the program cycle, any
attempt to read the device will received the
complement of the loaded data on I/O7. Once the
program cycle is completed, I/O7 will show true
status, device ID and manufacturer ID.
Entering Autoselect mode is accomplished by
applying a high voltage (VH) to the A9 Pin, or
through a sequence of commands (as shown in
table 2). Device will exit this mode once high
voltage on A9 is removed or another command is
loaded into the device.
V29C51002T/V29C51002B Rev. 2.1 October 2000
10
Page 11
MOSEL VITELIC V29C51002T/V29C51002B
Boot Block Protection Status
In Autoselect mode, performing a read at
address location 3CXX2H (V29C51002T) or
0CXX2H (V29C51002B) will indicate boot block
protection status. If the data is 01H, the boot block
is protected. If the data is 00H, the boot block is
unprotected. This is also shown is table 3.
Device ID
In Autoselect mode, performing a read at
address XXX1H will determine whether the device
is a Top Boot Block device or a Bottom Boot Block
device. If the data is 02H, the device is a Top Boot
Block. If the data is A2H, the device is a Bottom
Boot Block device (see Table 3).
Table 3. Autoselect Decoding
Decoding Mode Boot Block
Boot Block Protection Top V
Bottom V
Device ID Top V
Bottom A2H
Manufacture ID V
NOTE:
1. X = Don’t Care, VIH = HIGH, VIL = LOW.
A
0
IL
IL
IH
IL
Manufacturer ID
In Autoselect mode, performing a read at
address XXXX0H will determine the manufacturer
ID. 40H is the manufacturer code for Mosel Vitelic
Flash.
Hardware Data Protection
VCC Detection: the program operation is inhibited
when VCC is less than 3.5V.
Noise Protection: a CE or WE pulse of less than
5ns will not initiate a program cycle.
Program Inhibit: holding any one of OE LOW, CE
HIGH or WE HIGH inhibits a program cycle.
Address
A
1
V
IH
V
IH
V
IL
V
IL
A2–A
XVIH01H: protected
XVIL00H: unprotected
X X 02H
X X 40H
13
A14–A
Data I/O0–I/O
17
7
V29C51002T/V29C51002B Rev. 2.1 October 2000
11
Page 12
MOSEL VITELIC V29C51002T/V29C51002B
Byte Program Algorithm Chip/Sector Erase Algorithm
Write Byte-Write
Command Sequence
Add/Data
5555H/AAH
2AAAH/55H
5555H/A0H
PA/PD
Data Polling or Toggle bit
successfully completed
or t
WTWH (2 or 3)
timeout
Write Erase
Command Sequence
Add/Data
5555H/AAH
2AAAH/55H
Four Bus
Cycle
Sequence
5555H/80H
Six Bus
Cycle
Sequence
5555H/AAH
2AAAH/55H
Writing
Completed
V29C51002T/V29C51002B Rev. 2.1 October 2000
5555H/10H (Chip Erase)
SA/30H (Sector Erase)
Data Polling or Toggle bit
successfully completed
or t
WTWH (2 or 3)
Erase Completed
12
timeout
51002-16
Page 13
MOSEL VITELIC V29C51002T/V29C51002B
DATA Polling Algorithm Toggle Bit Algorithm
No
Read I/O
Address = PBA
I/O7 = Data
7
(1)
Yes
Program
Done
NOTE:
1. PBA: The byte address to be programmed.
Yes
Read I/O
Read I/O
I/O6 Toggle
No
Program
Done
6
6
51002-17
V29C51002T/V29C51002B Rev. 2.1 October 2000
13
Page 14
MOSEL VITELIC V29C51002T/V29C51002B
Package Diagrams
32-pin Plastic DIP
INDEX-1
.050 MAX
.100
TYP
32-pin PLCC
INDEX-2
1.660 MAX.
EJECTOR MARK
+.012
.047
– 0
+.006
.018
– .002
20 19 18 17 16 15 14
21
22
23
24
25
26
27
28
29
30 31 32 1 2 3 4
0.545/0.555
0.010 MIN
+.012
.032
– 0
13
12
11
10
9
8
7
6
5
0.210 MAX
0.120 MIN
.590 ± .005
.550 ± .003
.010
+.004
– .0004
15° MAX
.600 TYP
V29C51002T/V29C51002B Rev. 2.1 October 2000
.450 ± .003
.490 ± .005
.420 ± .003
.045X45°
.050 TYP
14
.017
3° - 6°
.110
.136 ± .003
.046 ± .003
.025
3° - 6°
3° - 6°
30°
Page 15
MOSEL VITELIC V29C51002T/V29C51002B
32-pin TSOP-I
Units in inches
0.787 ± 0.008
Detail “A”
0.005 MIN.
0.007 MAX.
0.724 TYP. (0.728 MAX.)
See Detail “A”
0.032 TYP.
0.315 TYP.
(0.319 MAX.)
SEATING
PLANE
0.020 MAX.
0.010
0.003 MAX
0.024 ± 0.004
0.035 ± 0.002
0.047 MAX.
0.020 SBC
0.009 ± 0.002
V29C51002T/V29C51002B Rev. 2.1 October 2000
15
Page 16
MOSEL VITELIC WORLDWIDE OFFICES V29C51002T/V29C51002B
U.S.A.
3910 NORTH FIRST STREET
SAN JOSE, CA 95134
PHONE: 408-433-6000
FAX: 408-433-0952
HONG KONG
19 DAI FU STREET
TAIPO INDUSTRIAL ESTATE
TAIPO, NT, HONG KONG
PHONE: 852-2666-3307
FAX: 852-2770-8011
NORTHWESTERN
3910 NORTH FIRST STREET
SAN JOSE, CA 95134
PHONE: 408-433-6000
FAX: 408-433-0952
TAIWAN
7F, NO. 102
MIN-CHUAN E. ROAD, SEC. 3
TAIPEI
PHONE: 886-2-2545-1213
FAX: 886-2-2545-1209
NO 19 LI HSIN ROAD
SCIENCE BASED IND. PARK
HSIN CHU, TAIWAN, R.O.C.
PHONE: 886-3-579-5888
FAX: 886-3-566-5888
U.S. SALES OFFICES
SOUTHWESTERN
302 N. EL CAMINO REAL #200
SAN CLEMENTE, CA 92672
PHONE: 949-361-7873
FAX: 949-361-7807
SINGAPORE
10 ANSON ROAD #23-13
INTERNATIONAL PLAZA
SINGAPORE 079903
PHONE: 65-3231801
FAX: 65-3237013
JAPAN
ONZE 1852 BUILDING 6F
2-14-6 SHINTOMI, CHUO-KU
TOKYO 104-0041
PHONE: 03-3537-1400
FAX: 03-3537-1402
CENTRAL,
NORTHEASTERN &
SOUTHEASTERN
604 FIELDWOOD CIRCLE
RICHARDSON, TX 75081
PHONE: 972-690-1402
FAX: 972-690-0341
UK & IRELAND
SUITE 50, GROVEWOOD
BUSINESS CENTRE
STRATHCLYDE BUSINESS
PARK
BELLSHILL, LANARKSHIRE,
SCOTLAND, ML4 3NQ
PHONE: 44-1698-748515
FAX: 44-1698-748516
GERMANY
(CONTINENTAL
EUROPE & ISRAEL)
BENZSTRASSE 32
71083 HERRENBERG
GERMANY
PHONE: +49 7032 2796-0
FAX: +49 7032 2796 22
© Copyright 2000, MOSEL VITELIC Inc.
The information in this document is subject to change without
notice.
MOSEL VITELIC subjects its products to normal quality control
sampling techniques which are intended to provide an assurance
10/00
Printed in U.S.A.
of high quality products suitable for usual commercial applicaMOSEL VITELIC makes no commitment to update or keep current the information contained in this document. No part of this
document may be copied or reproduced in any form or by any
means without the prior written consent of MOSEL-VITELIC.
tions. MOSEL VITELIC does not do testing appropriate to provide
100% product quality assurance and does not assume any liabil-
ity for consequential or incidental arising from any use of its prod-
ucts. If such products are to be used in applications in which
personal injury might occur from failure, purchaser must do its
own quality assurance testing appropriate to such applications.
MOSEL VITELIC 3910 N. First Street, San Jose, CA 95134-1501 Ph: (408) 433-6000 Fax: (408) 433-0952 Tlx: 371-9461
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