The TL062 is a high speed J-FET input dual
operational amplifier. It incorporates well matched,
high voltage J-FET and bipolar transistors in a
monolithic integrated circuit. The device features high
slew rates, low input bias and offset currents, and low
offset voltage temperature coefficient.
FEATURES
*Very low power consumption
*Wide common-mode (up to Vcc+ ) and differential
voltage range
*Low input bias and offset current
*Output short-circuit protection
*High input impedance J-FET input stage
*Internal frequency compensation
*Latch up free operation
*High slew rate: 3.5V/µs(typ)
*Typical supply current: 200µA
SOP-8
DIP-8
PIN CONFIGURATIONS
OUTPUT 1
INVERTING
INPUT 1
NON-
INVERTING
INPUT 1
Vcc-
1
2
3
4
8
Vcc+
7
OUTPUT 2
INVERTING
6
INPUT 2
NON-
5
INVERTING
INPUT 2
UTC UNISONIC TECHNOLOGIES CO., LTD.1
QW-R105-003,A
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UTC TL062LINEAR INTEGRATED CIRCUIT
BLOCK DIAGRAM
ABSOLUTE MAXIMUM RATINGS(Ta=25°C )
Supply Voltage (note 1)Vcc+-18V
Input Voltage (note 2)Vi+-15V
Differential Input Voltage (note 3)Vid+-30V
Power DissipationPtot680mW
Output Short-Circuit Duration (Note 4)Infinite
Operating Free Air TemperatureToper0 to 70
Storage TemperatureTstg-65 to 150
PARAMETER SYMBOLVALUEUNIT
°C
°C
NOTES: 1. All voltage values, except differential voltage, are with respect to the zero reference level (ground) of
2. The magnitude of the input voltage must never exceed the magnitude of the supply voltage or 15 volts,
3. Differential voltages are at the non-inverting input terminal with respect to the inverting input terminal.
4. The output may be shorted to ground or to either supply. Temperature and/or supply voltages must be
the supply voltages where the zero reference level is the midpoint between Vcc- and Vcc+.
whichever is less.
limited to ensure that the dissipation rating is not exceeded.
Temperature Coefficient of Input Offset
Voltage(Rs=50Ω)
Input Offset Current*
Ta=25°C
Tmin<=Ta<=Tmax
Input Bias Current*
Ta=25°C
Tmin<=Ta<=Tmax
Input Common Mode VoltageVicm+-11-12~+15V
Output Voltage Swing(RL=10kΩ,CL=100pF)
Ta=25°C
Tmin<=Ta<=Tmax
Large Signal Voltage Gain(RL=10Ω, Vo=+-
10V) Ta=25°C
Tmin<=Ta<=Tmax
Gain Bandwidth Product(Ta=25°C, RL=10kΩ,
CL=100Pf)
Input ResistanceRi
Common Mode Rejection Ratio(RS=50Ω)
Supply Voltage Rejection Ratio(RS=50Ω)
Supply Current(Ta=25°C, no load, no signal)
Channel Separation(Av=100, Ta=25°C)
Total Power Consumption(Ta=25°C, no load,
f=1KHz)
*The Input bias currents of a FET-input operational amplifier are normal junction reverse currents, which are
temperature sensitive. Pulse techniques must be used that will maintain the junction temperature as closes to the
ambient temperature as possible.
Vio
Dvio10
Iio
Iib
Vopp
20
20
Avd
3
3
GBP1MHz
CMR7076dB
SVR7095dB
Icc200250
V01/V02120dB
PD67.5mW
SR1.53.5
tr0.2
Kov10%
en42
315
20
5200
5
30400
10
27V
6V/mV
1012
mV
µV/°C
pA
nA
pA
nA
µA
V/µs
µs
Ω
UTC UNISONIC TECHNOLOGIES CO., LTD.3
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UTC TL062LINEAR INTEGRATED CIRCUIT
UTC TL062AC ELECTRICAL CHARACTERISTICS( Vcc=+-15V, Ta=25°C, unless otherwise
specified)
PARAMETER SYMBOL MIN TYP MAX UNIT
Input Offset Voltage(Rs=50Ω, Ta=25°C
Tmin<=Ta<=Tmax
Temperature Coefficient of Input Offset
Voltage(Rs=50Ω)
Input Offset Current*
Ta=25°C
Tmin<=Ta<=Tmax
Input Bias Current*
Ta=25°C
Tmin<=Ta<=Tmax
Input Common Mode VoltageVicm+-11.5-12~+15V
Output Voltage Swing(RL=10kΩ)
Ta=25°C
Tmin<=Ta<=Tmax
Large Signal Voltage Gain(RL=10kΩ, Vo=+-
10V) Ta=25°C
Tmin<=Ta<=Tmax
Gain Bandwidth Product(Ta=25°C, RL=10kΩ,
CL=100pF)
Input ResistanceRi
Common Mode Rejection Ratio(RS=50Ω)
Supply Voltage Rejection Ratio(RS=50Ω)
Supply Current(Ta=25°C, no load, no signal)
Channel Separation(Av=100, Ta=25°C)
Total Power Consumption(Ta=25°C, no load,
no signal)
Slew Rate(Vi=10V, RL=10kΩ, CL=100pF,
Av=1)
Rise Time(Vi=20mV, RL=10kΩ, CL=100pF,
Av=1)
Overshoot Factor(Vi=20mV, RL=10kΩ,
CL=100pF, Av=1)
Equivalent Input Noise Voltage(RS=100Ω,
f=1KHz)
*The Input bias currents of a FET-input operational amplifier are normal junction reverse currents, which are
temperature sensitive. Pulse techniques must be used that will maintain the junction temperature as closes to the
ambient temperature as possible.
Vio
Dvio10
Iio
Iib
Vopp
20
20
Avd
4
4
GBP1MHz
CMR8086dB
SVR8095dB
Icc200250
V01/V02120dB
PD67.5mW
SR1.53.5
tr0.2
Kov10%
en42
36
7.5
5100
3
30200
7
27V
6V/mV
1012
mV
µV/°C
pA
nA
pA
nA
µA
V/µs
µs
Ω
UTC UNISONIC TECHNOLOGIES CO., LTD.4
QW-R105-003,A
Page 5
UTC TL062LINEAR INTEGRATED CIRCUIT
UTC TL062BC ELECTRICAL CHARACTERISTICS( Vcc=+-15V, Ta=25°C, unless otherwise
specified)
PARAMETER SYMBOL MIN TYP MAX UNIT
Input Offset Voltage(Rs=50Ω, Ta=25°C
Tmin<=Ta<=Tmax
Temperature Coefficient of Input Offset
Voltage(Rs=50Ω)
Input Offset Current*
Ta=25°C
Tmin<=Ta<=Tmax
Input Bias Current*
Ta=25°C
Tmin<=Ta<=Tmax
Input Common Mode VoltageVicm+-11-12~+15V
Output Voltage Swing(RL=10kΩ)
Ta=25°C
Tmin<=Ta<=Tmax
Large Signal Voltage Gain(RL=10kΩ, Vo=+-
10V) Ta=25°C
Tmin<=Ta<=Tmax
Gain Bandwidth Product(Ta=25°C, RL=10kΩ,
CL=100pF)
Input ResistanceRi
Common Mode Rejection Ratio(RS=50Ω)
Supply Voltage Rejection Ratio(RS=50Ω)
Supply Current(Ta=25°C, no load, no signal)
Channel Separation(Av=100, Ta=25°C)
Total Power Consumption(Ta=25°C, no load,
no signal)
Slew Rate(Vi=10V, RL=10kΩ, CL=100pF,
Av=1)
Rise Time(Vi=20mV, RL=10kΩ, CL=100pF,
Av=1)
Overshoot Factor(Vi=20mV, RL=10kΩ,
CL=100pF, Av=1)
Equivalent Input Noise Voltage(RS=100Ω,
f=1KHz)
*The Input bias currents of a FET-input operational amplifier are normal junction reverse currents, which are
temperature sensitive. Pulse techniques must be used that will maintain the junction temperature as closes to the
ambient temperature as possible.
Vio
Dvio10
Iio
Iib
Vopp
20
20
Avd
4
4
GBP1MHz
CMR8086dB
SVR8095dB
Icc200250
V01/V02120dB
PD67.5mW
SR1.53.5
tr0.2
Kov10%
en42
23
5
5100
3
30200
7
27V
6V/mV
1012
mV
µV/°C
pA
nA
pA
nA
µA
V/µs
µs
Ω
UTC UNISONIC TECHNOLOGIES CO., LTD.5
QW-R105-003,A
Page 6
UTC TL062LINEAR INTEGRATED CIRCUIT
UTC UNISONIC TECHNOLOGIES CO., LTD.6
QW-R105-003,A
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UTC TL062LINEAR INTEGRATED CIRCUIT
UTC UNISONIC TECHNOLOGIES CO., LTD.7
QW-R105-003,A
Page 8
UTC TL062LINEAR INTEGRATED CIRCUIT
PARAMETER MEASUREMENT INFORMATION
UTC UNISONIC TECHNOLOGIES CO., LTD.8
QW-R105-003,A
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