Datasheet UTCLAG665F Datasheet (UTC)

UTC LAG665F LINEAR INTEGRATED CIRCUIT
RADIO AND CASSETTE RECORDER CIRCUIT
DESCRIPTION
The UTC LAG665F is a monolithic integrated circuit, designed for portable radio cassette.
FEATURES
*1-Chip stereo tape recorder with motor speed controller. *Operating supply voltage range: Vcc=2~5V *Good volume control
SOP-28
BLOCK DIAGRAM
25 24 23 22 21 19 20 18 14 17 16 15 13
2627
Power Amp
Motor
1/2 Vcc
Power Amp
8283 4 5
9 11 10 12
Control
Power Amp
1/2 Vcc
1 2
Pre Amp
Bias Control
Pre Amp
Attenuator
V/I
Attenuator
6 7
UTC UNISONIC TECHNOLOGIES CO., LTD.
QW-R110-013,A
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UTC LAG665F LINEAR INTEGRATED CIRCUIT
PIN CONFIGURATION
V
BPRE
1IN+ 1IN­INF
PRF
PRE
IOUT
ATT1 CON
VOL
V
REF
1OUT
P
GND
P
V
BP
GND
MD
V
CON
MO
ON
PIN NO. SYMBOL DESCRIPTION PIN NO. SYMBOL DESCRIPTION
1 VBPRE Pre Amp Bias Voltage 15 CONS Speed Control 2 1 IN+ Channel 1 “+” Input 16 CONT Torqul Control 3 1 IN - Channel 1 “-” Input 17 VCCMO Motor Power Control 4 1 NFPRE Feedback 1 18 MOOFF Motor Forced Stop 5 1 OUTPRE Pre Amp Output 1 19 2 OUTP Power Amp Output 2 6 ATT 1 Attenuator 1 20 VCC Supply Voltage 7 CONVOL Volume Control 21 VCCPRE Supply Voltage 8 VREF Reference Voltage 22 PREOFF Pre Amp Off
9 1 OUTP Power Amp Output 1 23 ATT 2 Attenuator 2 10 GNDP Power GND 24 2 OUTPRE Pre Amp Output 2 11 VBP Power Amp Bias
12 GNDMD Motor GND 26 2 IN- Channel 2 “ -” Input 13 VCON Motor Control Voltage 27 2 IN+ Channel 2 “+” Input 14 MOON Motor Forced Start 28 GNDPRE Pre GND
10 11 12 13 14
Voltage
1 2 3 4 5 6 7 8 9
28 27 26 25 24 23 22 21 20 19 18 17 16 15
GND 2IN+
2IN­2NF 2OUT ATT2 PRE
V V 2OUT
MO
V CON CON
PRE
PRE
PRE
OFF
CCPRE
CC
P
OFF
CCMO
T
S
25 2 NFPRE Feedback 2
UTC UNISONIC TECHNOLOGIES CO., LTD.
QW-R110-013,A
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UTC LAG665F LINEAR INTEGRATED CIRCUIT
ABSOLUTE MAXIMUM RATINGS(Ta=25°C)
PARAMETER SYMBOL VALUE UNIT
Supply Voltage Vcc -0.3~+7.5 V Power Dissipation Pd 450 mW Operating Voltage Vop 2~5 V Operating Temperature Topr -20~+65 °C Storage Temperature Tstg -40~+125 °C
ELECTRICAL CHARACTERISTICS(Ta=25°C,Vcc=3V, f=1kHz, RL=16, unless otherwise specified)
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
Supply Current Icc Vin=0V, IM=0mA 18 25 mA PRE-AMPLIFIER Open Loop Gain Gvo Vo=-10dBm, RL= 72 dB Close Loop Gain Gvc Vo=-10dBm 40 42 44 dB Maximum Output Voltage Vom THD=10% 0.45 0.6 Vrms Total Harmonic Distortion THD Vout=100mVrms 0.05 0.5 % Output Noise Voltage Von Vin=0, Rg=2.2k,
BPF(30~20k) Input Impedance Zin Vout=-10dBm 18 22 k Cross Talk between CH CT Rg=2.2k, Vout=-10dBm 30 dB Pre Amp Output Voltage when Pre-Off Vooff Vin=100mVrms -50 dB Output Impedance when Pre-Off Rooff 10 k Input Impedance when Pre-Off Rioff 10 K Attenuator Maximum Input Voltage Vimax 0.2 Vrms Maximum Attenuation Vamax Vcont=Min 66 dB Attenuation Error Vaerr Vcont=Max 0 dB Input Impedance Zia 15 20 k Control Ternimal Input Impedance Power Amplifier Voltage Gain GV Pout=5mW 26 28 30 dB Channel Voltage Difference ∆GV Vcont=Max 0 3 dB Maximum Output Power I Pom 1 THD=10%, RL=32 20 28 mW Maximum Output Power II Pom 2 THD=10%, RL=16 30 mW Total Harmonic Distortion THD Pout=5mW 0.2 2 % Cross Talk between CH CT Pout=5mW 20 30 dB Output Noise Voltage Von Rg=2.2k, Vcont=Min 0.25 1 mVrms Ripple Rejection RR Vcc=3V, 100Hz, 100mVp-p 34 40 dB Pre + Pulse Boost + Power Noise Motor *Vcc=3V, Im=100mA Current Consumption IMC 3 5 mA Starting Current IMS 500 mA Reference Voltage Vref Pin 15~Pin 16 0.72 0.8 0.87 V
Zicot 100 k
Vnto Vin=0V, Rg=2.2k,
Vcont=Max*
150 300 µVrms
6 9 mVrms
UTC UNISONIC TECHNOLOGIES CO., LTD.
QW-R110-013,A
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UTC LAG665F LINEAR INTEGRATED CIRCUIT
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
Reference Voltage Change I Vref 1 Vcc=2.1~5V 0.05 %/V Reference Voltage Change II Vref 2 Im=25~250mA 0.01 %/mA Reference Voltage Change III Vref 3 Ta=-10~50°C 0.01 %/°C Current Factor K 32 38 43 Current Factor Change I K 1 Vcc=2.1~5V 0.5 %/V Current Factor Change II K 2 Im=25~250mA 0.05 %/mA Current Factor Change III K 3 Ta=-10~50°C 0.02 %/°C Saturation Voltage at Forced ON VCEsa IM=200mA, Pin 14=Vcc 0.6 V Input Impedance at Forced ON Pin Leakage Current at Forced OFF IML 200 µA Input Impedance at Forced OFF Pin
TEST CIRCUIT
Rion 5.6 K
Ricon 33 K
NOTE1 : SW12,SW12 R1,R’ =33k
R2,R2’ =5.1k R3,R3’ =200k R2,R2,=5.1k C1,C’ =0.1µF
NOTE2 : See figure 1 for SW
UTC UNISONIC TECHNOLOGIES CO., LTD.
QW-R110-013,A
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UTC LAG665F LINEAR INTEGRATED CIRCUIT
FIGURE 1
Item Symbol SW No. TEST CONDITION
1 2 3,3’ 4 5 6 7 8 9 10 11 Vcc=3V,f=1kHz,RL=16
AMP Supply Current Icc
Close Loop Gain Gvc
Maximum Output Voltage Vom
Total Harmonic Distortion THD
Output Noise Voltage Von
Cross Talk between CH CT
c c a b b a b b b a a
b b b b b a b b b a a Im=0mA
b b b b b a b b b a a Vo=244mV
b b b b b a b b b a a Vo=400mV
c c b b b a b b b a a B.P.F.(30-20kHz)
b/cc/bb b b a b b b a a Vo=244mV
Output Voltage when Pre­Off
Attenuator Maximum Input Voltage Vimax
Maximum Attenuation Vamax
Power AMP
Voltage Gain Channel Voltage Difference ∆GV
Maximum Output Power I Pom 1
Maximum Output Power II Pom 2
Vooff
GV
b b b a b a b b b a a Vin=100mV
a a a a b a b b b a a Vr=Min, THD=10%,
a a a a b a b b b a a
a a a a b a b b b a a Pout=5mV
a a a a b a b b b a a VR=MAX
a a a a b b a b b a a RL=32,THD=10%
a a a a b a b b b a a RL=16,THD=10%
UTC UNISONIC TECHNOLOGIES CO., LTD.
QW-R110-013,A
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