Datasheet UT62V25616MC-70LLI, UT62V25616MC-70LI, UT62V25616MC-100LLI, UT62V25616MC-100LI, UT62V25616BS-70LLI Datasheet (UTRON)
...Page 1
UTRON
UT62V25616(I)
Rev. 1.1
256K X 16 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80067
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
1
FEATURES
Fast access time : 70/100 ns
CMOS Low operating power
Operating current: 30/20mA (Icc max)
Standby current: 20 uA(TYP.) L-version
2 uA(TYP.) LL-version
Single 2.3V~2.7V power supply
Operating temperature:
Industrial : -40℃~85℃
All inputs and outputs TTL compatible
Fully static operation
Three state outputs
Data retention voltage: 1.5V (min)
Data byte control :
LB
(I/O1~I/O8)
UB
(I/O9~I/O16)
Package : 44-pin 400mil TSOPⅡ
48-pin 6mm × 8mm TFBGA
FUNCTIONAL BLOCK DIAGRAM
MEMORY ARRAY
2048 Rows x 128 Columns x 16 bits
COLUMN I/O
COLUMN DECODER
I/O
CONTROL
LOGIC
CONTROL
I/O1
VSS
VCC
I/O16
.
.
.
.
.
.
. .
.
A
10
A
11
A
5
. . .
.
.
A9
ROW
DECODER
A0 A1 A2 A3 A4 A8 A
17
A
13
A
14
A
15
A
16
A7 A6
LB
UB
WE
OE
CE
A
12
GENERAL DESCRIPTION
The UT62V25616(I) is a 4,194,304-bit low power
CMOS static random access memory organized as
262,144 words by 16 bits.
The UT62V25616(I) operates from a single 2.3V ~
2.7V power supply and all inputs and outputs are fully
TTL compatible.
The UT62V25616(I) is designed for low power
system applications. It is particularly suited for use
in high-density high-speed system applications.
PIN DESCRIPTION
SYMBOL DESCRIPTION
A0 - A17 Address Inputs
I/O1 - I/O16 Data Inputs/Outputs
CE
Chip Enable Input
WE
Write Enable Input
OE
Output Enable Input
LB
Lower-Byte Control
UB
High-Byte Control
VCC Power Supply
VSS Ground
NC No Connection
Page 2
UTRON
UT62V25616(I)
Rev. 1.1
256K X 16 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80067
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
2
PIN CONFIGURATION
A1
A2
A3
A4
I/O16
I/O1
I/O2
I/O3
Vcc
Vss
A12
A17
I/O15
I/O13
I/O14
I/O12
Vss
Vcc
I/O11
I/O10
I/O4
I/O5
UT62V25616
TSOP II
28
14
13
12
11
10
9
8
7
6
5
4
3
2
1
17
16
15
20
19
18
22 23
24
25
26
27
21
CE
OE
A16
A0
I/O7
I/O8
A5
A6
A7
A8
A9
I/O6
I/O9
A15
A14
A13
A10
WE
NC
34
29
30
31
32
33
44
39
40
41
42
43
35
36
37
38
UB
LB
A11
OE
CE
WE
LB
UB
A12
A11
A13
NC
I/O9
A10
A14
I/O11I/O10
A15 I/O6
I/O7
I/O8
A9
Vss
I/O12
A8
A16 I/O5
Vcc
Vcc
I/O4A17
NC
I/O13
Vss
NC
A7
A0
I/O3I/O2
I/O15 I/O14
I/O1
NC
A6
A1
A3
A5
NC
I/O16
A4
A2
123456
H
G
C
D
E
F
A
B
TFBGA
TRUTH TABLE
WE
I/O OPERATION
MODE
CE
OE
LB
UB
I/O1-I/O8 I/O9-I/O16
SUPPLY CURRENT
H X X X X High – Z High – Z ISB, I
SB1
Standby
X X X H H High – Z High – Z I
SB
, I
SB1
Output
Disable
L
L
H
H
H
H
X
L
L
X
High – Z
High – Z
High – Z
High – Z
ICC,I
CC1,ICC2
Read L
L
L
L
L
L
H
H
H
L
H
L
H
L
L
D
OUT
High – Z
D
OUT
High – Z
D
OUT
D
OUT
I
CC,ICC1,ICC2
Write L
L
L
X
X
X
L
L
L
L
H
L
H
L
L
DIN
High – Z
D
IN
High – Z
D
IN
DIN
I
CC,ICC1,ICC2
Note: H = VIH, L=VIL, X = Don't care.
Page 3
UTRON
UT62V25616(I)
Rev. 1.1
256K X 16 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80067
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
3
ABSOLUTE MAXIMUM RATINGS
*
PARAMETER SYMBOL RATING UNIT
Terminal Voltage with Respect to VSS V
TERM
-0.3 to 3.6 V
Operating Temperature Industrial T
A
-40 to 85
℃
Storage Temperature T
STG
-65 to +150
℃
Power Dissipation PD 1 W
DC Output Current I
OUT
50 mA
Soldering Temperature (under 10 secs) Tsolder 260
℃
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC = 2.3V~2.7V, TA = -40℃ to 85℃(I))
PARAMETER
SYMBOL
TEST CONDITION MIN. TYP. MAX. UNIT
Power Voltage VCC 2.3 2.5 2.7 V
Input High Voltage VIH 2.0 - VCC+0.3 V
Input Low Voltage VIL -0.2 - 0.6 V
Input Leakage Current ILI
V
SS
≦VIN ≦VCC
- 1 - 1
µ
A
Output Leakage Current ILO
V
SS
≦V
I/O
≦V
CC;
Output Disabled
- 1 - 1
µ
A
Output High Voltage VOH IOH= -0.5mA 2.0 - - V
Output Low Voltage VOL IOL= 0.5mA - - 0.4 V
70 - 20 30 mA Operating Power
Supply Current
ICC Cycle time=min, 100%duty,
I/O=0mA,
CE
=V
IL
;
100 - 15 20 mA
Icc1
Cycle time=1µs,100%duty,I/O=0mA,
CE
≦
0.2V,other pins at 0.2V or Vcc-0.2V,
- 3 4 mA
Average Operation
Current
Icc2 Cycle time=500ns,100%duty,I/O=0mA,
CE
≦
0.2V,other pins at 0.2V or Vcc-0.2V,
- 6 8 mA
Standby Current (TTL) ISB
CE
=V
IH,
other pins =VIL or VIH,
- 0.3 0.5 mA
Standby Current (CMOS) -L - 20 80
µ
A
I
SB1
CE
=V
CC
-0.2V,
other pins at 0.2V or Vcc-0.2V,
-LL - 2 15
µ
A
Page 4
UTRON
UT62V25616(I)
Rev. 1.1
256K X 16 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80067
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
4
CAPACITANCE
(TA=25℃, f=1.0MHz)
PARAMETER SYMBOL MIN. MAX UNIT
Input Capacitance C
IN
-
6 pF
Input/Output Capacitance C
I/O
-
8 pF
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS
Input Pulse Levels 0V to 2.2V
Input Rise and Fall Times 5ns
Input and Output Timing Reference Levels 1.2V
Output Load CL = 30pF, IOH/IOL = -0.5mA / 0.5mA
AC ELECTRICAL CHARACTERISTICS
(VCC =2.3V~2.7V, TA = -40℃ to 85℃(I))
(1) READ CYCLE
PARAMETER
SYMBOL UT62V25616(I)-70 UT62V25616(I)-100 UNIT
MIN. MAX. MIN. MAX.
Read Cycle Time
tRC 70 - 100 - ns
Address Access Time
tAA - 70 - 100 ns
Chip Enable Access Time
t
ACE
- 70 - 100 ns
Output Enable Access Time
tOE - 35 - 50 ns
Chip Enable to Output in Low Z
t
CLZ*
10 - 10 - ns
Output Enable to Output in Low Z
t
OLZ*
5 - 5 - ns
Chip Disable to Output in High Z
t
CHZ*
- 25 - 30 ns
Output Disable to Output in High Z
t
OHZ*
- 25 - 30 ns
Output Hold from Address Change
tOH 5 - 5 - ns
LB
,UB
Access Time
tBA - 70 - 100 ns
LB
,UB
to High-Z Output
t
HZB
- 30 - 40 ns
LB
,UB
to Low-Z Output
t
LZB
0 - 0 - ns
(2) WRITE CYCLE
PARAMETER
SYMBOL UT62V25616(I)-70 UT62V25616(I)-100 UNIT
MIN. MAX. MIN. MAX.
Write Cycle Time
tWC 70 - 100 - ns
Address Valid to End of Write
tAW 60 - 80 - ns
Chip Enable to End of Write
tCW 60 - 80 - ns
Address Set-up Time
tAS 0 - 0 - ns
Write Pulse Width
tWP 55 - 70 - ns
Write Recovery Time
tWR 0 - 0 - ns
Data to Write Time Overlap
tDW 30 - 40 - ns
Data Hold from End of Write Time
tDH 0 - 0 - ns
Output Active from End of Write
t
OW*
5 - 5 - ns
Write to Output in High Z
t
WHZ*
- 30 - 40 ns
LB
,UB
Valid to End of Write
tBW 60 - 80 - ns
*These parameters are guaranteed by device characterization, but not production tested.
Page 5
UTRON
UT62V25616(I)
Rev. 1.1
256K X 16 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80067
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
5
TIMING WAVEFORMS
READ CYCLE 1
(Address Controlled)
(1,2,4)
t
RC
Address
DOUT Data Valid
t
AA
t
OH
t
OH
READ CYCLE 2
(CE and
OE
Controlled)
(1,3,5,6)
t
RC
t
AA
t
ACE
t
BLZ
t
OE
t
CHZ
t
OHZ
t
CLZ
t
BHZ
t
OH
t
OLZ
HIGH-Z
Data Valid
HIGH-Z
Address
CE
LB , UB
OE
Dout
t
BA
Notes :
1.
WE
is HIGH for read cycle.
2. Device is continuously selected
CE
=V
IL.
3. Address must be valid prior to or coincident with
CE
transition; otherwise t
AA
is the limiting parameter.
4.
OE
is LOW.
5. t
CLZ
, t
OLZ
, t
CHZ
and t
OHZ
are specified with CL = 5pF. Transition is measured ±500mV from steady state.
6. At any given temperature and voltage condition, t
CHZ
is less than t
CLZ
, t
OHZ
is less than t
OLZ.
Page 6
UTRON
UT62V25616(I)
Rev. 1.1
256K X 16 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80067
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
6
WRITE CYCLE 1
(
WE
Controlled)
(1,2,3,5)
t
WC
t
AW
t
CW
t
AS
t
WP
t
BW
t
WHZ
t
OW
t
DW
t
DH
t
WR
Address
CE
WE
LB , UB
Dout
Din
Data Valid
High-Z
(4) (4)
WRITE CYCLE 2
(
CE
Controlled)
(1,2,5)
t
WC
t
AW
t
CW
t
AS
t
WR
t
WP
t
BW
t
WHZ
t
DW
t
DH
Data Valid
Address
CE
WE
LB , UB
Dout
Din
High-Z
Notes :
1.
WE
or
CE
must be HIGH during all address transitions.
2. A write occurs during the overlap of a low
CE
and a low
WE
.
3. During a
WE
controlled with write cycle with
OE
LOW, t
WP
must be greater than t
WHZ+tDW
to allow the drivers to turn off and data
to be placed on the bus.
4. During this period, I/O pins are in the output state, and input signals must not be applied.
5. If the CE
LOW
transition occurs simultaneously with or after WE
LOW
transition, the outputs remain in a
high impedance state.
6. t
OW
and t
WHZ
are specified with CL = 5pF. Transition is measured ±500mV from steady state.
Page 7
UTRON
UT62V25616(I)
Rev. 1.1
256K X 16 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80067
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
7
DATA RETENTION CHARACTERISTICS
(TA =
-40℃ to 85℃(I)
)
PARAMETER SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT
Vcc for Data Retention
V
DR
CE
≧ V
CC
-0.2V
1.5 - - V
Data Retention Current
I
DR
Vcc=1.5V
- L - 1 50
µ
A
CE
≧ V
CC
-0.2V
- LL - 0.5 15
µ
A
Chip Disable to Data
t
CDR
See Data Retention 0 - - ms
Retention Time
Waveforms (below)
Recovery Time
t
R
5 - - ms
DATA RETENTION WAVEFORM
t
CDR
t
R
2.7V
VCC
CE
VSS
Data Retention Mode
V
DR
≧ 1.5V
CE ≧ V
CC
-0.2V
2.7V
Page 8
UTRON
UT62V25616(I)
Rev. 1.1
256K X 16 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80067
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
8
PACKAGE OUTLINE DIMENSION
44pin 400mil TSOP-Ⅱ PACKAGE OUTLINE DIMENSION
θ
DIMENSIONS IN MILLMETERS DIMENSIONS IN INCHS SYMBOLS
MIN NOM MAX. MIN. NOM. MAX.
A 1.00 - 1.20 0.039 - 0.047
A1 0.05 - 0.15 0.002 - 0.006
A2 0.95 1.00 1.05 0.037 0.039 0.041
b 0.30 0.35 0.45 0.012 0.014 0.018
c 0.12 - 0.21 0.0047 - 0.083
D 18.313 18.415 18.517 0.721 0.725 0.728
E 11.854 11.836 11.838 0.460 0.466 0.470
E1 10.058 10.180 10.282 0.398 0.400 0.404
e - 0.800 - - 0.0315 L 0.40 0.50 0.60 0.0157 0.020 0.0236
2D - 0.805 - - 0.0317 -
y 0.00 - 0.076 0.000 - 0.003
Θ
0
o
- 5o 0
o
- 5o
Page 9
UTRON
UT62V25616(I)
Rev. 1.1
256K X 16 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80067
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
9
48-pin 6mm×8mm TFBGA PACKAGE OUTLINE DIMENSION
Page 10
UTRON
UT62V25616(I)
Rev. 1.1
256K X 16 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80067
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
10
ORDERING INFORMATION
INDUSTRIAL TEMPERATURE
PART NO. ACCESS TIME
(ns)
STANDBY CURRENT
(µA) TYP.
PACKAGE
UT62V25616MC-70LI 70 20
44 PIN TSOP-Ⅱ
UT62V25616MC-70LLI 70 2
44 PIN TSOP-Ⅱ
UT62V25616MC-100LI 100 20
44 PIN TSOP-Ⅱ
UT62V25616MC-100LLI 100 2
44 PIN TSOP-Ⅱ
UT62V25616BS-70LI 70 20 48 PIN TFBGA
UT62V25616BS-70LLI 70 2 48 PIN TFBGA
UT62V25616BS-100LI 100 20 48 PIN TFBGA
UT62V25616BS-100LLI 100 2 48 PIN TFBGA
Page 11
UTRON
UT62V25616(I)
Rev. 1.1
256K X 16 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80067
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
11
REVISION HISTORY
REVISION DESCRIPTION DATE
Preliminary Rev. 0.1 Original. Mar, 2001
Rev. 1.0
1. The symbols CE# and OE# and WE# are revised as.
CE
and
OE and
WE
.
2. Separate Industrial and Consumer SPEC.
Aug 7,2001
Rev. 1.1
1. Revised PIN CONFIGURATION :
Rev 1.0 : No A17 pintyping error
Rev 1.1 : add A17 pin.
Oct 18,2001
Page 12
UTRON
UT62V25616(I)
Rev. 1.1
256K X 16 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80067
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
12
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