Datasheet UT62L25716BS-55LLE, UT62L25716BS-55LL, UT62L25716BS-55LE, UT62L25716BS-55L, UT62L25716BS-70LLE Datasheet (UTRON)

UTRON

UT62L25716

Rev. 1.0

256K X 16 BIT LOW POWER CMOS SRAM

UTRON TECHNOLOGY INC. P80047

1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.

TEL: [phone] FAX: [phone]

1



FEATURES



High speed access time :

55ns(max) for Vcc=3.0V~3.6V
70/100 ns(max) for Vcc=2.7V~3.6V



CMOS Low power consumption



Operation current : 45/35/25 (Icc,max.)



Standby: 20uA (TYP.) L-version

3uA (TYP.) LL-version



Single 2.7V~3.6V power supply



Operation temperature:

Commercial : 0℃~70

℃

Extended : -20℃~80

℃



All inputs and outputs are TTL compatible



Fully static operation



Three state outputs



Data retention voltage:1.5V (min.)



Data byte control :

LB

(I/O1~I/O8)

UB

(I/O9~I/O16)



Package : 48-pin 6mm × 8mm TFBGA

FUNCTIONAL BLOCK DIAGRAM

MEMORY ARRAY

2048 Rows x 128 Columns x 16 bits

COLUMN I/O

COLUMN DECODER

I/O

CONTROL

LOGIC

CONTROL

I/O1

VSS

VCC

I/O16

.

.

.

.
.

.

. .

.

A

10

A

11

A5 A

7

. . .

.

.

A9

ROW

DECODER

A0 A1 A

2

A3 A4 A

8

A

13

A

14

A

15

A

16

A

17

A6

LB

UB

WE

OE

1CE

A12

CE2

GENERAL DESCRIPTION

The UT62L25716 is a 4,194,304-bit low power
CMOS static random access memory organized as
262,144 words by 16 bits.

The UT62L25716 operates from a single 2.7V ~

3.6V power supply and all inputs and outputs are
fully TTL compatible.

The UT62L25716 is designed for low power system
applications. It is particularly well suited for use in
high-density low power system applications.

PIN DESCRIPTION

SYMBOL DESCRIPTION

A0 - A17 Address Inputs
I/O1 - I/O16 Data Inputs/Outputs

1CE

, CE2

Chip Enable Input

WE

Write Enable Input

OE

Output Enable Input

LB

Lower-Byte Control

UB

High-Byte Control

Vcc Power Supply
Vss Ground
NC No Connection

PIN CONFIGURATION

OE

1CE

WE

LB

UB

A12

A11

A13

CE2

I/O9

A10

A14

I/O11I/O10

A15 I/O6 I/O7

I/O8

A9

Vss

I/O12

A8

A16 I/O5

Vcc

Vcc

I/O4A17

NC

I/O13

Vss

NC

A7

A0

I/O3I/O2

I/O15 I/O14

I/O1

NC

A6

A1

A3

A5

NC

I/O16

A4

A2

123456

H

G

C

D

E

F

A

B

TFBGA

UTRON

UT62L25716

Rev. 1.0

256K X 16 BIT LOW POWER CMOS SRAM

UTRON TECHNOLOGY INC. P80047

1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.

TEL: [phone] FAX: [phone]

2



ABSOLUTE MAXIMUM RATINGS

*

PARAMETER SYMBOL RATING UNIT

Terminal Voltage with Respect to V

SS

V

TERM

-0.3 to 4.6 V

Commercial T

A

0 to 70

℃

Operating Temperature

Extended T

A

-20 to 80

℃

Storage Temperature T

STG

-65 to 150

℃

Power Dissipation P

D

1.0~1.5 W

DC Output Current I

OUT

20 mA

Soldering Temperature (under 10 secs) Tsolder 260.10

℃.sec

*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.

TRUTH TABLE

MODE

1

CE

CE2

OE

WE LB

UB

I/O1-I/O8 I/O9-I/O16

SUPPLY CURRENT

H X X X X X High – Z High – Z ISB, I

SB1

X L X X X X High – Z High – Z ISB, I

SB1

Standby

XXXXH HHigh – ZHigh – Z I

SB

, I

SB1

Output
Disable

L
L

H
H

H
H

H
H

L
X

XLHigh – Z

High – Z

High – Z
High – Z

I

CC1,ICC2

Read L

L
L

H
H
H

L
L
L

H
H
H

L

H

L

H

L
L

D

OUT

High – Z
D

OUT

High – Z
D

OUT

D

OUT

I

CC1,ICC2

Write L

L
L

H
H
H

X
X
X

L
L
L

L

H

L

H

L
L

D

IN

High – Z
D

IN

High – Z
D

IN

D

IN

I

CC1,ICC2

Note: H = VIH, L=VIL, X = Don't care.(Must be low or high state)

DC ELECTRICAL CHARACTERISTICS

(Vcc = 2.7V~3.6V, TA = 0℃ to 70℃ / -20℃ to 80℃(E))

PARAMETER

SYMBOL

TEST CONDITION

MIN. TYP. MAX. UNIT

Power Voltage Vcc

2.7 3.0 3.6

V

Input High Voltage V

IH

2.0 - Vcc+0.3

V

Input Low Voltage V

IL

- 0.2 - 0.6

V

Input Leakage Current I

LI

VSS ≦VIN ≦Vcc

- 1 - 1

µA

Output Leakage Current I

LO

VSS ≦V

I/O

≦Vcc, Output Disabled

- 1 - 1

µA

Output High Voltage V

OH

IOH= - 1.0mA

2.2 - -

V

Output Low Voltage V

OL

IOL= 2.1mA

--0.4

V

55

-30 45

mA

70

-25 35

mA

I

CC

Cycle time =min,100% duty, I

I/O

=0mA,

CE2=V

IH

,

1CE

=V

IL, VIN=VIH

or VIL,

100

-

20 25

mA

Icc1 Cycle time = 1us,100% duty, I

I/O

=0mA,

1CE

≦

0.2V, CE2≧Vcc-0.2V

other pins at 0.2V or Vcc-0.2V,

-4 5

mA

Operating Power

Supply Current

Icc2 Cycle time =500ns,100% duty, I

I/O

=0mA,

1CE

≦

0.2V, CE2≧Vcc-0.2V

other pins at 0.2V or Vcc-0.2V,

-8 10

mA

Standby Current I

SB

1CE

=V

IH,

or CE2=VIH,other pins =VIH or VIL,

-0.30.5

mA

-L

-20 80

µAStandby Current I

SB1

1CE

≧

V

CC

-0.2V,or CE2 ≦0.2V,

other pins at 0.2V or Vcc-0.2V,

-LL

-3 25

µA

UTRON

UT62L25716

Rev. 1.0

256K X 16 BIT LOW POWER CMOS SRAM

UTRON TECHNOLOGY INC. P80047
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: [phone] FAX: [phone]

3



CAPACITANCE

(TA=25℃, f=1.0MHz)

PARAMETER SYMBOL MIN. MAX UNIT

Input Capacitance C

IN

-

6pF

Input/Output Capacitance C

I/O

-

8pF

Note : These parameters are guaranteed by device characterization, but not production tested.

AC TEST CONDITIONS

Input Pulse Levels 0V to 3.0V
Input Rise and Fall Times 5ns
Input and Output Timing Reference Levels 1.5V
Output Load CL = 30pF, IOH/IOL = -1mA/2mA

AC ELECTRICAL CHARACTERISTICS

(VCC = 2.7V~3.6V , TA = 0℃ to 70℃ / -20℃ to 80℃(E))

(1) READ CYCLE

PARAM E TER

SYMBOL UT62L25716-55* UT62L25716-70 UT62L25716-100 UNIT

MIN. MAX. MIN. MAX. MIN. MAX.

Read Cycle Time

t

RC

55 - 70 - 100 - ns

Address Access Time

t

AA

- 55 - 70 - 100 ns

Chip Enable Access Time

t

ACE

- 55 - 70 - 100 ns

Output Enable Access Time

t

OE

-30-35-50ns

Chip Enable to Output in Low Z

t

CLZ*

10 - 10 - 10 - ns

Output Enable to Output in Low Z

t

OLZ*

5-5-5-ns

Chip Disable to Output in High Z

t

CHZ*

-20-25-30ns

Output Disable to Output in High Z

t

OHZ*

-20-25-30ns

Output Hold from Address Change

t

OH

5-5-5-ns

LB

,UB

Access Time

t

BA

- 55 - 70 - 100 ns

LB

,UB

to High-Z Output

t

HZB

-25- 30040ns

LB

,UB

to Low-Z Output

t

LZB

0-0-0-ns

(2) WRITE CYCLE

PARAM E TER

SYMBOLUT62L25716-55* UT62L25716-70 UT62L25716-100 UNIT

MIN. MAX. MIN. MAX. MIN. MAX.

Write Cycle Time

t

WC

55 - 70 - 100 - ns

Address Valid to End of Write

t

AW

50 - 60 - 80 - ns

Chip Enable to End of Write

t

CW

50 - 60 - 80 - ns

Address Set-up Time

t

AS

0-0-0-ns

Write Pulse Width

t

WP

45 - 55 - 70 - ns

Write Recovery Time

t

WR

0-0-0-ns

Data to Write Time Overlap

t

DW

25 - 30 - 40 - ns

Data Hold from End of Write Time

t

DH

0-0-0-ns

Output Active from End of Write

t

OW*

5-5-5-ns

Write to Output in High Z

t

WHZ*

-30-30-40ns

LB

,UB

Valid to End of Write

t

PWB

45 - 60 - 80 - ns

* These parameters are guaranteed by device characterization, but not production tested.
* 55ns for 3.0V~3.6V.

UTRON

UT62L25716

Rev. 1.0

256K X 16 BIT LOW POWER CMOS SRAM

UTRON TECHNOLOGY INC. P80047
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: [phone] FAX: [phone]

4



TIMING WAVEFORMS

READ CYCLE 1

(Address Controlled)

(1,2,4)

t

RC

Address

DOUT Data Valid

t

AA

t

OH

t

OH

READ CYCLE 2

(

1CE

and CE2

and

OE

Controlled)

(1,3,5,6)

t

RC

t

AA

t

ACE1

t

ACE2

t

BLZ

t

OE

t

CHZ1

t

CHZ2

t

OHZ

t

CLZ1

t

CLZ2

t

BHZ

t

OH

t

OLZ

HIGH-Z

Data Valid

HIGH-Z

Address

CE1

CE2

LB , UB

OE

Dout

Notes :

1.

WE

is HIGH for read cycle.

2. Device is continuously selected

CE1

=V

IL

and CE2=V

IH.

and

LB

=VIL and

UB

=V

IH.

3. Address must be valid prior to or coincident with

CE1

and CE2 and

LB

and

UB

transition; otherwise t

AA

is the limiting parameter.

4.

OE

is low.

5. t

CLZ1

, t

CLZ2

, t

OLZ

, t

CHZ1

, t

CHZ2

and t

OHZ

are specified with CL=5pF. Transition is measured ±500mV from steady state.

6. At any given temperature and voltage condition, t

CHZ1

is less than t

CLZ1

, t

CHZ2

is less than t

CLZ2

, t

OHZ

is less than t

OLZ.

UTRON

UT62L25716

Rev. 1.0

256K X 16 BIT LOW POWER CMOS SRAM

UTRON TECHNOLOGY INC. P80047
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: [phone] FAX: [phone]

5



WRITE CYCLE 1

(

WE

Controlled)

(1,2,3,5)

t

WC

t

AW

t

CW1

t

AS

t

WP

t

PWB

t

WH

t

OW

t

DW

t

DH

t

CW2

t

WR

Address

CE1

CE2

WE

LB , UB

Dout

Din

Data Valid

High-Z

(4) (4)

WRITE CYCLE 2

(

1CE

and CE2

Controlled)

(1,2,5)

t

WC

t

AW

t

CW1

t

AS

t

WR

t

CW2

t

WP

t

PWB

t

WHZ

t

DW

t

DH

Data Valid

Address

CE1

CE2

WE

LB , UB

Dout

Din

High-Z

Notes :

1.

WE

or

CE1

must be HIGH during all address transitions.

2. A write occurs during the overlap of a low

CE1

and a low

WE

.

3. During a

WE

controlled with write cycle with

OE

LOW, t

WP

must be greater than t

WHZ+tDW

to allow the drivers to turn off and data to

be placed on the bus.

4. During this period, I/O pins are in the output state, and input singals must not be applied.

5. If the

CE1

LOW transition occurs simultaneously with or after

WE

LOW transition, the outputs remain in a high impedance state.

6. t

OW

and t

WHZ

are specified with CL = 5pF. Transition is measured ±500mV from steady state.

UTRON

UT62L25716

Rev. 1.0

256K X 16 BIT LOW POWER CMOS SRAM

UTRON TECHNOLOGY INC. P80047
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: [phone] FAX: [phone]

6



DATA RETENTION CHARACTERISTICS

(TA = 0℃ to 70℃ / -20℃ to 80℃(E))

PARAMETER SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT

Vcc for Data Retention

V

DR

1CE

≧

V

CC

-0.2V or CE2≦0.2V

1.5 - 3.6 V

Data Retention Current

I

DR

Vcc=1.5V - L - 1 50 µA

1CE

≧ V

CC

-0.2V

or CE2≦0.2V

- LL - 0.5 20 µA

Chip Disable to Data

t

CDR

See Data Retention 0 - - ms

Retention Time

Waveforms (below)

Recovery Time

t

R

5--ms

DATA RETENTION WAVEFORM

t

CDR

t

R

V

CC

1CE

V

SS

Date Retention Mode

V

DR

≧ 1.5V

1CE

≧ V

CC

-0.2V

4.5

V

IL

V

IL

V

IH

V

IH

CE2 ≤ 0.2V

CE2

UTRON

UT62L25716

Rev. 1.0

256K X 16 BIT LOW POWER CMOS SRAM

UTRON TECHNOLOGY INC. P80047
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: [phone] FAX: [phone]

7



PACKAGE OUTLINE DIMENSION

48 pin 6.0mmX8.0mm TFBGA Package Outline Dimension

UTRON

UT62L25716

Rev. 1.0

256K X 16 BIT LOW POWER CMOS SRAM

UTRON TECHNOLOGY INC. P80047
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: [phone] FAX: [phone]

8



ORDERING INFORMATION

COMMERCIAL TEMPERATURE

PART NO. ACCESS TIME

( ns )

STANDBY CURRENT

( µA max )

PACKAGE

UT62L25716BS-55L 55 20 48 PIN BGA
UT62L25716BS-55LL 55 3 48 PIN BGA
UT62L25716BS-70L 70 20 48 PIN BGA
UT62L25716BS-70LL 70 3 48 PIN BGA

EXTENDED TEMPERATURE

PART NO. ACCESS TIME

(ns)

STANDBY CURRENT

( µA max )

PACKAGE

UT62L25716BS-55LE 55 20 48 PIN BGA
UT62L25716BS-55LLE 55 3 48 PIN BGA
UT62L25716BS-70LE 70 20 48 PIN BGA
UT62L25716BS-70LLE 70 3 48 PIN BGA

UTRON

UT62L25716

Rev. 1.0

256K X 16 BIT LOW POWER CMOS SRAM

UTRON TECHNOLOGY INC. P80047
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: [phone] FAX: [phone]

9



REVISION HISTORY

REVISION DESCRIPTION DATE

Preliminary Rev. 0.5 Original. Mar, 2001

Rev.1.0 1. Separate Industrial and Commercial SPEC.

2. New waveforms.

3. Add access time 55ns range.

4. The symbols CE1# and OE# and WE# are revised
as.

1CE

and OEand

WE

.

Jul. 12,2001

UTRON

UT62L25716

Rev. 1.0

256K X 16 BIT LOW POWER CMOS SRAM

UTRON TECHNOLOGY INC. P80047
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: [phone] FAX: [phone]

10



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